基于面积的LUT结构FPGA的工艺映射

提出了一种基于面积的针对ＬＵＴ结构ＦＰＧＡ的工艺映射算法。该算法在映射的过程中充分利用了网络节点的属性，通过计算节点的参数，采用线性规划方法给出网络的目标函数和约束条件，把一个电路网络的问题转化为纯数学的规划问题求解，映射问题转化为节点属性的分配问题，来得到最后的映射结构。与其它算法相比，该算法的映射结构较优。     

Parameterized High Throughput Function Evaluation for FPGAs

This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters, multipliers, and dividers. We discuss trade-offs involved between (1) full-lookup tables, (2) bipartite (lookup-add) units, (3) lookup-multiply units, (4) shift-and-add based CORDIC units, and (5) rational approximation. Our treatment mainly focuses on explaining method (3), and briefly covers the background of the other methods. For lookup-multiply units, we provide equations for estimating approximation errors and rounding errors which are used to parameterize the hardware units. The resources and performance of the resulting design can be estimated given the input parameters. A selection of the compared methods are implemented as part of the current PAM-Blox module generation environment. An example shows that the lookup-multiply unit produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units. Additionally, the lookup-multiply method or rational approximation can produce efficient designs for larger data widths when evaluating functions not supported by CORDIC.     

RPR中MAC处理单元的FPGA实现

弹性分组环(ResilientPacketRing)桥接芯片是弹性分组环技术在光通信领域得以运用的关键芯片,MAC地址处理是桥接芯片的一个必备的功能。分析了RPR中适用的HASH算法,介绍了MAC处理单元在FPGA中实现方法,并给出了仿真验证结果。     

Computer Evaluation of a Method for Combinational-Circuit Synthesis in FPGAs

A method is proposed for the synthesis of combinational circuits in FPGAs subject to programmable-resource utilization. The method is evaluated by computer simulation. The circuit-optimization criterion is the degree of utilization of FPGA logic units and interconnects.     

动态数据的稳健处理

本文研究了对于含有异常值的动态数据如何进行参数估计及建模的问题．详细论述了异常值的识别、检测与剔除，进而提出了一种在微机上实现稳健回归的野点剔除迭代算法，这对于建立性能优良稳定的参数模型具有广泛的实用价值。     

Visual Information Processing Based on Qualitative Mapping

1 IntroductionVisionis a most i mportant feeling modefor human be-ings and mass of ani mals.Many science andtechnical work-ers of varies of subjects have done rich research on visualinformation processing on different levels and nowit hasdeveloped into a …     

QNX实时操作系统多任务性在雷达数据处理中的应用

阐述了QNX实时操作系统的多任务特性和功能,进程管理和通讯,以及线程的创造;并给出了在单站雷达数据处理中的应用。     

Static and Dynamic Temperature-Aware Scheduling for Multiprocessor SoCs

Thermal hot spots and high temperature gradients degrade reliability and performance, and increase cooling costs and leakage power. In this paper, we explore the benefits of temperature-aware task scheduling for multiprocessor system-on-a-chip (MPSoC). We evaluate our techniques using workload characteristics collected from a real system by Sun's Continuous System Telemetry. We first solve the task scheduling problem statically using integer linear programming (ILP). The ILP solution is guaranteed to be optimal for the given assumptions for tasks. We formulate ILPs for minimizing energy, balancing energy, and reducing hot spots, and provide an extensive comparison of their thermal behavior against our technique. Our static solution can reduce the frequency of hot spots by 35%, spatial gradients by 85%, and thermal cycles by 61% in comparison to the ILP for minimizing energy. We then design dynamic scheduling policies at the OS-level with negligible performance overhead. Our adaptive dynamic policy reduces the frequency of high-magnitude thermal cycles and spatial gradients by around 50% and 90%, respectively, in comparison to state-of-the-art schedulers. Reactive thermal management strategies, such as thread migration, can be combined with our scheduling policy to further reduce hot spots, temperature variations, and the associated performance cost.      

Reconfigurable architectures for bio-sequence database scanning on FPGAs

Protein sequences with unknown functionality are often compared to a set of known sequences to detect functional similarities. Efficient dynamic-programming algorithms exist for solving this problem, however current solutions still require significant scan times. These scan time requirements are likely to become even more severe due to the rapid growth in the size of these databases. In this paper, we present a new approach to bio-sequence database scanning using re-configurable field-programmable gate array (FPGA)-based hardware platforms to gain high performance at low cost. Efficient mappings of the Smith-Waterman algorithm using fine-grained parallel processing elements (PEs) that are tailored toward the parameters of a query have been designed. We use customization opportunities available at run time to dynamically reconfigure the PEs to make better use of available resources. Our FPGA implementation achieves a speedup of approximately 170 for linear gap penalties and 125 for affine gap penalties compared to a standard desktop computing platform. We show how run-time reconfiguration can be used to further improve performance.     

High Performance Static Segment On-Chip Memory for Image Processing Applications

The performance of the processor core depends on the configuration parameters and utilization of on-chip memory in multimedia applications such as image, video and audio processing. The design of the on-chip memory architecture is critical for power and area efficient design without compromising quality in data-intensive computing applications. This paper proposes a design of high speed, area, and energy efficient Static Segment On-Chip (SSOC) memory for error-tolerant applications. In this static segment method, n-bit data array is reduced by m-bit data array for significant value of input data to achieve balanced design metrics at the cost of accuracy. The proposed m-bit static segmentation algorithm is implemented and verified in Single Port Static Random Access Memory (SP SRAM) architecture for the approximate computing applications. From the overall simulation results, the proposed 4-bit SSOC SP SRAM design provides 49.02% area savings, 50.62% power reduction and 16.92% speed improvement at the cost of 0.64% Peak Signal to Noise Ratio (PSNR) and exhibits same visual quality in comparison with the existing 8-bit conventional on-chip SP SRAM design in the image processing applications.     

基于DSP的实时多任务调度内核设计

随着处理器（DSP,Digital Signal Processor）芯片在支持多任务系统中的广泛应用,传统DSP软件架构已不能满足要求。文中介绍了一个用于DSP芯片的实时多任务调度内核的实现方法。该内核是一种支持多任务、MMU和消息机制的调度内核,内核架构简洁,代码量小,占用内存少,执行效率高,完全由C语言开发,可方便地在TI公司的各种DSP上移植,可以大大加快软件开发速度,提高软件的灵活性,使DSP软件开发工作变得简单、快速。     

等离子显示器动态图像处理技术

在说明彩色等离子体显示原理的基础上，阐述彩色PDP产生图像动态假轮廓现象的原因，并初步探讨了抑制这一现象的几种基本方法。     

Low Cost BIST for Static and Dynamic Testing of ADCs

This paper presents a low cost test method for the static and dynamic characterization of analog-to-digital converters. The method is suitable for implementation in a SoC environment, as a built-in self test (BIST) solution. In the proposed approach, noise is used as the test signal. Theory of operation and practical results demonstrating the effectiveness of the method for INL, DNL, THD and SINAD characterization are presented. The BIST surface overhead caused by the noise generator is only 7.4% of the ADC total area. The reduced number of data samples required allows a reduction of about 7.5× in test time, in comparison to the histogram method.Maria da Gloria Cataldi Flores was born in Santa Maria, Brazil, in 1978. She received the electrical engineering degree in 2000 from Universidade Federal de Santa Maria (UFSM) and the M.S. degree engineering in 2003 from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then, she has been working as a design engineer in an EAS Supply brazilian company. Her main research interests include mixed-signal and analog testing and digital signal processing.Marcelo Negreiros was born in Porto Alegre, Brazil, in 1969. He received the electrical engineering degree in 1992 and the M.S. degree engineering in 1994, both from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. Since then he was been working as an associate researcher in the Signal Processing Lab. (LaPSI) of the Electrical Engineering Department at UFRGS. Since 2000 he also works toward a Ph.D. in Computer Science from UFRGS. His main research interests include mixed-signal and analog testing and digital signal processing.Luigi Carro was born in Porto Alegre, Brazil, in 1962. He received the Electrical Engineering and the M.Sc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1985 and 1989, respectively. From 1989 to 1991 he worked at ST-Microelectronics, Agrate, Italy, in the R&D group. In 1996 he received the Ph.D. degree in the area of Computer Science from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design and Digital Signal processing disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible for courses in Embedded Systems, Digital Signal Processing, and VLSI Design. His primary research interests include mixed-signal design, digital signal processing, mixed-signal and analog testing, and fast system prototyping. He has published more than 90 technical papers in those topics and is the author of the book Digital Systems Design and Prototyping (in portuguese).Altamiro A Susin was born in Vacaria-RS, Brazil, in 1945. He received the Electrical Engineering and the MSc. degrees from Universidade Federal do Rio Grande do Sul (UFRGS), Brazil, in 1972 and 1977, respectively. Since 1968 he worked in the start up of Computer Centers of two local Universities. In 1981 he got his Dr. Eng degree from Institut National Polytechnique de Grenoble-France. He is presently a lecturer at the Electrical Engineering Department of UFRGS, in charge of Digital Systems Design disciplines at the graduate and undergraduate level. He is also a member of the Graduation Program in Computer Science of UFRGS, where he is responsible by courses in VLSI Architecture and is also thesis director. His main research interests are Integrated Circuit Architecture, Embedded Systems, Signal Processing with more than 50 technical papers published in those domains. He is/was responsible for several R&D projects either funded with public and/or industry resources.Felipe Ricardo Clayton received the B.S. degree in Electrical Engineering from State University of Campinas (UNICAMP), Brazil, in 1986. He worked at CPqD (Brazilian PTT R&D Center) till 1996 designing analog and mixed signal circuits for telecom and automotive applications. From 1997 to the second half of 1998, he worked at Instituto Superior Técnico (IST), Lisbon, Portugal, under the guidance of Prof. Carlos Azeredo Leme on development of CMOS RF circuits. Since October 1998 he had worked for Motorola SPS. Now he is head of the Power Managment Group at Freescale.Cristiano Benevento received his B.S. degree in Electrical Engineering from Universidade Estadual de Campinas (Unicamp), Brazil, in 1997. He worked at Motorola Cellular Infrastructure Group until August 2000 as a Systems Engineer. He joined Motorola Semiconductor Product Sector in August 2000 as IC Designer for Power Management Group and is now at Freescale.     

Hardware Acceleration of HMMER on FPGAs

We propose a new parallelization scheme for the hmmsearch function of the HMMER software, in order to target FPGA technology. hmmsearch is a very compute intensive software for biological sequence alignment, based on profile hidden Markov models. We derive a flexible, generic, scalable hardware parallel architecture which can accelerate the core of hmmsearch by nearly two orders of magnitude, without modifying the original algorithm of this software. Our derivation is based on the expression of the algorithm as a set of recurrence equations, and we show in a systematic way how a very efficient parallel version of the algorithm can be found by combining scheduling, projection, partitioning, pipelining and precision analysis. We present the performance of the implementation of this parallel algorithm on a FPGA platform.     

基于FPGA的液晶模组设计

从液晶模组产品化设计考量,介绍了一种以FPGA为核心的整体液晶模组设计方案。方案从客户需求分析入手,进行器件选型,附加功能开发,进而完成整体的硬件与软件架构;设计相关实验,进行产品可靠性验证。实验可采用FPGA自身产生信号画面源,亦可采用外部信号画面源。     

Xilinx FPGA的功耗优化设计

对于FPGA来说,设计人员可以充分利用其可编程能力以及相关的工具来准确估算功耗,然后再通过优化技术来使FPGA设计以及相应的PCB板在功率方面效率更高。静态和动态功耗及其变化 在90nm工艺时,电流泄漏问题对AISC和FPGA都变得相当严重。在65nm工艺下,这一问题更具挑战性。为获得更高的晶体管性能,必须降低阈值电压,但同时也加大了电流泄漏。     

雷达软件代码静态质量度量方法

通过软件静态质量分析可以定量评价软件代码的质量。文章通过对软件代码静态质量度量模型的研究,考虑质量准则在不同度量范围间的传递,结合雷达软件代码质量的关注点,提出雷达软件静态质量度量方法,以量化数据表示代码的质量水平,并以玫瑰图的形式表示出来。试验结果表明,新的度量方法能够有效地对软件静态质量进行度量,为设计师了解软件代码质量水平提供了客观依据,减少了软件质量评估中的主观性。     

Dynamic Threshold Delay Characterization Model for Improved Static Timing Analysis

Transistors within a gate take a finite amount of time to switch and hence there is always a propagation delay associated with it. These delays are evaluated by standard cell characterization techniques using EDA tools. However, these standard measurement methods tend to fail when simulating the design with practical values of slope and load and gives rise to the problem of negative or non-monotonic delays. Negative/non-monotonic delays lead to false positives during static timing analysis, synthesis and simulation of circuits and are undesirable. Hence, there is a need to implement new methods for characterization of propagation delay that will lead to more realistic monotonic delay values, ultimately achieving early timing closures. One such method of delay measurement based on actual switching thresholds has been proposed in this work.     

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the model: 1) static offset voltages from the mismatch in $muhbox{C}_{rm ox}$ and threshold voltage ${rm V}_{rm th}$ and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25- $mu{hbox {m}}$ and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of “Lewis-Gray” structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.