Statistical Properties of Timing Jitter in a PAM Timing Recovery Scheme

A new technique is presented for evaluating the performance of a popular type of timing recovery circuit for baseband synchronous pulse amplitude modulation (PAM) data signals. The timing circuit consists of a square-law device followed by a narrowband filter tuned to the pulse repetition frequency along with provision for reshaping the pulses entering the timing path (prefiltering). The output of the timing circuit is a nearly sinusoidal timing wave whose zero crossings indicate the appropriate sampling instants for demodulation of the PAM signal. For a random data sequence, the timing wave exhibits phase fluctuations which are strongly dependent on the pulse shapes entering the timing path and the passband shape of the narrow-band filter. Expressions for rms phase fluctuation in the timing wave as a function of the prefiltering and postfiltering characteristics of the filters preceding and following the square-law device are presented. These expressions have a form which is especially suitable for studying the case where the baseband PAM signal is band-limited to frequencies less than the pulse repetition frequency. A condition on prefiltering and postfiltering which gives error-free timing recovery is presented. Results obtained from some specific examples serve to illustrate several aspects of the timing recovery problem.     

Timing and geodesy

Geodetic science (geodesy) is that branch of science concerned with determining the size, shape, and gravitational field of the earth, and precisely mapping its surface features. Astronomic observations provide essential information in the geodetic process. Both the earth-based observing stations and the observed extraterrestrial bodies (stars, planets, natural and artificial earth satellites) are in motion, creating time-dependent coordinate systems and making epoch, interval, and synchronization important. Modern geodesy uses the most sophisticated optical and electronic equipment in measurements, and the timing requirements have become increasingly stringent. Systems that require accurate timing often have potential in the determination of time. Lunar laser ranging, a currently developing technique with many exciting geodetic implications, may develop into a practical method for the determination of Universal Time (UT1) to a new order of accuracy.     

Timing driven gate duplication

In the past few years, gate duplication has been studied as a strategy for cutset minimization in partitioning problems. This paper addresses the problem of delay optimization by gate duplication. We present an algorithm to solve the gate duplication problem. It traverses the network from primary outputs(PO) to primary inputs(PI) in topologically sorted order evaluating tuples at the input pins of gates. The tuple's first component corresponds to the input pin required time if that gate is not duplicated. The second component corresponds to the input pin required time if that gate were duplicated. After tuple evaluation the algorithm traverses the network from PI to PO in topologically sorted order, deciding the gates to be duplicated. The last and final traversal is again from PO to PI, in which the gates are physically duplicated. Our algorithm uses the dynamic programming structure. We report delay improvements over other optimization methodologies. Gate duplication, along with other optimization strategies, can be used for meeting the stringent delay constraints in today's ultra complex designs.     

关于GPS单星定时提高定时精度的研究

为满足特殊用户或固定站点对高精度定时信息的需求,文中重点研究位置已知情况下基于卡尔曼滤波算法的GPS单颗星定时的方法。理论分析及仿真结果表明：与位置未知时四颗星联合定位／定时方法相比,位置已知情况下单颗星定时的精度优于位置未知时多星联合定位定时的时间精度,同时,利用观测到的多颗GPS卫星分别进行单星定时得到的信息,可进一步提高时间精度。     

MIMO-OFDM系统定时同步算法

应用MIMO—OFDM无线通信系统的空间信号资源，提出了基于单个前导符号的MIMO--OFDM系统帧定时和符号定时同步的分集算法，以克服高速无线多径信道中深衰落对MIMO—OFDM系统定时同步性能的影响，给出了具体的帧定时、符号定时同步的分集算法以及在高速无线多径信道COST207模型下帧定时和符号定时同步的仿真结果。     

Timing characterization and constraining tool

This paper presents Timing Characterization and constraining Tool (TCT) that facilitates designing of modular reconfigurable Integrated Circuits (ICs) by supporting early constraint-based design space exploration and timing constraining. These steps of the design methodology are crucial from the perspective of quality of results and are not directly addressed by the synthesis tools used nowadays.     

Utilizing Redundancy for Timing Critical Interconnect

Conventionally, the topology of signal net routing is almost always restricted to Steiner trees, either unbuffered or buffered. However, introducing redundant paths into the topology (which leads to non-tree) may significantly improve timing performance as well as tolerance to open faults and variations. These advantages are particularly appealing for timing critical net routings in nanoscale VLSI designs where interconnect delay is a performance bottleneck and variation effects are increasingly remarkable. We propose Steiner network construction heuristics which can generate either tree or non-tree with different slack-wirelength tradeoff, and handle both long path and short path constraints. We also propose heuristics for simultaneous Steiner network construction and buffering, which may provide further improvement in slack and resistance to variations. Furthermore, incremental non-tree delay update techniques are developed to facilitate fast Steiner network evaluations. Extensive experiments in different scenarios show that our heuristics usually improve timing slack by hundreds of pico seconds compared to traditional approaches. When process variations are considered, our heuristics can significantly improve timing yield because of nominal slack improvement and delay variability reduction.     

罗兰C天波授时信号研究

介绍了长波天波传播特性,阐述了罗兰C天波信号实测试验的原理,通过对试验数据的研究分析,得出罗兰C天波信号覆盖范围、修正精度及昼夜变化规律,给出了天波使用的有关建议。     

SoC静态时序分析中时序约束策略的研究及实例

文章简要描述了静态时序分析的原理，并在一款音频处理SoC芯片的验证过程中，详细介绍了针对时钟定义、多时钟域、端口信号等关键问题的时序约束策略。实践结果表明，静态时序分析很好地满足了该芯片的验证要求．而且比传统的动态验证效率更高。     

Timing Recovery in Digital Subscriber Loops

Tradeoffs in the design of the timing recovery functions in a subscriber loop receiver are analyzed. The techniques considered are applicable to both the echo cancellation (EC) and time compression multiplexing (TCM) methods of full duplex transmission. Emphasis is on those techniques that lend themselves to implementation in MOSLSI technology, where the objective requirement is that timing recovery be implemented on a sampled-data signal (with the minimum possible sampling rate where EC is used). The wave difference method (WDM) for timing recovery appears to be the best candidate. A detailed study of its performance is carried out analytically and by computer simulation for the case of binary and alternate mark-inversion (AMI) line coding. A closed form expression describing the binary jitter performance of the WDM and its continuous time counterpart, the spectral line technique, is used to compare the two techniques. Analytical and simulation results for recovered phase and jitter are presented for various cable pulse responses carefully chosen to represent worst-case or nearly worst-case conditions. Two methods for including frequency detection in the WDM, the quadricorrelator and the rotational detector, are also simulated.     

Performance Limits in DS-CDMA Timing Acquisition

This paper addresses timing acquisition aspects in direct-sequence code division multiple access (DS-CDMA) systems. Various chip waveform shaping schemes are considered, including both one-chip long full-response pulses, and partial-response ones occupying several chip periods. Different figures of merits are considered in a comparative analysis that seeks to establish performance limits in terms of correct timing detection capability, false alarm rate, bandwidth occupancy, multiple-access interference (MAI), and inter-chip interference (ICI). A waveform design algorithm is formulated to optimize system performance in terms of signal-to-interference-ratio (SIR) subject to other signalling constraints, and a solution based on the use of prolate spheroidal wave functions (PSWF) is derived. Numerous waveform design examples are then constructed to illustrate acquisition detection capability versus system load for both faded and unfaded cases. A comparative assessment of the performance of conventional signalling waveforms against the optimized ones is also presented. In particular, the numerical results show that the half-sine pulse used in minimum shift keying (MSK) is quasi-optimal within the full-response category, while root-raised cosine (RRC) Nyquist filtering with 22% rolloff (used in third generation CDMA standards) is also close to optimal when considering many-chip-long pulses.     

时延驱动的VLSI版图规划算法

本文提出了时延驱动布图规划的思想。在用改进的广义力矢量法优化功能单元间连线时延的同时，运算非线性规划的方法进一步优化关键路径上功能单元的时延及连线时延。结果表明，这是一种有效的优化版图时延的方法。     

基于TQ时序分析器的时序分析和约束

静态时序分析是FPGA系统设计中最常用的分析、调试时序性能的方法和工具,TimeQuest（TQ）时序分析器作为Altera公司的第二代静态时序分析器,得到了业界广泛的应用和关注。本文在解释了何为静态时序分析的基础上,介绍了基于TQ的时序分析和约束。     

OFDM系统中定时偏移的估计技术

在T.M.Schmidl和D.C.Cox提出的解决正交频分多路复用（OFDM）系统定时同步的基础上,给出了两种改进算法。在加性高斯白噪声信道（AWGN）和存在符号间干扰（ISI）的两种信道中,分别对估值进行比较,这两种改进算法得到估值的方差要小得多。     

Timing modeling of latch-controlled sub-systems

We present a new timing model for latch-controlled sub-systems, referred to as the advanced black box model. The proposed model considers the transparency characteristics of latches in modeling and uses only the constraints on input signals and the characteristics of output departure time to represent the timing characteristics of the latch-controlled sub-system. Thus, it can be used for the efficient timing verification of the IP-based SoC design without re-verifying the internal timings of pre-verified Intellectual Properties (IPs) at the lower level. We also present an efficient algorithm to characterize the proposed model, which enables us to perform the timing characterization and verification of the given system simultaneously. The worst-case complexity of the entire characterization process is O(P×N²), where P and N are the numbers of primary inputs and latches in the system.     

Timing of some fast DFT-algorithms

Timing experiments of 6 fast DFT-algorithms are performed on 3 computers. Results show that the complexity of an algorithm in terms of the number of multiplications and additions is not a satisfactory measure for the speed of a DFT-algorithm.     

一种数据辅助的前向位定时估计算法

以平方法为代表的非数据辅助(NDA)类前向位定时估计算法在低信噪比和小成性系数场合估计性能严重恶化,而采用数据辅助(DA)类估计是值得考虑的选择。但传统的数据辅助类算法需要大量的搜索以获取位定时的精确估计,运算量大实现困难。本文将三角内插技术应用于位定时估计,提出了一种新的数据辅助前向位定时估计算法,该算法简单、便于实现。仿真结果表明,本文算法估计性能逼近修正卡美罗界(MCRB),且对成形滚降系数不敏感,适合于低信噪比突发通信。最后,本文针对突发信号给出了前导码捕获与位定时估计一体化的实现结构。      

Timing Recovery for Backplane Ethernet

The dominant solutions for single-chip multi-port backplane Ethernet transceivers utilize a dual-loop design - a combination of a single master phase-locked loop (PLL) and multiple slave delay-locked loops (DLL). Each transmitter or receiver port has its own DLL, which delays or advances a copy of the master clock from the master PLL to generate its own clock signal for synchronization. The DLLs are typically implemented using current-mode logic phase interpolators. This paper presents an alternative solution to this synchronization problem. Instead of moving the sampling phase, timing recovery is done by changing the group delay of the receiver-side forward equalizer by rotating its tap coefficients. The standard least-mean-square algorithm is used for coefficient rotation. This solution is equivalent to a first-order PLL/DLL, which suffers from steady-state timing offset when there is a frequency offset between the transmitter and the receiver. However, the degradation in performance caused by a frequency offset is significantly reduced by using a coefficient-rotation digital-signal processor capable of detecting and reducing the offset. With a practical frequency accuracy specification of plusmn100 ppm, the improved performance can approach that of the PLL/DLL dual-loop solution.     

Timing Synchronization in Decode-and-Forward Cooperative Communication Systems

Cooperative communication systems have attracted much attention recently due to their desirable performance gain while using single antenna terminals. This paper addresses the joint timing and channel estimation problem, and furthermore the resynchronization of multiple timing offsets in a cooperative relay system. The estimations of timing and channel are conducted in two phases and the associated CramÉr-Rao bounds (CRB) are derived for both phases. It is demonstrated that the conventional CRB is not valid for timing parameters under fading conditions, and a new bound called Weighted Bayesian CRB is proposed. With the timing and channel estimates, a general framework of the resynchronization filter design is developed in order to compensate the multiple timing offsets at the destination. The proposed methods are applied to different scenarios with varying degrees of timing misalignment and are numerically shown to provide excellent performances that approach the perfectly synchronized case.      

On Timing Offset Estimation of OFDM

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