A fast parallel implementation of elliptic curve point multiplication over GF(2m)

A fast parallel architecture for the implementation of elliptic curve scalar multiplication over binary fields is presented. The proposed architecture is implemented on a single-chip FPGA device using parallel strategies that trades area requirements for timing performance. The results achieved show that our proposed design is able to compute GF(2191) elliptic curve scalar multiplication operations in 63 μs.     

High performance hardware support for elliptic curve cryptography over general prime field

Secure information exchange in resource constrained devices can be accomplished efficiently through elliptic curve cryptography (ECC). Due to the high computational complexity of ECC arithmetic, a high performance dedicated hardware architecture is essential to provide sufficient performance in a computation of elliptic curve scalar multiplication. This paper presents a high performance hardware support for elliptic curve cryptography over a prime field GF(p). It exploited a best available possible parallelism of elliptic curve points in projective representation. The proposed hardware for ECC is implemented on Xilinx Virtex-4, Virtex-5 and Virtex-6 FPGAs. A 256-bit scalar multiplication is completed in 2.01  ms, 2.62  ms and 3.91  ms on Virtex-6, Virtex-5 and Virtex-4 FPGA platforms, respectively. The results show that the proposed design is 1.96 times faster with insignificant increase in area consumption as compared to the other reported designs. Therefore, it is a good choice to be used in many ECC based schemes.     

针对椭圆曲线密码系统点乘算法的改进差分故障攻击

针对故障攻击椭圆曲线点乘算法失效问题,提出一种改进的差分故障攻击算法。该算法消除了非零块的假设,并引入验证机制抵抗了“故障检测”失效威胁。以SM2算法提供的椭圆曲线为例,通过软件仿真成功攻击了二进制点乘算法、二进制非相邻型（NAF）点乘算法和蒙哥马利点乘算法,3小时内恢复出了256比特私钥。针对二进制NAF点乘算法攻击过程进行了优化,将攻击时间缩短至原来的五分之一。实验结果表明,所提算法能够提高攻击的有效性。     

一种快速的椭圆曲线标量乘方法

该文提出并实现了一种快速的椭圆曲线标量乘方法。理论分析与实验结果表明,该方法安全、有效。例如,对于160位的大整数标量乘,与固定基窗口方法相比,其实现速度提高了82.5%。     

An area/performance trade-off analysis of a GF(2) multiplier architecture for elliptic curve cryptography

A hardware architecture for GF(2^m) multiplication and its evaluation in a hardware architecture for elliptic curve scalar multiplication is presented. The architecture is a parameterizable digit-serial implementation for any field order m. Area/performance trade-off results of the hardware implementation of the multiplier in an FPGA are presented and discussed.     

椭圆曲线标量乘算法的改进

椭圆曲线密码体制的快速实现依赖于标量乘(nP)的有效计算,该文改进 的二进制和三进制的混合表示方法,并且将其推广到 的二进制、三进制和五进制的混合表示。该算法在已知二倍点、三倍点和五倍点运算量的基础上,经过恰当的运算计算标量乘。试验结果表明,该算法减少计算标量乘的运算量,能有效地计算标量乘。     

一种灵活的椭圆曲线密码并行化方法

提出标量划分与整合模型,基于此模型,提出一种灵活的椭圆曲线密码标量乘的并行化处理方法。由于该方法是基于标量乘的算法操作级别,因此能在各种不同处理器数量的并行系统中实现。相对于现有的基于固定数量处理器的标量乘并行化方法,本文的并行化方法是灵活的。同时,本文提出的标量乘并行化方法最优时间复杂度可以减少到(logk)A+kD。通过实例比较,本文提出的方法的最优时间复杂度比经典的二进制方法减少了大约30%。     

一个改进的多点乘算法

SPA(Simple Power Analysis)攻击可能通过泄露的信息获取内存受限制的设备(如smart卡)中的密钥,它是通过区分一次点乘运算中点加运算和倍点运算进行的。抗SPA攻击的点乘算法较多,但对于多点乘算法相关措施较少。inter-leaving多点乘算法是一个时间和空间效率都非常优秀的多点乘算法。为此提出一种基于interleaving的抗SPA攻击的多点乘算法,新的算法在内存空间消耗和计算速度上较原算法负担增加可以忽略不计,而且能够抗SPA攻击。     

抗SPA的多点乘算法

SPA(Simple Power Analysis)攻击可能通过泄露的信息获取内存受限制的设备中的密钥,它是通过区分一次点乘运算中点加运算和倍点运算进行的。抗SPA攻击的点乘算法较多,但对于多点乘算法相关措施较少。Sharmir-NAF多点乘算法是一个时间和空间效率都非常优秀的多点乘算法。为此提出一种基于Sharmir-NAF的抗SPA攻击的多点乘算法。新的算法在内存空间消耗和计算速度上较原算法负担增加可以忽略不计,而且能够抗SPA攻击。     

基于半点运算与多基表示的椭圆曲线标量乘法

椭圆曲线密码体制的实现速度依赖于曲线上标量乘法的运算速度。在具有极小2-挠的椭圆曲线上基于半点运算的标量乘法算法优于传统的标量乘法算法。该文将半点运算运用于基于多基表示的标量乘法算法中,得到一种新的多基表示形式和基于该表示形式的标量乘法算法,有效提高了标量乘法的运算效率。     

A Synthesis of Multi-Precision Multiplication and Squaring Techniques for 8-Bit Sensor Nodes: State-of-the-Art Research and Future Challenges

Multi-precision multiplication and squaring are the performance-critical operations for the implementation of public-key cryptography, such as exponentiation in RSA, and scalar multiplication in elliptic curve cryptography (ECC). In this paper, we provide a survey on the multi-precision multiplication and squaring techniques, and make special focus on the comparison of their performance and memory footprint on sensor nodes using 8-bit processors. Different from the previous work, our advantages are in at least three aspects. Firstly, this survey includes the existing techniques for multiprecision multiplication and squaring on sensor nodes over prime fields. Secondly, we analyze and evaluate each method in a systematic and objective way. Thirdly, this survey also provides suggestions for selecting appropriate multiplication and squaring techniques for concrete implementation of public-key cryptography. At the end of this survey, we propose the research challenges on efficient implementation of the multiplication and the squaring operations based on our observation.     

Efficient implementation of modular multiplication over 192-bit NIST prime for 8-bit AVR-based sensor node

Modular multiplication is one of the most time-consuming operations that account for almost 80% of computational overhead in a scalar multiplication in elliptic curve cryptography. In this paper, we present a new speed record for modular multiplication over 192-bit NIST prime P-192 on 8-bit AVR ATmega microcontrollers. We propose a new integer representation named Range Shifted Representation (RSR) which enables an efficient merging of the reduction operation into the subtractive Karatsuba multiplication. This merging results in a dramatic optimization in the intermediate accumulation of modular multiplication by reducing a significant amount of unnecessary memory access as well as the number of addition operations. Our merged modular multiplication on RSR is designed to have two duplicated groups of 96-bit intermediate values during accumulation. Hence, only one accumulation of the group is required and the result can be used twice. Consequently, we significantly reduce the number of load/store instructions which are known to be one of the most time-consuming operations for modular multiplication on constrained devices. Our implementation requires only 2888 cycles for the modular multiplication of 192-bit integers and outperforms the previous best result for modular multiplication over P-192 by a factor of 17%. In addition, our modular multiplication is even faster than the Karatsuba multiplication (without reduction) which achieved a speed record for multiplication on AVR processor.

     

有限域GF(2m)上椭圆曲线密码体制的快速实现

椭圆曲线密码体制的快速实现是当前公钥密码体制研究的热点之一。椭圆曲线上点的标量乘和加法运算是椭圆曲线密码算法的核心运算。为了提高运算速度,利用射影坐标思想,改进椭圆曲线上求两点和运算公式,对标量乘算法进行优化。讨论了椭圆曲线密码体制的优势及研究其快速实现的意义。     

适合资源受限环境的GF(2m)域上乘法器结构

椭圆曲线密码体制因其每比特最大的安全性受到越来越广泛的重视。而有限域上的乘法运算,成为决定椭圆曲线上的标量乘法运算速度的主要因素。文中基于Massey-Omura乘法器,和另外一种并行乘法器,提出了一种新型的有反馈的并行乘法器结构,结构需要8(m-1)个异或门和(8m-7)个与门。比起原来的乘法器,门数有了很大的减少。因此这种结构比较适合资源受限的环境中应用。     

并行设计的高性能随机椭圆曲线加密协处理器

为加速椭圆曲线加密的运算,本文提出了一种新的并行设计的椭圆曲线加密处理器结构。该处理器采用的模运算单元的特点是含有两个模乘、一个模加和一个模平方模块。两个模乘可以并行运算,而且在模乘运算的同时可并行完成模加或模平方的运算。Xilinx公司的VirtexE XCV2600 FPGA硬件实现结果表明,完成有限域GF(2163)上任意椭圆曲线上的一次标量乘的全部运算只需3064个时钟,时间消耗为31.17μs,资源消耗为3994个寄存器和15527个查找表,适合高性能椭圆曲线加密应用的要求。     

利用半点计算椭圆曲线双标量乘法算法

实现椭圆曲线密码体制最主要的运算是椭圆曲线点群上的标量乘法(或点乘)运算。一些基于椭圆曲线的密码协议比如ECDSA签名验证,就需要计算双标量乘法kP+lQ,其中P、Q为椭圆曲线点群上的任意两点。一个高效计算kP+lQ的方法就是同步计算两个标量乘法,而不是分别计算每个标量乘法再相加。通过对域F2m上的椭圆曲线双标量乘法算法进行研究,将半点公式应用于椭圆曲线的双标量乘法中,提出了一种新的同步计算双标量乘法算法,分析了效率,并与传统的基于倍点运算的双标量乘法算法进行了详细的比较,其效率更优。     

基于多基表示的滑动窗口椭圆曲线多标量乘算法

标量乘运算从整体上决定了椭圆曲线密码体制的快速实现效率，在一些椭圆曲线公钥密码体制中需要计算多标量乘。多基数链的标量表示长度更短、非零比特数目更少，较好地适用于椭圆曲线标量乘的快速计算。为了提高椭圆曲线密码的效率，在已有的二进制域和素域的标量乘算法的基础上，结合滑动窗口技术、多基算法，提出新的更高效的多标量乘算法。实验结果表明，新算法与传统Shamir算法和交错NAF算法相比，其所需的运算量更少，能有效地提高椭圆曲线多标量乘算法的效率，使多标量乘的运算更高效。相比于其他算法，新算法的计算效率比已有的多标量乘算法提高了约7.9%~20.6%。     

有限域GF(2m)上ECDSA算法的优化

椭圆曲线数字签名算法(ECDSA)是数字签名算法(DSA)在椭圆曲线密码体制中的实现,其安全性依赖于椭圆曲线离散对数问题(ECDLP)的难解性。该文介绍了ECDSA在有限域GF(2m)上的实现,利用射影坐标思想,改进椭圆曲线上求两点和运算公式,对点乘算法进行优化,有效地提高了数字签名和签名验证的速度。     

素数域椭圆曲线密码系统算法实现研究

针对素数域椭圆曲线密码系统的算法高速实现，分别讨论了对椭圆曲线上的点的加法和倍点运算。以及对点的标量乘法运算进行优化的技术，同时给出了测试比较结果，说明了所讨论的优化技术可以大大提高整个椭圆曲线密码系统的算法实现性能。     

椭圆曲线中抗SPA和DPA攻击标量乘算法研究

标量乘法的效率和安全性是椭圆曲线密码体制的瓶颈问题,针对椭圆曲线上标量乘法的实现方法,对普通抗SPA和DPA攻击的标量乘算法进行了研究,并提出一种改进算法。改进算法引入随机变量,将标量进行编码,采用点的底层域快速算法和滑动窗口算法,达到兼顾效率和安全性的目标。当滑动窗口长度为4,标量的二进制位长分别为160、192和224 bit时,改进算法效率分别提高了26.9%,21.5%和27.2%。