Planar normally-off GaAs JFET for high speed logic circuits

Normally-off JFETs with 1.3 ?m-long gates were fabricated by selective double ion implantation for the n and n+ regions and selective Zn diffusion for the p-gate area. A JFET with a 10 ?m-wide gate had a transconductance of 2 mS in average and a high value of 3 mS. A 15 stage ring oscillator made of resistively loaded DCFLs showed the minimum delay time of 45 ps, the shortest value obtained based on optical lithography. The minimum power-delay product was 3.8 fJ with a delay time of 83 ps.     

Design and performance of GaAs normally-off MESFET integrated circuits

DC and transient analyses of GaAs normally-off MESFET integrated circuits are described. The design tradeoffs between device parameters and logic characteristics are discussed for an inverter with a resistive load. By increasing the supply voltage to several times that of the built-in voltage, the propagation delay time can be lowered similar to that when using an active load (current source). To investigate the speed-power performance of the IC's, ring oscillators with different fan-in and fan-out configurations were fabricated. A binary frequency divider which uses a master-slave flip-flop was tested. The maximum counting frequency of the divider was 610 MHz at a supply voltage of 1.5 V. This coincides with the results obtained from the ring oscillators with fan-in/fan-out = 2/2. Comparing the experimental results with the theory, the effective electron mobility in the thin channel layer is expected to be very low. By improving the mobility and shortening the gate length to half a micrometer, practical functioning circuits should operate with an average propagation delay time of less than 100 ps.     

Dependence of GaAs power MESFET microwave performance on device and material parameters

The results of recent X-band measurements on GaAs Power FET's are described. These devices are fabricated with a simple planar process and at least 1-W output power at 9 GHz with 4-dB gain has been obtained from more than 25 slices having carrier concentrations in the range 5 to 15 × 10¹⁶cm^-3. The highest output powers observed to date are 1.0 W at 11 GHz and 3.6 W at 8 GHz with 4-dB gain. Devices have had up to 46-percent power-added efficiency at 8 GHz. The fabrication process is briefly described and the factors contributing to the high output powers reported here are discussed. Some of these factors are epitaxial carrier concentration near 8 × 10¹⁶cm^-3, good device heatsinking, and low parasitic resistance. The observed dependence of microwave performance on total gate width, gate length, pinchoff voltage, epitaxial doping level, etc., is described.     

High performance GaAs JFET with shallow implanted Cd-gate

Shallow p⁺-regions in GaAs, formed by Cd ion implantation, have been used as the gate region for GaAs JFETs. 0.7 μm gate length JFETs demonstrated a transconductance of 165 mS/mm a saturation current of 130 mA/mm, an f_t of 26 GHz, and an f _max of 42 GHz. These frequency metrics are superior to previous Zn-gate JFETs of similar dimensions     

Optimization of n+ self-aligned short-channel normally-off GaAs MESFETs by two-dimensional numerical device simulation

The behaviour of n⁺ self-aligned short-channel normally-off GaAs MESFETs with increasing channel doping concentration is investigated by detailed computer simulation. Characteristic data of n⁺ self-aligned technology like n⁺-gate spacing and projected range of n⁺-implant are optimized. For the calculation a two-dimensional numerical GaAs device simulation program developed at Dresden University of Technology is used. Increasing channel doping concentration up to 10¹⁸ cm⁻³ decreases sensitivity of threshold voltage upon gate length by about 25–30%. Furthermore, transconductance and K-value are increased by more than twofold. A transconductance of 610 mS/mm was calculated for a GaAs normally-off MESFET with 0.5 μm gate. This is a remarkably high value for MESFETs.     

A GaAs memory device utilizing a buried JFET channel fornondestructive charge sensing

A new GaAs memory cell consists of a monolithic element in which a P-i-N-i-P epitaxial structure stores charge and a buried p-channel FET senses charge. Measured storage times up to 40 s were observed at 300 K with minimal effects on charge decay for applied drain voltages of V _DS=±1.5 V. Electrical write and erase techniques are demonstrated and discussed     

Charge storage in vertically integrated GaAs n-channel JFET/junction capacitor device

A GaAs vertical npn structure in which the bottom layer serves as a JFET charge sensing channel has been fabricated and tested as a dynamic memory element. The device can be read nondestructively and exhibits tens of seconds storage times at room temperature. Use of an n channel for sensing charge provides increased sensitivity compared to an earlier p-channel device.<>     

Assessing GaAs high-speed-switching JFET device models: 1- versus 2-dimensional analysis

The general results and conclusions of these researchers and others investigating 1- and 2-dimensional device models for high-speed low-power GaAs switching JFET's are briefly reviewed and summarized. Guidelines for assessing 1- or 2-dimensional device model adequacy based upon device geometries and dopings are proposed.     

High speed normally-off GaAs MESFET integrated circuit

Normally-off GaAs MESFET integrated circuits with a maximum toggle frequency of 2.4 GHz were fabricated by conventional photolithography. The unfavourable effect of the surface depletion layer due to the large state density at the GaAs surface has been reduced by adopting the recessed gate FET structure.     

Operation of SiC normally-off JFET at the edges of its safe operating area

The paper presents the results of an experimental characterization about the operation of the last-generation normally-off SiC JFETs at the edges of their safe operating area. Short circuit and unclamped turn-off operations have been investigated by means of a nondestructive experimental set up where the device is switched in the presence of a protection circuit capable of limiting the energy dissipated on the device after the failure occurrence. The experimental results confirm the very good performances of the device in short circuit for which the failure can be associated only to the increase of the temperature over the limits imposed by the surface metallization. A different scenario appears for the unclamped tests where a second breakdown occurs after a quite long avalanche phase followed by the device failure. It is demonstrated that the duration of the avalanche phase depends on the temperature of the device under test. The damaged area after an avalanche failure is localized at the edge termination of the device and, in particular, at the corner between source and gate metallization.     

10 K-gate GaAs JFET sea of gates

The first GaAs 10 K-gate sea of gates has been successfully fabricated using junction FETs (JFETs) with a gate length of 0.5 μm. A basic cell is designed to comprise both a direct coupled FET logic (DCFL) four-NOR circuit and a source coupled FET logic (SCFL) inverter circuit with an identical enhancement-type JFET. Each input and output level is designed to be compatible with Si emitter-coupled-logic (ECL), CMOS, and transistor-transistor-logic (TTL) levels. Unloaded and loaded DCFL gate delays are 21 and 180 ps/gate with power consumption of 0.4 and 0.5 mW/gate, respectively. The toggle frequency of the T-type flip-flop is 3.9 and 4.4 GHz for DCFL and SCFL, respectively     

Temperature stability of ultrahigh-speed GaAs JFET ICs

Ultrahigh-speed digital integrated circuits (ICs) implemented with GaAs/int JFETs are confirmed to be reliable in a wide variety of temperatures. Divide-by-256/258 dual-modulus prescaler ICs using source-coupled FET logic (SCFL) circuits that can operate up to 9 GHz have temperature coefficients of operating frequency stability and input power sensitivity of -17.2 MHz/degree and +0.12 dBm/degree between -20 and +100°C, respectively. Direct-coupled FET logic (DCFL) circuits were also confirmed to have very small temperature coefficients. The variations of the maximum operating frequency and the input power sensitivity of the DCFL divide-by-4 divider IC are -1.93 MHz/degree and +0.47 dBm/degree, respectively, between -60 and +100°C. The variation in the threshold voltage of the JFET is -0.88 mV/degree which is very small for the temperature stability of GaAs digital ICs     

10GHz GaAs JFET dual-modulus prescalar IC

A divide-by-256/258 dual-modulus prescalar IC has been successfully fabricated using enhancement-mode GaAs JFETs. The maximum operation frequency of 10.4 GHz is obtained by a 0.5 mu m gate length and buried p-layer JFET technology. The prescalar IC has sufficient operational margin to make it compatible with Si bipolar ECL circuits over a wide frequency range.<>     

Threshold voltage margin of normally-off GaAs MESFET in DCFL circuit

The margin of threshold voltage (VT) for GaAs normally-off MESFET DCFL's was numerically analyzed applying the equivalent inverter circuit model. The results show that the optimum (VT) is 0.3 V. Quantitative relation between the margin and delay time is obtained as a function of (VT). At (VT) = 0.3 V, the margin is 0.28 V with tpdless than 100 ps for 0.5 µm gate length.     

Fabrication technology for an 80-ps normally-off GaAs MESFET logic

Fabrication technology of a high-speed normally-off GaAs MESFET logic has been described. Anodic Oxidation process is applied to control epitaxial layer thickness precisely. A SiO2cap during alloying ohmic metal is used to prevent the ohmic layer surface from becoming uneven. A sloped mesa structure edge is used to avoid disconnection of metal interconnection. Electron-beam direct writing is employed to define a submicrometer gate. Applying these technologies, high-speed and small switching energy have been accomplished. The minimum delay timd and the associated switching energy were 77 ps and 75 fJ at room temperature and 51 ps and 97 fJ at 77 K.     

提高电流源性能的JFET级联技术

很多工艺控制传感器(如热敏电阻器和应变桥)都需要精确的偏置电流。增加一只电流设置电阻器R_1后,电压基准电路IC_1就可以构成一个恒定和精确的电流源(图1)。     

Threshold voltage adjustable process for self-aligned gate GaAs JFET

A self-aligned GaAs JFET process, allowing threshold voltage adjustment after gate metallisation, has been developed. Zn-doped tungsten silicide was used as the gate metallisation, which also acts as the source of Zn diffusion for the p-junction gate. The threshold voltage was adjusted by repeated short thermal pulses in a lamp annealer at 550°C. The process has the potential to solve the most difficult task of threshold voltage control necessary for achieving high yield in LSI fabrication.     

Proposed GaAs IMPATT device structure for D-band applications

A GaAs double drift IMPATT device structure for applications in D-band is proposed which exhibits high efficiencies at relatively high impedance levels. Computer simulations using a full hydrodynamic transport model with two additional energy balance equations for accurate modelling of impact ionisation show that under realistic thermal considerations, output powers up to 400 mW should be obtainable around 150 GHz     

GaAs digital IC technology/statistical analysis of device performance

A new approach to the design and fabrication of GaAs digital integrated circuits capable of high speed and low power dissipation has been demonstrated. This technology relies on Schottky-diode FET logic (SDFL) circuits which take advantage of the high switching speed of Schottky diodes and the high transconductance of the GaAs 1-µm gate MESFET. These circuits are fabricated by localized implantations directly into the semi-insulating GaAs substrate. Excellent results in terms of speed and power dissipation have been achieved, while circuit complexity has lrapidly grown as demonstrated by the successful operation of an eight-channel multiplexer, an eight-channel demultiplexer, and a 3 × 3 parallel multiplier employing 64, 60, and 75 gates, respectively. This rapid progress requires considerable work in monitoring the process through statistical evaluation of test devices. This paper discusses the process monitoring work carried out in support of the technology, The organization of the masks used for circuit development is described, with emphasis on process monitoring test patterns. Automatic instrumentation used to gather a large amount of statistical information is described, and wafer maps illustrating statistical results are presented and discussed. Uniformity of device characteristics over the full wafer and over smaller areas (circuit size) is compared. Implications of these results are discussed in terms of circuit yield.     

An integrated GaAs n-p-n-p thyristor/JFET memory cell exhibitingnondestructive read

An integrated GaAs n-p-n-p thyristor-junction field effect transistor (JFET) structure displays memory by storing charge on the thyristor reverse-biased junctions. The device can be electrically programmed and erased through a single terminal. A buried p-channel, which also functions as the thyristor anode, is used to read stored charge nondestructively over a small range of applied drain voltages (±1.5 V). Measured storage times exceeded 10 s at room temperature with an activation energy of approximately 0.6 eV