Design and fabrication of sub-μs silicon-on-insulator thermo-optic 4×4 switch matrix

A rearrangeable nonblocking silicon-on-insulator-based thermo-optic 4×4 switch matrix with spot size converters (SSCs) and a new driving circuit are designed and fabricated. The introduction of a spot size converter (SSC) has decreased the insertion loss to less than 10dB and the new driving circuit has improved the response speed to less than 1μs.     

Design and fabrication of sub-μs silicon-on-insulator thermo-optic 4×4 switch matrix

A rearrangeable nonblocking silicon-on-insulator-based thermo-optic 4x4 switch matrix with spot size converters （SSCs） and a new driving circuit are designed and fabricated. The introduction of a spot size converter （SSC） has decreased the insertion loss to less than 10dB and the new driving circuit has improved the response speed to less than l~s.     

Design and Analysis of 4×4 Arrayed Waveguide Grating Multiplexer

The operation principle of an arrayed waveguide grating(AWG) multiplexer is introduced and the 4×4 AWG with following design parameters is discussed in detail, such as the choice of wavelength, the neighboring arrayed waveguide distance ΔL, the channel frequency interval Δf, and the free spectral range. The structure of 4×4 AWG is designed and the result of stimulated test is also given. Analysis shows that the 4×4 AWG is characterized by a wide dynamic range, low crosstalk, better spectrum properties, and a compact structure.     

Design and fabrication of 2.4 GHz pre-biased rectifier

A 2.4 GHz rectifier operating in a region of low RF input power was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input signal. Since a rectifier needs an RF signal higher than the threshold voltage of transistors, we introduced a pre-biasing circuit to compensate for the threshold voltage. A low-voltage digital circuit, subthreshold voltage regulator, and low-power level shifter were introduced for reducing the power consumption of the pre-biasing circuit and increasing the driving voltage for the switches at the same time. The circuit simulations revealed that the pre-biasing circuit was effective in a low RF input power region. However, the output voltage was degraded in a high power region. Then, we combined the pre-biased rectifier in parallel with a non-biased rectifier. Three types of rectifiers consisting of LC matching circuits, three-stage rectifier cells, and biasing circuits were designed and fabricated using a 0.18-μm mixed signal/RF CMOS process with one poly and six metal layers. The fabricated pre-biased rectifier operated in a region of RF input power of less than ?15 dBm, while the non-biased rectifier could not operate in this region. The parallel combination of pre-biased and non-biased rectifiers effectively solved the drawback of the pre-biased rectifier in a high RF input power region.     

Design of a 1 × 2 novel optical switch based on polarization converters and splitters

In this paper, a 1?×?2 optical switch based on two TE/TM polarization converters, one 1?×?2-polarization beam splitter and a hybrid 2?×?2-polarization beam splitter/combiner is designed and discussed. The novelty of this work resides in the design of a 2?×?2-hybrid polarization beam combiner/splitter, operating as a 2?×?2 polarization optical switch through the combining and the splitting of polarized signals issued from two TE/TM polarization controllers. The novel hybrid splitter/combiner can route an optical signal either to a bar or a cross port with an extinction ratio higher than 90 dB, thanks to the feature of polarization splitting used in this device to suppress undesired polarization states and minimize the polarization-dependent loss. We have used polarization beam converters to switch between two orthogonal modes in order to facilitate the routing of these signals through the 2?×?2-hybrid polarization splitter/combiner. We changed the polarization states of signals, in our simulation via OptiSystem, through polarization controllers, by modifying only their phase shifts between 0 rad and π rad. The proposed 1?×?2 optical switch presents an average insertion loss of 3.5 dB.

     

Design and fabrication of compact 2 × 2 dual linear polarized wideband and high gain array for Ku-band satellite communication application

In this paper, the design of a planar array antenna for two-way satellite communication is presented. The antenna unit consists of four elements and two waveguide feeding networks used to connect the elements. The radiating elements are small horn apertures. Each element of the array includes two separate ports to radiate vertical and horizontal polarization, respectively. The feeding networks consist of power dividers and bends to connect the vertical and horizontal polarization ports of horns, separately. Radiating elements and feeding networks are designed to cover receive band (10.5–12.75 GHz) and transmit band (13.75–14.5 GHz) within Ku-band. The maximum gain for this type of antenna is 21 dBi.     

Design and fabrication of Si LED with the N-well-P^＋ junction based on standard CMOS technology

A wedge shape Si LED is designed and fabricated with 0.35 μm double-grating standard CMOS technology. The device structure is based on the N-well-P+ junction. The P+ has a wedge shape and is surrounded by the N-well. The micrographs of Si LEDs’ emitting and layout are captured. The I-V characteristic and spectra of the Si LED are tested. Under room temperature and backward bias, its radiant luminosity is 12 nW at 100 mA, and the wavelength of the emitting peak is located at 764 nm.     

Design and realization of 1.3?Gb/s off-chip transmission circuitry using 0.35?μm CMOS technology

Low-voltage-differential-signaling (LVDS) is one of the very popular technologies which simultaneously addresses low dynamic power consumption and high data rate transmission in modern high speed circuit applications. In this paper, system level integration design approach is applied to design LVDS transmitter featuring high off-chip data rate. Full wave electromagnetic simulation technique was adopted to accurately characterize possible couplings and parasitic effects induced from the off-chip components which then acted as the termination of the output circuitry. Common mode feedback was included to perform fine tuning on the offset leading to much higher overall precision. Meanwhile, generation of the controlled current and voltage across termination was guaranteed through the introduction of a constant transconductance bias network. The design was implemented using TSMC 3.3?V 0.35???m CMOS technology with overall chip size of 0.923?mm². At a DC power consumption level of 29.4?mW, the LVDS transmitter exhibited an off-chip data rate of 1.3?Gb/s validated through measurements.     

Design and analysis of a UWB low-noise amplifier in the 0.18μm CMOS process

An ultra-wideband （3.1-10.6 GHz） low-noise amplifier using the 0.18μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW （without output buffer for measurement） with a 1.8 V power supply and occupies 0.88 mm^2.     

Very-Low-Voltage and Cross-Submicron-Technology Passive Tag＇s Logic Design

A low-voltage wide-tolerance-range passive UHF RFID tag＇s baseband logic design is presented in this paper. Based on deep submicron CMOS technologies, the design utilizes tailored techniques to satisfy subthreshold operation： to deal with the specific timing and wide-range- variation problems at very low power supply, and for the consideration of limited availability of RF power. Compen- sated addition is proposed for the PIE decoder, and power- aware scheme is applied to the entire logic part. Galoi Lin- ear feedback shift register （LFSR） and one-hot counter are also applied to fulfill critical timing requirements. Addi- tionally, these techniques help to improve clock efficiency and reduce the frequency variation impact in low-voltage data link portions. Therefore the robustness in subthresh- old operation is ensured. The logic design was fabricated in 180nm- 130nm and 90nm CMOS technologies respectively to verify the compatibility. In measurement the designs in- dicate competent subthreshold operation. The 90rim ver- sion can function at 0.33V.     

Design,Fabrication，and Testing of Single Side Alignment of 16×0.8nm Arrayed Waveguide Grating

A novel design of 100GHzspaced 16channel arrayed-waveguide grating (AWG) based on silica-on-silicon chip is reported.AWG is achieved by adding a Ybranch to the AWG and arranging the input/output channel in a neat row,so the whole configuration can be aligned and packaged using only one fiberarray.This configuration can decrease the device’s size,enlarge the minimum radius of curvature,save time on polishing and alignment,and reduce the chip’s fabrication cost.     

Optical implementation of a polarization-independent bidirectional 3 × 3 optical switch

Based on the important role of optical switching in all-optical communications, a novel 3 × 3 optical switch is proposed using Phase Spatial Light Modulators (PSLM), Polarizing Beam-Splitters (PBS), mirrors, and Quarter-Wave Plates (QWP). This new configuration of optical switch has the advantages of being compact in structure, efficient in performance, and insensitive to polarization of the signal beam. Moreover, the functions of the 3 × 3 optical switch have been implemented bidirectionally in free-space. According to the routing-state table of the polarization-independent 3 × 3 optical switch, its operational processes are analyzed, and the results show that the experimental module of the 3 × 3 optical switch can connect an arbitrary output port to any input port beams. Simultaneously, the module is scalable to large array sizes and has the capability of reconfiguration. Therefore, it should be helpful in the design of a large-scale switching matrix.

Design and Analysis of 120-μm Core Rod-Type Photonic Crystal Fiber for High Power 1.5-μm Band Amplifier

We report the design and analysis of a rod-type photonic crystal fiber with Er-Yb co-doped for the high power 1.5-μm band amplifier.The fiber structure is designed to be the 120-μm extreme large core diameter,300-μm inner cladding diameter,and 1.5-mm outer cladding diameter that ensure the single mode output during high power amplification.Both the continuous wave(CW) and pulsed amplification characteristics are analyzed based on the exact modeling and simulation under the designed geometry.The 4-mJ pulse energy and 400-kW peak power are obtained in theory,so the 1.5-μm band amplifier that achieves milojoule level pulse energy meanwhile keeping single mode is firstly designed.     

Analysis of ATPMOS configurations-based 4 × 1 multiplexer with estimation of power and delay

In this article, two consecutive augmenting transistor P-channel metal oxide semiconductor (ATPMOS) configurations are proposed. These two ATPMOS configurations (ST ATPMOS and DT ATPMOS) are implemented on a 4 × 1 (multiplexer) mux circuit. Leakage power dissipation, dynamic power dissipation and delay performance parameters are calculated for both (ST ATPMOS and DT ATPMOS) ATPMOS configurations-based 4 × 1 mux circuits at different values of transistor’s width. Due to simulation, it is realised that the leakage power dissipation and dynamic power dissipation are reduced and delay is improved (delay is reduced) in the DT ATPMOS configuration-based mux circuit compared to the ST ATPMOS configuration-based mux circuit. The whole simulation process was carried out in 45-nm technology. The circuits were operated at 1-V power supply.     

Design and Implementation of a Driver＇s Eye State Recognition Algorithm Based on PERCLOS

In order to improve the general detection accuracy of eye state, this paper puts forward an innovative method for judging human eye state based on PERCLOS. After pretreatment of the eye image, Hough transformation is used for ellipse detection and pupil position. The gray projection variance threshold analysis is then used to help make the final detection. Freeman chain and the Snake model algorithm are used for the corner detection and pre- cise calculation of the height of an open eye. Thus the PER- CLOS value and the eye state can be figured out. The performance of our eye state recognition algorithm is validated by more than 1000 images within product database. The statistics result shows that the fatigue detection accuracy rate can meet the need of usage in complex environment.     

A Fast H.264 Intra Frame Encoder with Serialized Execution of 4 × 4 and 16 × 16 Predictions and Early Termination

This paper presents a fast H.264 intra frame encoder that processes a single macroblock of 1920 × 1080 size video in 334 cycles on average which is 20% faster than the previous best design. The speed-up is mainly achieved by early termination of either 4 × 4 intra prediction or 16 × 16 intra prediction. The executions of intra 4 × 4 and 16 × 16 predictions are serialized and the second prediction is terminated early by using the cost of the first prediction as the stop criterion. A simple and efficient algorithm by making use of spatial locality is proposed to select the mode that is processed first. To avoid the bubble cycles caused by this serialized execution of 4 × 4 and 16 × 16 predictions, the modified processing order presented in (Jung et al. 2008) is employed for intra 4 × 4 prediction in order to schedule dependent 4 × 4 blocks apart from each other. To further reduce the execution time of 4 × 4 prediction, neighboring pixels with the same value are grouped, and only one prediction mode in the group is evaluated. Experimental results show that the PSNR drop is 0.0619 dB and the bitrate increase is 0.842% when compared with the JM reference software. The additional hardware cost to support the proposed methods is less than eight thousand gates which are very small when compared with the hardware size of a whole intra frame encoder.     

Design and Implementation of a Novel Area-Efficient Interpolator

提出了一种插值滤波器的设计与实现的新方法,并最终将其实现.该方法适合于过采样数模转换器.为减小芯片面积及设计复杂度,采用一种等同子滤波器级联设计方法,并对其改进.同时,提出了一种新型的等同子滤波器实现结构,进一步减少了芯片实现所需的硬件.测试结果表明,芯片达到了设计指标,节省了芯片面积,并显示出良好的噪声抑制性能.该数字插值滤波器已经被成功应用于一款过采样数模转换器.     

Design and Fabrication of Polymer Arrayed Waveguide Grating

1　IntroductionTheArrayedWaveguideGrating(AWG)multi plexerisanimportantopticaldeviceforWavelengthDivisionMultiplexing (WDM )inopticaltelecom municationsystems[1～ 5] .Thisdevicecanoffersomebasicfunctionsincludingmultiplexing/demultiplex ing ,add/dropmultiplexingandN×Ninterconnec tion.Also,itpossessessomeadvantages,suchasnarrowerwavelengthspacing ,moresignalchannels,lowercrosstalkandsmootherpassbands.AWGmul tiplexers[6～1 0 ] havebeenfabricatedusingsilicas,InPandpolymers.Amongthem ,apo…