窄带射频接收系统中带通∑-△调制器的设计

设计了一种适用于无线窄带射频接收系统的带通∑-△调制器，并将其成功集成于一个无线射频收发芯片之中。该调制器采用0．35μm CMOS工艺实现，采用斩波-稳零，动态元件匹配，以及正交采样等技术，提高系统的信噪比，并解决通道间失配的问题。模拟结果表明，该电路在30kHz带宽内，信噪比为83．4dB，而两个通道消耗的总电流仅为1mA。     

测量系统中20位精度带通Σ-Δ调制器的设计

设计了一种用于测量系统的20位精度带通Σ-Δ调制器.采用低失真离散时间单环4阶1比特量化结构,以实现高精度的指标.对带通调制器中最关键的模块-谐振子进行了研究,设计了一种对电容非线性和失配不敏感并具有精确谐振频率的高Q值谐振子.仿真结果表明,该调制器在100 kHz中频处20 Hz带宽内实现了20位分辨率.本调制器采用AMI 0.35 μm标准CMOS工艺实现,整个调制器的总面积仅为2.5 mm2,在3.3 V供电电压下,调制器的总功耗仅为4 mW.     

一种低电压工作的高速开关电流∑-△调制器

基于作者先前提出的时钟馈通补偿方式的开关电流存储单元及全差分总体结构，本文设计了一种二阶开关电流∑-Δ调制器。工作中采用TSMC 0．35μm CMOS数字电路工艺平台，在低电压工作下进行电路参数优化。实验表明，调制器在3．3V工作电压、10MHz采样频率、64倍过采样率下实现10-bit精度。与已有类似研究相比，本工作在相当的精度条件下，实现了低电压、视频速率的工作。     

一种5阶1位∑-△调制器的设计

提出了一种稳定的5阶∑-△调制器的设计与调试方法.电路采用5阶级联结构,主要用CMOS开关电容技术实现,文章重点放在调制器结构的设计及几种防止系统发散和改进性能的途径上.模拟实验表明,经过改进的系统有较好的性能.     

20位∑-△A/D转换器的设计

文章介绍了20位、5V单电源过采样∑-△A/D转换器,根据精度与阶数和过采样比的关系,设计了4阶蒡-驻调制器。在∑-△调制器中添加了局部负反馈,使转换器能对满量程(FS)输入信号进行精确转换;在梳状滤波器后面添加了补偿电路,补偿梳状滤波器在基带内的衰减,使基带内的纹波小于0.001dB。本电路采用0.6滋mCMOS工艺,电路的结构和精度通过了HSPICE、STAR-SIM等EDA软件的验证。     

低电压∑-△调制器关键技术及设计实例

介绍了低电压开关电容∑-△调制器的实现难点及解决方案,并设计了一种1V工作电压的∑-△调制器。在0．18μm CMOS工艺下,该∑-△调制器采样频率为6．25MHz,过采样比为156,信号带宽为20kHz;在输入信号为5．149kHz时,仿真得到∑-△调制器的峰值信号噪声失真比达到102dB,功耗约为5mW。     

高阶模拟∑-△调制器设计研究

在简要介绍高阶1位量化∑-△A/D转换器基本原理的基础上,分析了∑-△调制器的噪声特性;介绍了传统线性模型下的噪声传递函数的设计方法.同时,结合实际高阶模拟∑-△调制器的开关电容实现电路,重点对影响调制器性能的非理想因素进行了详细分析,并采用程序建模仿真的方法指导电路设计.与传统设计方法的结果对比表明,文中的方法可以为电路设计提供更加可靠的依据.     

一种高阶1 bit插入式∑-△调制器的设计

介绍了插入式∑-△ A/DC调制器的设计过程,并给出了调制器行为级SIMULINK模型,通过对调制器系统级仿真可以确定调制器的信噪比、增益因子等参数,为其电路设计提供依据.设计了一个4阶调制器,仿真结果显示在128的过采样比、输入信号相对幅度-6 dB的条件下,可获得110 dB的信噪比,达到18 bit的分辨率.     

高分辨率∑-△ADC的原理及应用

MAX1402是一种高分辨率、高精度ADC.文中主要介绍它的应用和设计中的注意事项.     

∑-△调制器在非理想环境中的仿真

摘要：介绍了一整套Simulink模型，利用其可以对任何∑-△调制器的性能进行详尽的仿真。给出的模型中考虑了大量∑-△调制器的非理想因素，例如采样时钟抖动、kT／C噪声和运算放大器参数(噪声、有限增益、有限带宽、转换速率和饱和电压)等。针对每个模型给出了详尽描述和所有实现细节。文中所有仿真的对象为一典型的二阶SC ∑-△调制器结构。最后的仿真结果论证了仿真模型的正确性。     

一种低功耗高精度Sigma-Delta调制器

提出了一种改进的三阶单环Sigma-Delta调制器,噪声传递函数采用前馈方式实现极点,降低了积分器输出信号的幅度,从而降低功耗;采用局部反馈实现零点,从而优化了输出信噪比。采用0.35μm CMOS工艺设计了该调制器,过采样率128,信号带宽24kHz,分辨率16bit,在3.3V工作电压下,模拟电路部分功耗2.7mW,数字部分功耗0.5mW。电路用开关电容技术实现,在HSPICE中通过多工艺角验证。     

一种12位开关电流型Σ-△调制器

开关电流电路（ＳＩ）是近年兴起的一种模拟电路。文中引用了新型的两步采样开关电流技术（Ｓ＾２Ｉ）,对该电路中减小时钟馈漏效应的几种方法进行了分析。利用差分平衡结构的Ｓ＾２Ｉ存储单元设计了平衡Ｓ＾２Ｉ积分器,并在此基础上设计出一种平衡差分结构的二阶∑－△调制器。该调制器能够完全与标准ＣＭＯＳ数字工艺兼容。利用标准１．２μｍ数字ＣＯＭＳ工艺的ＨＳＰＩＣＥ模型参数进行了分析,该电路信噪比达到７３．３ｄＢ,     

A Wideband Sigma-Delta Modulator With Cross-Coupled Two-Paths

The performance of a sigma-delta analog-to-digital converter (ADC) critically depends on one or more of the main three parameters: over-sampling ratio, the order of the modulators, and the number of bits used. Increasing each one of these parameters presents a degree of challenge (i.e., the increase in the over-sampling ratio is limited by the technology and the power consumption requirement). This paper presents a method to obtain high order noise shaping with $N$-path architectures that are based on first-order or second-order modulators. The desired noise transfer function (NTF) is obtained by suitable cross-coupling paths. The method was applied to a two-path first-order modulator for obtaining a second-order noise shaping. The performances of the proposed sigma-delta ADC were verified at the behavioral and transistor level implemented in 90-nm CMOS technology.      

A 1 V Second Order Sigma-Delta Modulator

A second order switched capacitor sigma-delta modulator operating at a supplyvoltage of 1 V is presented. This low supply voltage restricts the gate overdrivevoltage available for switching transistors. The design relies on the elimination ofcritical switches by using a modified switched op amp for the integrator and novelswitched half-supply and reference voltage generators. The design has been carried outin a fully differential configuration in order to minimize errors arising from chargeinjection and clock-feedthrough effects. The converter has been implemented using aconventional 0.8 m double-poly double-metal CMOS process, having a nominalthreshold voltage of 0.75 V. Test results, showing more than 9 bits of resolutionwith an oversampling ratio of 64, are also presented.     

A Triple-Mode Sigma-Delta Modulator for Multi-Standard Wireless Radio Receivers

A 1.8 V sigma-delta modulator with a 4 bit quantizer has been designed for GSM/WCDMA/WLAN receivers in a 0.18 um CMOS process. The modulator makes use of low-distortion sigma-delta modulator architecture and Pseudo-Data-Weighted-Averaging technique to attain high linearity over a wide bandwidth. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. In GSM mode, the modulator achieves 96/104 dB peak SNR/SFDR over 100 kHz bandwidth and dissipates 18 mW at a sampling frequency of 32 MHz. The modulator achieves 92/68 dB peak SFDR and 77/54 dB peak SNR over a 2 MHz/10 MHz bandwidth and dissipates 23/39 mW at a sampling frequency of 64 MHz/160 MHz in WCDMA/WLAN. Ana Rusu received degrees of diploma engineer in electronics and telecommunications engineering from Technical University of Iasi, Romania, in 1983 and Ph.D. in electronics engineering from Technical University of Cluj-Napoca, Romania, in 1998. During 1983–1986 she was with Research Institute for Electronics Iasi, as researcher engineer. From 1986 to 1988 she was with Territorial Computer Centre, Piatra-Neamt, Romania, as a programmer in software engineering. Since 1988 she has been with the Technical University of Cluj-Napoca, Electronics and Telecommunications Faculty. In 1999 she was appointed as an associate professor. She has been in visiting researcher positions in University of Bradford, England, and Institute National Politechnique of Grenoble, France, in 1997 and 2001, respectively. Since September 2001, she has been with the Royal Institute of Technology (KTH), Stockholm, Sweden, where she is a senior researcher in radio and mixed-signal systems group. Her research interests include data conversion techniques for wireless communications and the design of low-voltage low-power analog and mixed-signal ICs. Ana Rusu has authored or coauthored five books (published in Romanian language) and more than 40 papers in international conference proceedings and journals. Alexey Borodenkov received his B.Sc. degree in computer science and engineering from St. Petersburg Electrotechnical University, Russia in 2002 and M.Sc. degree in electrical engineering from Royal Institute of Technology (KTH), Stockholm, Sweden in 2004. In October 2004 he joined Samsung Electronics Co. Ltd., Gyeunggi-Do, Korea, where he is involved in the design of multi-standard transceivers for wireless communications. His current research interests include integrated-circuit development of frequency synthesizers and data converters. Mohammed Ismail received the B.S. and M.S. degrees in electronics and telecommunications engineering from Cairo University, Egypt, in 1974 and 1978 and the Ph.D. in electrical engineering from the University of Manitoba, Canada, in 1983. He is a Professor with the Department of Electrical Engineering, The Ohio State University, Columbus. Since April 2003, he is also a Professor with the Department of Microelectronics and Information Technology, Royal Institute of Technology (KTH) Stockholm, Sweden. He has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the Far East. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has co edited and coauthored several books. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Spirea AB, Stockholm (now Firstpass Semiconductors AB), a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal's Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He is a Fellow of IEEE. Hannu Tenhunen received degrees of diploma engineer in electrical engineering and computer sciences from Helsinki University of Tehnology, Helsinki, Finland, in 1982 and Ph.D. in Microelectronics from Cornell University, Ithaca, NY, U.S.A., in 1986. During 1978–1982 he was with Electron Physics Laboratory, Helsinki University of Technology, and from 1983 to 1985 at Cornell University as a Fullbright scholar. From September 1985 he has been with Tampere University of Technology, Signal Processing Laboratory, Tampere, Finland, as an associate professor. He was also a coordinator of National Microelectronics Program of Finland during 1987–1991. Since January 1992, he has been with Royal Institute of Technology (KTH) Stockholm, Sweden, where he is a professor of electronic system design. His current research interests are VLSI circuits and systems for wireless and broadband communication, and related design methodologies and prototyping techniques. He has made over 400 presentations and publications on IC technologies and VLSI systems worldwide, and has over 16 patents pending or granted.     

一种流水线型高速过采样∑-△调制器

提出了一种采用流水线采样输入的开关电容型∑－△调制器的实现方法，该方法充分利用了时钟的每一时刻。用此方法设计的∑－△调制器来样速率可提高３０％。实验表明，这种方法是完全可取的。     

基于ΣΔ调制技术的CPFSK调制芯片设计

采用ΣΔ调制技术的小数分频频率合成器设计了CPFSK调制电路,对调制电路的原理以及噪声性能进行了细致的分析。芯片集成了2RC波形成形电路、三阶单级ΣΔ调制器、双模分频器、鉴频鉴相器、电荷泵和压控振荡器,在四电平2RC-CPFSK调制时,16kHz的带宽内可以实现25.6kbps的信息速率传输。电路采用0.35μm标准CMOS工艺实现,调节片外电感,芯片最高工作频率可以到200MHz。     

基于OFDM信号的新型∑△调制器研究

针对OFDM系统的量化噪声问题,研究适于多载波信号的新型量化噪声整形器.比较单零点∑△与多零点∑△调制器的适用性,进而给出多零点∑△调制器用于OFDM系统的完整方法、理论及仿真分析.研究表明,无过采样多零点∑△调制器可有效减小OFDM系统的量化噪声,具有比传统单零点∑△更好的整形性能.3bit量化、信噪比6dB时,系统误比特率性能改善3个数量级;但受限于非循环的量化噪声结构,多零点∑△调制器未能达到完全消除量化噪声的理想状态.     

基于Σ△调制技术的CPFSK调制芯片设计

采用Σ△调制技术的小数分频频率合成器设计了CPFSK调制电路,对调制电路的原理以及噪声性能进行了细致的分析.芯片集成了2RC波形成形电路、三阶单级Σ△调制器、双模分频器、鉴频鉴相器、电荷泵和压控振荡器,在四电平2RC-CP FSK调制时,16 kHz的带宽内可以实现25.6 kbps的信息速率传输.电路采用0.35μm标准CMOS工艺实现,调节片外电感,芯片最高工作频率可以到200 MHz.