A Study on the Breakdown Mechanism of an Electroless-Plated Ni(P) Diffusion Barrier for Cu/Sn/Cu 3D Interconnect Bonding Structures

This study examined the thermal stability of an electroless-plated Ni(P) barrier layer inserted between Sn and Cu in the bonding structure of Cu/Sn/Cu for three-dimensional (3D) interconnect applications. A combination of transmission electron microscopy (TEM) and scanning electron microscopy allowed us to fully characterize the bonding morphology of the Cu/Ni(P)/Sn/Ni(P)/Cu joints bonded at various temperatures. The barrier suppressed Cu and Sn interdiffusion very effectively up to 300°C; however, an interfacial reaction between Ni(P) and Sn led to gradual decomposition into Ni₃P and Ni₃Sn₄. Upon 350°C bonding, the interfacial reaction brought about complete disintegration of the barrier in local areas, which allowed unhindered interdiffusion between Cu and Sn.     

Electromigration-Induced Interfacial Reactions in Cu/Sn/Electroless Ni-P Solder Interconnects

The effect of electromigration (EM) on the interfacial reaction in a line-type Cu/Sn/Ni-P/Al/Ni-P/Sn/Cu interconnect was investigated at 150°C under 5.0 × 10³ A/cm². When Cu atoms were under downwind diffusion, EM enhanced the cross-solder diffusion of Cu atoms to the opposite Ni-P/Sn (anode) interface compared with the aging case, resulting in the transformation of interfacial intermetallic compound (IMC) from Ni₃Sn₄ into (Cu,Ni)₆Sn₅. However, at the Sn/Cu (cathode) interface, the interfacial IMCs remained as Cu₆Sn₅ (containing less than 0.2 wt.% Ni) and Cu₃Sn. When Ni atoms were under downwind diffusion, only a very small quantity of Ni atoms diffused to the opposite Cu/Sn (anode) interface and the interfacial IMCs remained as Cu₆Sn₅ (containing less than 0.6 wt.% Ni) and Cu₃Sn. EM significantly accelerated the dissolution of Ni atoms from the Ni-P and the interfacial Ni₃Sn₄ compared with the aging case, resulting in fast growth of Ni₃P and Ni₂SnP, disappearance of interfacial Ni₃Sn₄, and congregation of large (Ni,Cu)₃Sn₄ particles in the Sn solder matrix. The growth kinetics of Ni₃P and Ni₂SnP were significantly accelerated after the interfacial Ni₃Sn₄ IMC completely dissolved into the solder, but still followed the t ^1/2 law.     

A Linear-Time Complex-Valued Eigenvalue Solver for Full-Wave Analysis of Large-Scale On-Chip Interconnect Structures

This paper proposes a linear-time complex-valued eigenvalue solver for solving large-scale on-chip interconnect problems. The fast eigenvalue solution is achieved by eigenvalue clustering, fast system reduction with negligible computational cost, and fast linear-time solution of the reduced system. Numerical and experimental results are presented to demonstrate the accuracy and efficiency of the proposed method.      

集成电路Cu互连线的XRD研究

对硫酸盐体系中电镀得到的Cu镀层,使用XBD研究不同电沉积条件、不同衬底和不同厚度镀层的织构情况和择优取向.对比了直流电镀和脉冲电镀在有添加剂和无添加剂条件下的织构情况.实验结果表明,对于在各种条件下获得的1 μm Cu镀层,均呈现(111)晶面择优,这样的镀层在集成电路Cu互连线中有较好的抗电迁移性能.     

Electromigration-Induced Void Formation at the Cu<Subscript>5</Subscript>Zn<Subscript>8</Subscript>/Solder Interface in a Cu/Sn-9Zn/Cu Sandwich

The electromigration that occurs in a Cu/Sn-9Zn/Cu sandwich was investigated for void formation at room temperature with 10³ A/cm². A focused ion beam revealed that voids nucleated at the intermetallic compound (IMC)/solder interface regardless of the electron flow direction. The needle-like voids initiated at the cathode Cu₅Zn₈/solder interface due to the outward diffusion of Zn atoms in the Zn-rich phase and expanded as a result of the surface diffusion of Sn atoms upon current stressing.     

一种用于线性网络约简的高效互连线模型

给出了一种用于线性网络约简的高效互连线模型.在这个新模型中,互连线网络的端口被分为有源和无源两类.通过端口的分类,部分的冗余特性可以在约简之前被删减.使用这种模型,约简后线性网络的规模可以减小50%以上.     

一种用于线性网络约简的高效互连线模型

给出了一种用于线性网络约简的高效互连线模型.在这个新模型中,互连线网络的端口被分为有源和无源两类.通过端口的分类,部分的冗余特性可以在约简之前被删减.使用这种模型,约简后线性网络的规模可以减小50 %以上.     

集成电路互连线串扰的模型与分析

针对集成电路中互连线之间的串扰问题,建立了一个基于电阻和电容的串扰分析模型,给出了干扰信号为线性倾斜信号时串扰的时域响应公式,并得出了串扰峰值的估算公式,明确了干扰信号上升沿对串扰的影响。利用该公式,能对全局互连性能的影响做出正确的估计,在互连布局前预先进行路由规划和资源选择。     

空气隙Cu互连结构热应力史研究

将空气引入Cu导线间形成空气隙,可有效降低等效介电常数K_(eff),但同时也使互连结构的机械稳定性面临着挑战。利用ANSYS进行了有限元热分析,研究了制备空气隙Cu互连结构的两种主流工艺过程,即CVD沉积法和热分解牺牲层法,模拟了Cu导线上的热应力变化趋势,并比较了两者的优劣,最终发现互连结构经过一系列热应力的循环作用后,各种材料在不同程度上都有较大的形变,这将影响结构的机械稳定性,甚至引起破坏。所以,需要进一步改善结构设计和使用理想电介质。     

一种用于提取超大规模集成电路电容的新型库查找法

提出了八种节点电容典型结构用以建立电容模型库,并阐明了这八种结构可以提取大多数VLSI互连线的电容参数,给出了这些结构的拟合公式.采用该库查找法计算的互连线电容结果与FastCap所得结果非常吻合.由于电容是直接代入拟合公式计算得到的,所以计算速度非常快.     

一种用于提取超大规模集成电路电容的新型库查找法

提出了八种节点电容典型结构用以建立电容模型库,并阐明了这八种结构可以提取大多数VLSI互连线的电容参数,给出了这些结构的拟合公式.采用该库查找法计算的互连线电容结果与FastCap所得结果非常吻合.由于电容是直接代入拟合公式计算得到的,所以计算速度非常快.     

基于互连线延时的SET脉冲宽度评估模型

研究了互连线延时对单粒子瞬态脉冲效应的影响。研究发现,随着互连线长度的增加,瞬态脉冲首先被展宽,在一定距离后,脉冲宽度衰减为零。基于此研究结果,提出了脉冲宽度随互连线长度变化的数学解析模型。在SMIC 130 nm、90 nm CMOS工艺下,采用Spice软件对应用该数学解析模型的多种器件进行验证。结果表明,该数学解析模型的计算值与仿真值误差最大为6.09%,最小为0.37%。该模型提高了单粒子瞬态脉冲宽度的评估准确度,可应用于单粒子瞬态脉冲效应的硬件加速模拟。     

互联多媒体应用的设计

本文介绍了如何设计具有PVR功能、网络连接和LCD显示的便携式视频点唱机。该设计采用了飞利浦的Nexperia PNX1500媒体处理器，提供通信和视频应用所需要的性能和灵活性。Nexperia是飞利浦用于多媒体应用的可重新编程系统和集成电路(IC)解决方案系列，灵活创新，能缩短上市时间，并适于未来发展需要。     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.     

互连封装结构电特性分析中的改进PEEC三维建模

本文提出了一种改进的PEEC模型,为便于在大规模互连封装结构分析中利用规模缩减技术,它以描述系统的状态方程代替了具体的等效电路.为此它以矢量磁位的积分表达式和洛仑兹规范代替了矢量磁位和标量电位的积分表达式,对积分方程进行展开.这样做可以避免复杂介质结构中的电容矩阵提取,大大节省了计算时间.这一模型可方便地嵌入更大的系统进行分层次的综合分析和利用PVL等规模缩减技术.数值计算的结果与其他文献吻合较好,表明该方法有较高的可靠性.     

一种稳定的RLC互连Π模型构建及其应用

基于RLC互连树节点导纳的低阶矩构建了一种稳定的互连π模型，并讨论了它在互连树延时和逻辑门延时估计中的应用．结果表明，该模型与已有方法相比精度有一定程度的提高．     

A Model for Temporal Evolution of PMD

We elaborate on a stochastic model of the temporal evolution of polarization-mode dispersion (PMD). The reliability of the model is tested by comparison of theoretical results, obtained in the investigation of the conditional statistics of the PMD vector, with data measured on an installed fiber plant.     

Void Growth Behavior in ULSI Cu Interconnections by Grain-Boundary Diffusion Simulation

The behavior of void growth in ultra-large-scale integration Cu interconnections has been investigated by grain-boundary diffusion simulation to confirm the effectiveness of the high-pressure reflow process for suppressing stress-induced voiding. Void growth was simulated by combining stress analysis and atomic flux analysis. The former was calculated by the finite-element method (FEM), and the latter was calculated by an unusual FEM in which grain boundaries were defined as elements. From the results of void growth analysis, we found that voids tend to disappear during the isochronal annealing step and that the void shrinkage rate can be increased by two to three times by applying pressure of 150 MPa compared with normal-pressure annealing. From the simulation results, it can be conjectured that the high-pressure reflow process is effective for eliminating voids in via holes of Cu interconnections.     

Void formation at the interface in Sn/Cu solder joints

The effect of electroplated Cu (EPC), electroplated Sn (EPS) and Cu addition (0.7 wt.%) on the void formation at the reaction interface was investigated through the reaction of solders with Cu substrates. The voids were observed at the Cu₃Sn/EPC interface in the Sn/EPC joints after aging at 150 °C, while not at the Cu₃Sn/high purity Cu (HPC) interface in the Sn/HPC joints even after aging at 180 °C for 720 h. In the EPS/HPC joints, the voids appeared at both Cu₆Sn₅/Cu₃Sn and Cu₃Sn/HPC interfaces after long time aging at 150 °C. The formation of these voids may be induced by the impurities, which were introduced during the electroplating process. The addition of Cu could reduce the interdiffusion of Cu and Sn at the interface and retard the growth of Cu₃Sn layer. Consequently, the formation of voids was suppressed.     

A Unified Finite-Element Solution From Zero Frequency to Microwave Frequencies for Full-Wave Modeling of Large-Scale Three-Dimensional On-Chip Interconnect Structures

It has been observed that a full-wave finite-element-based solution breaks down at low frequencies. This hinders its application to on-chip problems in which broadband modeling from direct current to microwave frequencies is required. Although a static formulation and a full-wave formulation can be stitched together to solve this problem, it is cumbersome to implement both static and full-wave solvers and make transitions between these two when necessary. In this work, a unified finite-element solution from zero frequency to microwave frequencies is developed for full-wave modeling of large-scale three-dimensional on-chip interconnect structures. In this solution, a single full-wave formulation is used. No switching to a static formulation is needed at low frequencies. This is achieved by first identifying the reason why a full-wave eigenvalue-based solution breaks down at low frequencies, and then developing an approach to eliminate the reason. The low frequency breakdown problem was found to be attributed to the discrepant frequency dependence of the real part and the imaginary part of the eigenvalues, which leads to an ill-conditioned eigenvalue system at low frequencies. The discrepant frequency dependence of the real part and the imaginary part is further attributed to the different scaling of the transverse and longitudinal fields with respect to frequency in a transmission-line type structure. By extracting transverse and longitudinal fields separately in the framework of a full-wave formulation, we avoid the numerical difficulty of solving an ill-conditioned eigen-system at low frequencies. The validity of the proposed approach is demonstrated by numerical and experimental results.