一种适用于0.8VCMOS助听器的电流模前馈增益控制系统

摘要：本文介绍了一种适用于助听器前端系统的电流模前馈增益控制系统。和传统自动增益控制系统相比,电流模前馈增益控制通过数字增益控制码来实现前端系统总谐波失真的显著降低。为了从麦克风微弱的输出信号中得到数字控制码, 本文提出了用电流模实现的整流电路和电流模状态控制电路.该设计基于0.13微米CMOS工艺. 测试表明芯片可工作于0.6V的电源电压.在电源电压为0.8V下, 输出摆幅500mVp-p的信号总谐波失真在0.06% (-64dB)以下, 且功耗控制在40uW以内.另外,系统的等效输入噪声达到4uVrms,最大增益保持在33dB.     

GNSS接收机带有滤波功能可变增益放大器的设计

传统GNSS前端接收机系统中,可变增益放大器（VGA）不具备滤波功能,大多数选用片外滤波,这样系统增益和集成度降低,而系统集成的波器选频性能有限。为此,设计一种具有滤波功能的可变增益放大器,采用0．5μmSiGe HBT工艺,可控增益单元与Gm-C滤波单元集成一体,并运用4晶体管回转器结构实现滤波。电路驱动电压为3.3V,电流为11．7mA。线性增益控制范围为-26～62dB,且电压控制范围为0．1．8V,最小增益下输入1dB压缩点为-4dBm。可变增益放大器电路不仅具备大的增益控制范围,而且中频46MHz处滤波性能良好,提高芯片的集成度．降低系统功耗。     

多模式开关电源控制芯片的低功耗设计

针对降低多模式开关电源控制芯片在轻载与待机工作模式下功耗,提高其全负载条件下工作效率的需要,提出一种开关电源控制芯片供电系统的设计方案,实现了其在启动、关断、重载、轻载以及待机等各种工作情况下的高效率低功耗工作。该供电系统主要包括欠压锁定电路、数字模块电源单元和两种不同的模拟模块电源单元,以及状态检测模块和模式控制逻辑单元,能够实现电源的上电、掉电控制,同时能够根据电源的负载条件控制各模块的开通关断以实现低功耗工作。该系统已应用于绿色多模式反激式开关控制器的设计中,取得了提高电源效率、降低待机功耗的作用。芯片采用1.5μm BiCMOS工艺设计制成。测试表明,所设计电源的各项指标均已达到设计要求。     

GNSS接收机带有滤波功能可变增益放大器的设计

传统GNSS前端接收机系统中,可变增益放大器(VGA)不具备滤波功能,大多数选用片外滤波,这样系统增益和集成度降低,而系统集成的波器选频性能有限.为此,设计一种具有滤波功能的可变增益放大器,采用0.5 μm SiGe HBT工艺,可控增益单元与Gm-C滤波单元集成一体,并运用4晶体管回转器结构实现滤波.电路驱动电压为3.3 V,电流为11.7 mA,线性增益控制范围为-26～62 dB,且电压控制范围为0～1.8 V,最小增益下输入1 dB压缩点为-4 dBm.可变增益放大器电路不仅具备大的增益控制范围,而且中频46 MHz处滤波性能良好,提高芯片的集成度,降低系统功耗.     

宽带CMOS可变增益放大器的设计

采用TSMC 0.18μm RF CMOS工艺设计实现了一种对数增益线性控制型的宽带可变增益放大器.电路采用两级结构,前级采用电压并联负反馈的Cascode结构以实现良好的输入匹配和噪声性能;后级采用信号相加式电路实现增益连续可调.同时本文设计了一种新型指数控制电压转换电路,解决了射频CMOS电路中,由于漏源电流与栅源电压通常不为指数关系而造成放大器对数增益与控制电压不成线性关系的难题,实现了可变增益放大器的对数增益随控制电压呈线性变化.芯片测试结果表明,电路在1.8V电源电压下,电流为9mA,3dB带宽为430～2330MHz.增益调节范围为-3.3～9.5dB,最大增益下噪声系数为6.2dB,最小增益下输入1dB压缩点为-9dBm.     

UHF RFID发射机用高精度可编程增益放大器设计

采用标准0.18μm CMOS工艺,设计了一种应用于超高频射频识别(UHF RFID)发射机的高精度可编程增益放大器(PGA).该PGA由增益细调级和增益粗调级级联形成.增益细调级采用闭环电阻反馈技术,实现了增益的精确控制,并提高了线性度.增益粗调级采用开环源极负反馈技术,实现了增益的粗略控制,并降低了功耗.仿真结果表明,在1.8V工作电压下,整个可编程增益放大器的功耗为2.69mW,增益动态范围为-12~24dB,步长为1dB,增益误差0.02dB;-12dB增益下输入1dB压缩点为-5.54dBm.     

一种具有精确增益控制的CMOS可编程增益放大器

采用0.13μm RF CMOS工艺,设计了一款具有精确增益步长控制的宽带可编程增益放大器.在传统电阻网络衰减器的基础上,提出了一种新的增益控制方法.该方法采用两个互相重叠的反馈环路,通过改变环路中跨导的比值以实现精细的增益步长控制.测试结果表明,当电源电压为1.2V时,功耗为24 mW,-3 dB带宽为600MHz....     

应用于接收机AGC环路中的SAR ADC

提出了一种应用于射频接收机自动增益控制(AGC)环路中的10位1 MS/s逐次逼近型模数转换器(SARADC).动态高精度比较器和自举开关技术应用在设计中,在保证转换速度和精度的同时,降低了电路功耗.芯片采用SMIC 0.13μm IP8M RF CMOS工艺实现.测试结果表明,在1.2 V电源电压下,采样率为1 MS...     

宽带CMOS可变增益放大器的设计

采用TSMC0.18μm RF CMOS工艺设计实现了一种对数增益线性控制型的宽带可变增益放大器,电路采用两级结构,前级采用电压并联负反馈的Cascode结构以实现良好的输入匹配和噪声性能;后级采用信号相加式电路实现增益连续可调,同时本文设计了一种新型指数控制电压转换电路,解决了射频CMOS电路中,由于漏源电流与栅源电压通常不为指数关系而造成放大器对数增益与控制电压不成线性关系的难题,实现了可变增益放大器的对数增益随控制电压呈线性变化,芯片测试结果表明,电路在1.8V电源电压下,电流为9mA,3dB带宽为430-2330MHz,增益调节范围为-3.3-9.5dB,最大增益下噪声系数为6.2dB,最小增益下输入1dB压缩点为-9dBm。     

具有温度补偿及dB线性增益控制的单级宽范围CMOS可变增益放大器

提出了一种新颖的宽范围CMOS可变增益放大器结构.利用可变跨导和新颖的可变输出电阻,基于单独可变增益级的放大器可提供80dB的宽范围调节.同时控制电路的设计完成了温度补偿及dB线性增益特性,实现在整个温度及增益调节范围内绝对增益误差小于±1.5dB.基于0.25μm CMOS工艺验证表明,放大器可提供64.5dB的增益变化范围,其中dB线性范围为55.6dB.输入1dB压缩点为-17.5到11.5dBm,3dB带宽为65MHz到860MHz,2.5V电源供电下功耗为16.5mW.     

A current mode feed-forward gain control system for a 0.8 V CMOS hearing aid

A current mode feed-forward gain control（CMFGC）technique is presented,which is applied in the front-end system of a hearing aid chip.Compared with conventional automatic gain control（AGC）,CMFGC significantly improves the total harmonic distortion（THD）by digital gain control.To attain the digital gain control codes according to the extremely weak output signal from the microphone,a rectifier and a state controller implemented in current mode are proposed.A prototype chip has been designed based on a 0.13μm standard CMOS process.The measurement results show that the supply voltage can be as low as 0.6 V.And with the 0.8 V supply voltage,the THD is improved and below 0.06%（-64 dB）at the output level of 500 mV_p-p,yet the power consumption is limited to 40μW.In addition,the input referred noise is only 4μV_rmsand the maximum gain is maintained at 33 dB.     

A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

正A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC(automatic gain control) and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL(sound pressure level).Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power(48μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35μm(V_(TON) + |V_(TOP)|≈1.35 V).The THD is below -45 dB.The fabricated chip only occupies the area of 1×0.5 mm~2 and 1×1 mm~2.     

A low power automatic gain control loop for a receiver

This paper proposes a new structure to lower the power consumption of a variable gain amplifier(VGA) and keep the linearity of the VGA unchanged.The structure is used in a high rate amplitude-shift keying(ASK) based IF-stage.It includes an automatic gain control(AGC) loop and ASK demodulator.The AGC mainly consists of sixstage VGAs.The IF-stage is realized in 0.18μm CMOS technology.The measurement results show that the power consumption of the whole system is very low.The system consumes 730μA while oper...     

A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit

An analog/digital reconfigurable automatic gain control(AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented.The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips.What’s more,a novel DC offset cancellation(DCOC) circuit with an HPCF(high pass cutoff frequency) less than 10 kHz is proposed.The AGC is fabricated by a 0.18μm CMOS process.Under analog control mode,the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz.Under digital control mode,through a 5-bit digital control word,the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB.The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV,while the offset voltage of 40 mV is introduced into the input.The overall power consumption is less than 3.5 mA,and the die area is 800×300μm~2.     

A high-performance low-power CMOS AGC for GPS application

A wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier (VGA), a comparator and a charge pump, and the dB-linear gain is controlled by the charge pump. The AGC was implemented in a 0.18 μm CMOS technology. The dynamic range of the VGA is more than 55 dB, the bandwidth is 30 MHz, and the gain error is lower than ±1.5 dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8 V power supply.The AGC power consumption is less than 5 mW, and the area of the AGC is 700 × 450 μm~2.     

一个新的分散定步长功率控制算法

功率控制是CDMA蜂窝移动通信系统的关键技术之一。该文考虑CDMA蜂窝移动系统,在假设系统信道增益时变、有界的情形下,把一个时变系统功率控制问题转化为具有确定信道增益功率控制问题。提出了一个分散定步长反馈调节功率控制算法,并证明了算法的收敛性。仿真结果表明算法是可行的。     

具有自动增益控制的WCDMA直放站上行链路的研究与设计

提出一种具有自动增益控制(AGC)的WCDMA选频式直放站的上行链路系统.基于系统功能电路图,详细地分析了该系统的模拟AGC的电路控制算法,并利用电路设计软件Advanced Design System(ADS)进行了系统级模拟.仿真结果表明此系统具有通带增益大、邻道抑制比高和输出功率稳定可调的优点,适用于WCDMA移动通信系统.     

A 20-Gb/s wideband AGC amplifier with 26-dB dynamic range in 0.18-μm SiGe BiCMOS

This paper presents a 20-Gb/s automatic gain control (AGC) amplifier in a 0.18-μm SiGe BiCMOS for high-speed applications. The proposed AGC amplifier compactly consists of a folded Gilbert variable-gain amplifier (VGA), a post amplifier (PA), a 50-Ω output buffer, and AGC loop including an open-loop peak detector (PD), a RC low-pass filter (LPF), and an error amplifier (EA). The AGC amplifier achieves the broadband characteristic by utilizing inductive peaking and capacitive degeneration as well as f_T-doubler techniques to overcome the large parasitic capacitances. The proposed AGC circuits together with a linear VGA exhibits a wide gain control range of 45 dB for the received signal strength indication (RSSI). The measured AGC amplifier achieves a maximum gain of 21 dB and a -3-dB bandwidth (BW) of 20.6 GHz, which can support up to 25.4-Gb/s data rate. For the pseudorandom bit sequence (PRBS) length 2³¹–1 with a bit-error rate (BER) of 10⁻¹² at 20 Gb/s, the measured input dynamic range is 26 dB (20–400mV_pp) and the peak-to-peak data jitter is less than 8 ps. The AGC amplifier consumes a power of 160 mW from a 3.3-V supply voltage and occupies an area of 850 μm × 850 μm.     

A 60-dB linear VGA with novel exponential gain approximation

A CMOS variable gain amplifier (VGA) that adopts a novel exponential gain approximation is presented.No additional exponential gain control circuit is required in the proposed VGA used in a direct conversion receiver.A wide gain control voltage from 0.4 to 1.8 V and a high linearity performance are achieved. The three-stage VGA with automatic gain control (AGC) and DC offset cancellation (DCOC) is fabricated in a 0.18-μm CMOS technology and shows a linear gain range of more than 58-dB with a linearity error less than ± 1 dB. The 3-dB bandwidth is over 8 MHz at all gain settings. The measured input-referred third intercept point (IIP3) of the proposed VGA varies from -18.1 to 13.5 dBm, and the measured noise figure varies from 27 to 65 dB at a frequency of 1 MHz. The dynamic range of the closed-loop AGC exceeds 56 dB, where the output signal-to-noise-and-distortion ratio (SNDR) reaches 20 dB. The whole circuit, occupying 0.3 mm2 of chip area, dissipates less than 3.7 mA from a 1.8-V supply.