一种高性能32位移位寄存器单元的设计

介绍了一种用于32位微处理器中执行单元的双总线(64位输入32位输出)移位寄存器单元的设计。讨论了矩阵移位器和树状移位器结构,提出了基于两者结合的Matrix-Tree 结构并给出了其硬件电路的实现。为了能实现X86指令集全部移位类指令,采用了指令预处理的技术,节省了指令周期,提高了CPU的效率。     

一种基于GCC的VLIW编译器指令调度算法

指令调度是编译优化过程中的重要技术。对于VLIW机器来讲，由于机器性能与编译器的设计和实现有很大的关系，指令调度就显得尤为重要。指令调度是在保证语义正确的前提下，改变指令执行的顺序，以提高指令级并行的程度。文章在一个DSP芯片C编译器上的工作基础上，介绍了一种行之有效的指令调度算法，并分析了算法的正确性。     

一种用于32位CPU的CPL流水线乘加器的设计

综合的32位乘加器需采用5段流水线才能满足CPU的设计指标，但这样会造成与CPU指令流水线不匹配，带来了控制复杂化。为解决这个问题，采用互补传输门逻辑(CPL)设计了用于32位CPU的高速乘加器，使其流水线段数从原来的5段缩减为与CPU指令流水线相匹配的3段，简化了控制、降低了功耗、节省了面积。     

基于机器学习的电网调度指令智能交互技术研究

随着新一代人工智能和通信技术的快速发展,电网调度指令技术面临着新的技术革新,传统的调度指令操作已无法满足目前提质增效的要求。文中深入研究了基于机器学习的电网调度指令智能交互技术,将电网调度指令分解为执行和评估两个步骤,并建立系统化的人机交互模型。模型设计涵盖了人机交互的4个阶段和一个循环过程,通过交互式迭代提升了调度系统的可交互性。采用机器学习算法完成调度指令的数据清洗,利用端对端的传输结构实现电网调度指令的传输,同时建立传输通道模型。经过系统测试验证了所提方法的有效性,电网调度指令的平均识别率达到91.45%,能够满足电网调度的基本要求。     

TMS320C6X的SPLOOP技术

软件流水是一种实现循环迭代中指令级并行的指令调度技术。它可以克服多周期指令延迟对CPU处理性能的影响,保证循环核的运行效率最优。从C64X+开始,TMS320C6X系列DSP引入SPLOOP技术,软件上增加SPLOOP(D/W)、SPKERNEL等相关指令,硬件上增加软件流水缓存等专用模块,通过模调度软件流水模式,有效缩小了软件代码量,提升了执行代码效率。一般情况下,采用SPLOOP技术后机器编译输出的循环代码质量很高,编程人员无需再对代码进行进一步的手工优化。     

一种DSP和通用CPU一体化的处理器架构及其4核实现

提出了一种DSP和通用CPU一体化的处理器架构,并完成了一款基于该架构的同构4核处理器设计和流片验证.该处理器基于VLIW结构,支持自主定义的DSP指令系统,兼容现有通用的MIPS 4KC处理器指令集,支持最大8个指令通道的并行发射.处理器在不改变CPU的指令编码以及执行顺序的前提下,实现了芯片结构上的DSP和CPU执行处理的一体化,适合在统一的平台上同时完成宽带通信和多媒体的信号和协议处理的嵌入式应用开发.处理器内核通过自主定义的DSP指令字中前后并行标识位和一条专用的前导paralink指令实现了DSP与CPU指令的并行发射.在4核处理器的同构架构上,采用了全局读局部写的多核间片上数据存储策略,在控制硬件开销的基础上实现片上数据的共享.仿真和流片验证结果表明,所提出的DSP和CPU一体化处理器架构可行,在宽带通信和多媒体等嵌入式应用上具有优势.     

基于SOPC的神经网络方法的软硬协同实现

提出了一种基于SOPC的神经网络的软硬件协同设计的实现方法,该方法以FPGA器件上SOPC为硬件载体,NIOS IP软核处理器为CPU,采用用户自定义指令,在NIOS中利用C语言编写神经网络算法程序,实现神经元细胞中软硬件协同设计浮点数乘积累加操作。整个系统在Altera的cyclone Ⅱ器件上测试,改变以往神经网络采用VHDL语言设计时出现的灵活性较差,不利于新型的神经网络模型移植到FPGA中的劣势。     

嵌入式WinCE多线程编程研究与实现

Windowsce5．0作为一个多任务操作系统,采用了一种新的任务调度机制。原理上它将一个进程划分为多个线程,每个线程按照一定的调度策略占用CPU的运行时间及其资源,这样使得CPU的调度单元很小,从而提高了CPU并发处理能力。本文以线程的创建,线程功能的实现,最后将2个线程在wince5．0上并发运行,达到了理论和实践的结合,更进一步了解了线程在嵌入式Windowsce中的调度机理     

自主设计精简指令集的流水线CPU

介绍了基于FPGA平台,设计16位精简指令集流水线CPU.该CPU参考MIPS架构设计精简指令集,通过分析指令处理过程实现五级流水线结构,结合"预测技术"和数据前推方法解决流水线相关问题.为了支持CPU软件架构,设计指令集的汇编编译器.在Modelsim平台运行测试程序,给出仿真综合结果.通过试验结果对比表明,所设计的CPU处理过程所需时钟周期大大减少.     

无线网络中平均功率受限的延时确保调度机制的最优化研究

该文研究了在高斯信道下平均发射功率受限的延时确保调度器的最优化问题。文章首先证明了对于延时确保条件下平均发射功率最优的时不变调度器,其最优的平均发射功率为延时确保界Dmax的单调递减函数,并根据其单调性给出了平均发射功率最优调度器和延时确保最优调度器之间的对偶关系。基于该关系,给出了到达过程未知条件下平均功率受限的延时确保最优调度器的实现形式。该实现形式中参数的确定方法也在给定到达过程分布的条件下给出,并以泊松到达为例进行了分析。文章的最后还给出了该调度器的一种实际实现方案并进行了仿真,仿真结果表明该方案能够达到调度器的最优。     

The design and implementation of real-time schedulers in RED-linux

Researchers in the real-time system community have designed and studied many advanced scheduling algorithms. However, most of these algorithms have not been implemented since it is very difficult to support new scheduling algorithms on most operating systems. To address this problem, we enhance the scheduling mechanism in Linux to provide a flexible scheduling framework. In the real-time and embedded Linux (RED-Linux) project, we implement a general scheduling framework which divides the system scheduler into two components: dispatcher and allocator. The dispatcher provides the mechanism of system scheduling and resides in the kernel space. The allocator is used to define the scheduling policy and implemented as a user space function. This framework allows users to implement application-specific schedulers in the user space which is easy to program and to debug. The framework also relieves the deficiency from the stock Linux scheduler which is not designed for real-time applications. To further enhance its power, a hierarchical scheduling mechanism has been provided in RED-Linux to allow a system designer to integrate different real-time applications together. Using scheduling groups, real-time jobs can be managed and scheduled in a hierarchical manner. In this paper, we discuss how the group mechanism is implemented in RED-Linux.     

A Design Perspective for Real-Time Task Control in Distributed Systems

Industrial control systems have unique system requirements which often require diverse systems of cooperating components to achieve system goals. System requirements may be specified in the form of tasks which must be executed in sequential order. This paper presents a design perspective in which such problems can be decomposed and implemented by a distributed system in a modular-fashion. A System Scheduler is responsible for all flow control functions. Loosely coupled Task Processors respond to instructions from the scheduler to perform the control algorithm Parallelism, redundancy, and distributed control are presented as methods of improving system performance and reliability.     

Priority queue schedulers with approximate sorting inoutput-buffered switches

All recently proposed packet-scheduling algorithms for output-buffered switches that support quality-of-service (QoS) transmit packets in some priority order, e.g., according to deadlines, virtual finishing times, eligibility times, or other time stamps that are associated with a packet. Since maintaining a sorted priority queue introduces significant overhead, much emphasis on QoS scheduler design is put on methods to simplify the task of maintaining a priority queue. In this paper, we consider an approach that attempts to approximate a sorted priority queue at an output-buffered switch. The goal is to trade off less accurate sorting for lower computational overhead. Specifically, this paper presents a scheduler that approximates the sorted queue of an earliest-deadline-first (EDF) scheduler. The approximate scheduler is implemented using a set of prioritized first-in/first-out (FIFO) queues that are periodically relabeled. The scheduler can be efficiently implemented with a fixed number of pointer manipulations, thus enabling an implementation in hardware. Necessary and sufficient conditions for the worst-case delays of the scheduler with approximate sorting are presented. Numerical examples, including traces based on MPEG video, demonstrate that in realistic scenarios, scheduling with approximate sorting is a viable option     

超标量RISC微处理器指令发射算法设计

提出了一种基于分布式控制方式的动态指令调度算法,该算法能够有效提高指令发射效率,降低指令分派单元逻辑复杂度,提高系统主频.该指令发射算法在自主设计的"龙腾R3" RISC"三发射"超标量微处理器中进行应用实现,达到了设计预期目标.     

A Real-Time Process Scheduler for a Ring-Type Microcomputer Network

This paper describes the design of a real-time process control scheduler for microcomputers in a distributed process control scheme with a ring-type network configuration. For simplicity, static priority based round-robin scheduling policy is used where working time-slice, for different processes can be variable. The memory size for the process scheduler modules is estimated at about 2.5 Kbytes using an Intel 8085 instruction set and a RAM requirement of about 1 Kbyte.     

基于802．16的跨层调度器设计

首先对基于IEEE802．16标准定义的QoS架构进行了扩充,然后对BS分组调度器进行了具体的设计,将其分为服务信息模块、信道状态反馈模块和服务调度模块3个部分。为不同类型的服务流提供QoS支持,设计了MAC—PHY跨层调度器,综合考虑无线信道的状态和MAC层业务QoS要求,对业务进行3级调度：     

Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems

Wepresent the Serra Run-Time Scheduler Synthesis and AnalysisTool which automatically generates a run-time scheduler froma heterogeneous system-level specification in both Verilog HDLand C. Part of the run-time scheduler is implemented in hardware,which allows the scheduler to be predictable in being able tomeet hard real-time constraints, while part is implemented insoftware, thus supporting features typical of software schedulers. Serra's real-time analysis generates a priority assignment forthe software tasks in the mixed hardware-software system. Thetasks in hardware and software have precedence constraints, resourceconstraints, relative timing constraints, and a rate constraint.A heuristic scheduling algorithm assigns the static prioritiessuch that a hard real-time rate constraint can be predictablymet. Serra supports the specification of critical regions insoftware, thus providing the same functionality as semaphores.We describe the task control/data-flow extraction,synthesis of the control portion of the run-time scheduler inhardware, real-time analysis and priority scheduler template.We also show how our approach fits into an overall tool flowand target architecture. Finally, we conclude with a sample applicationof the novel run-time scheduler synthesis and analysis tool toa robotics design example.     

建筑电气智能监控系统组态软件设计

基于自主开发L-N(Local-monitoring-Network)现场总线构成的电气监控网络,设计了一种适用性强、可靠性高、实时交互的建筑电气智能监控系统组态软件.该组态软件采用Visual C ++开发平台,将面向对象技术、多线程技术、TCP/IP远程通信技术有效结合起来,使用规范的应用层通信协议,实现建筑电气监控系统的用户管理、场景管理、组态编程与应用、宏指令管理、计划任务管理、报警功能配置及按键模板管理等功能.测试与工程应用结果表明,开发的组态软件表现出良好的实时性、稳定性和易用性,满足工程师和终端用户的需求.     

OBS核心控制器结构设计与硬件化实现

设计了一个基于JIT协议的OBS核心控制器,该控制器将路由选择和信道调度整合在一个模块中处理,并采用信道资源信息共享与先调度再转发的处理机制,简化了控制器的结构,有效提高了OBS核心节点的处理速度,同时也避免了路由选择的盲目性,减少丢包。在FPGA平台上实现了提出的OBS核心控制器结构并进行了实际测试。测试结果表明：接收完BCP包到发出光开关设置信号的最短时间为100ns。     

Reliable real-time task scheduler based on Rocket Queue architecture

This paper presents the design of an improved task scheduler for real-time and safety-critical systems, where it is important to deal with real-time requirements and reliability requirements simultaneously. The proposed scheduler implements EDF algorithm for the optimal scheduling of hard real-time tasks, which is essential for real-time operating systems. The proposed task scheduler allows removing any task from the queue according to task ID and regardless of the actual position of the task within the queue, which is important for flexibility of the scheduler for its future extensions. Both operations of the scheduler, i.e. task adding and task killing take always constant time (two clock cycles) to execute regardless of the actual or the maximum number of tasks within the scheduler. The scheduler was verified using simplified version of UVM and applying millions of instructions with randomly generated sort values. The scheduler, implemented in a form of a coprocessor, was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency. There are two improvements proposed that can significantly reduce resource costs of the scheduler, which is achieved by replacing static deadlines with dynamic deadlines and using a new Rocket Queue architecture for sorting of the tasks according to their deadline values. When both improvements are applied simultaneously, the total ALM cost savings are in the range from 42,59% to 60,18% and the total amount of registers is reduced by 73,74% to 74,87%, depending on the scheduler capacity. The spared resources are then used for implementation of two different variations of TMR in order to increase fault tolerance of the scheduler. The resource cost reductions achieved also indirectly increase the reliability of such scheduler because of reduced probability that a fault occurs.