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1.
In this letter, a low loss high isolation broadband single-port double-throw (SPDT) traveling-wave switch using 90 nm CMOS technology is presented. A body bias technique is utilized to enhance the circuit performance of the switch, especially for the operation frequency above 30 GHz. The parasitic capacitance between the drain and source of the NMOS transistor can be further reduced using the negative body bias technique. Moreover, the insertion loss, the input 1 dB compression point (${rm P} _{{1}~{rm dB}}$), and the third-order intermodulation (IMD3) of the switch are all improved. With the technique, the switch demonstrates an insertion loss of 3 dB and an isolation of better than 48 dB from dc to 60 GHz. The chip size of the proposed switch is 0.68 $,times,$0.87 ${rm mm}^{2}$ with a core area of only 0.32$,times,$0.21 ${rm mm}^{2}$.   相似文献   

2.
This letter presents a wideband low-noise amplifier (LNA) that supports both differential and single-ended inputs, while providing differential output. The LNA is implemented in 0.13 $mu{rm m}$ CMOS technology. For sub-1 GHz wideband applications, this LNA achieves 22.5 dB voltage gain, ${+ 1}~{rm dBm}$ IIP3, and 2.5 dB NF in the differential receiving mode, while achieving 23 dB voltage gain, ${- 0.5}~{rm dBm}$ IIP3, and 2.65 dB NF in the single-ended receiving mode. The LNA core circuit draws 2.5 mA from 1.2 V supply voltage, and occupies a small chip area of 0.06 ${rm mm}^{2}$.   相似文献   

3.
A fully differential architecture from the antenna to the integrated circuit is proposed for radio transceivers in this paper. The physical implementation of the architecture into truly single-chip radio transceivers is described for the first time. Two key building blocks, the differential antenna and the differential transmit–receive (T–R) switch, were designed, fabricated, and tested. The differential antenna implemented in a package in low-temperature cofired-ceramic technology achieved impedance bandwidth of 2%, radiation efficiency of 84%, and gain of 3.2 dBi at 5.425 GHz in a size of 15$times$15$times$1.6 ${hbox {mm}}^{3}$. The differential T–R switch in a standard complementary metal–oxide–semiconductor technology achieved 1.8-dB insertion loss, 15-dB isolation, and 15-dBm 1-dB power compression point ($P_{1,{hbox {dB}}}$) without using additional techniques to enhance the linearity at 5.425 GHz in a die area of 60$times$40 $mu{hbox {m}}^{2}$.   相似文献   

4.
A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18- $mu{{hbox{m}}}$ SiGe BiCMOS technology for $Q$-band (30–50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an ${rm IIP}_{3}$ of $-$13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8–44 GHz. The rms gain and phase errors are $leq$1.2 dB and $leq {hbox{8.7}}^{circ}$ for all 4-bit phase states at 30–50 GHz. The beamformer also results in $leq$ 0.4 dB of rms gain mismatch and $leq {hbox{2}}^{circ}$ of rms phase mismatch between the four channels. The channel-to-channel isolation is better than $-$35 dB at 30–50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is ${hbox{1.4}}times {hbox{1.7}} {{hbox{mm}}}^{2}$ including all pads and CMOS control electronics.   相似文献   

5.
This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.   相似文献   

6.
A 0.55 V supply voltage fourth-order low-pass continuous-time filter is presented. The low-voltage operating point is achieved by an improved bias circuit that uses different opamp input and output common-mode voltages. The fourth-order filter architecture is composed by two Active- ${rm G}_{rm m}{-}{rm RC}$ biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. The $-$ 3 dB filter frequency is 12 MHz and this is higher than any other low-voltage continuous-time filter cut-off frequency. The $-$3 dB frequency can be adjusted by means of a digitally-controlled capacitance array. In a standard 0.13 $mu{rm m}$ CMOS technology with ${V}_{THN}approx 0.25 {rm V}$ and ${V}_{THP}approx 0.3 {rm V}$, the filter operates with a supply voltage as low as 0.55 V. The filter $({rm total} {rm area}=0.47 {rm mm}^{2})$ consumes 3.4 mW. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.   相似文献   

7.
In this paper, gain-enhancement techniques suitable for folded cascode low-noise amplifiers (LNAs) at low-voltage operations are presented. By employing a forward bias and a capacitive divider at the body of the MOSFETs, the LNA circuit can operate at a reduced supply voltage while maintaining an enhanced gain due to suppression of the negative impact of the body transconductance. In addition, a $G_{m}$-boosting stage is introduced to further increase the LNA gain at the cost of circuit linearity. Using a standard 0.18-$mu{hbox {m}}$ CMOS process, two folded cascode LNAs are demonstrated at the 5-GHz band based on the proposed topologies. Consuming a dc power of 1.08 mW from a 0.6-V supply voltage, the LNA with the forward-body-bias technique demonstrates a gain of 10.0 dB and a noise figure of 3.37 dB. The measured $P_{{rm in}-1 {rm {dB}}}$ and ${rm IIP}_{3}$ are $-$18 and $-$ 8.6 dBm, respectively. For the LNA with a $G_{m}$-boosting feedback, a remarkable gain of 14.1 dB gain is achieved with a dc power of 1.68 mW.   相似文献   

8.
Millimeter Wave Varistor Mode Schottky Diode Frequency Doubler in CMOS   总被引:1,自引:0,他引:1  
The first mm-wave varistor mode Schottky diode frequency doubler fabricated in CMOS is demonstrated. The doubler exhibits 14 dB conversion loss, $-11~{rm dBm}$ output power at 132 GHz and 6 GHz 3-dB output bandwidth from 128 to 134 GHz. The input matching is better than $-10~{rm dB}$ and the rejection of fundamental signal at output is greater than 14 dB from 62 to 70 GHz.   相似文献   

9.
A novel unequal Wilkinson power divider is presented. A coupled-line section with two shorts is proposed to realize the high characteristic impedance line, which cannot be implemented by conventional microstrip fabrication technique due to fabrication limitation. The proposed coupled-line structure is compatible with single layer integration and can be easily designed based on an even-odd mode analysis. As a design example, a 10:1 Wilkinson power divider at 2 GHz is fabricated and measured. The measured $-10~{rm dB}$ bandwidth of $S_{11}$ is about 16%, and the isolation $S_{32}$ is better than $-20~{rm dB}$ . The measured amplitude balance between output port 2 and port 3 is between $-10.20~{rm dB}$ and $-9.52~{rm dB}$, and the corresponding phase difference is between 0$^{circ}$ and 4.6$^{circ}$.   相似文献   

10.
A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology   总被引:2,自引:0,他引:2  
A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.   相似文献   

11.
A linearization technique is proposed in which low-frequency second-order-intermodulation $({rm IM}_{2})$ is generated and injected to suppress the third-order intermodulation $({rm IM}_{3})$. The proposed linearization technique is applied to both a low-noise amplifier (LNA) and a down-conversion mixer in an RF receiver front-end (RFE) working at 900 MHz. Fabricated in a 0.18$ mu{hbox{m}}$ CMOS process and operated at 1.5 V supply with a total current of 13.1 mA, the RFE delivers 22 dB gain with 5.3 dB noise figure (NF). The linearization technique achieves around 20 dB ${rm IM}_{3}$ suppression and improves the RFE's ${rm IIP}_{3}$ from $-$ 10.4 dBm to 0.2 dBm without gain reduction and noise penalty while requiring only an extra current of 0.1 mA.   相似文献   

12.
A Low Voltage Mixer With Improved Noise Figure   总被引:2,自引:0,他引:2  
A 5.2 GHz low voltage mixer with improved noise figure using TSMC 0.18 $mu$m CMOS technology is presented in this letter. This mixer utilizes current reuse and ac-coupled folded switching to achieve low supply voltage. The noise figure of the mixer is strongly influenced by flicker noise. A resonating inductor is implemented for tuning out the parasitic components, which not only can improve noise figure but also enhance conversion gain. A low voltage mixer without resonating technique has also been fabricated and measured for comparison. Simulated results reveal that flicker corner frequency is lowered. The measured results show 4.5 dB conversion gain enhancement and 4 dB reduction of noise figure. The down-conversion mixer with resonating inductor achieves 5.8 dB conversion gain, ${-}16$ dBm ${rm P}_{{rm 1dB}},$ ${-}6$ dBm ${rm IIP}_{3}$ at power consumption of 3.8 mW and 1 V supply voltage.   相似文献   

13.
A 0.13 $mu{rm m}$ CMOS 2.4 GHz balun-mixer is proposed, where a current-reused noise-canceling topology is adopted as the transconductance stage to reduce dc power consumption. After frequency conversion, noise-cancellation is achieved only when a specified condition is satisfied, but single-to-differential signal conversion is inherently obtained by the mixer operation. The fabricated chip shows a conversion gain of 13.5 dB, a single-side-band (SSB) noise figure of 8 dB, and an input-referred ${rm IP}_{3}$ of ${- 6}~{rm dBm}$, while consuming only 3.5 mA from a 1.5 V supply voltage.   相似文献   

14.
A W-band (76–77 GHz) active down-conversion mixer has been demonstrated using low leakage (higher ${rm V}_{{rm T}}$) NMOS transistors of a 65-nm digital CMOS process with 6 metal levels. It achieves conversion gain of ${-}8$ dB at 76 GHz with a local oscillation power of 4 dBm (${sim-}2$ dBm after de-embedding the on-chip balun loss), and 3 dB bandwidth of 3 GHz. The SSB noise figures are 17.8–20 dB (11.3–13.5 dB after de-embedding on-chip input balun loss) between 76 and 77 GHz. ${rm IP}_{1{rm dB}}$ is ${-}6.5$ dBm and IIP3 is 2.5 dBm (${sim-}13$ and ${sim}-4$ dBm after de-embedding the on-chip balun loss). The mixer consumes 5 mA from a 1.2 V supply.   相似文献   

15.
Unstrained high-electron mobility transistors (HEMTs) were fabricated from InAlN/GaN on semi-insulating SiC substrates. The devices had 0.24-$muhbox{m}$ T-gates with a total width of $hbox{2} times hbox{150} muhbox{m}$. Final passivated performance values for these devices are $I_{max} = hbox{1279} hbox{mA/mm}$, $I_{rm DSS} = hbox{1182} hbox{mA/mm}$ , $R_{c} = hbox{0.43} Omega cdot hbox{mm}$, $rho_{s} = hbox{315} Omega/hbox{sq}$, $f_{T} = hbox{45} hbox{GHz}$, $f_{max({rm MAG})} = hbox{64} hbox{GHz}$, and $g_{m} = hbox{268} hbox{mS/mm}$. Continuous-wave power measurements at 10 GHz produced $P_{rm sat} = hbox{3.8} hbox{W/mm}$, $G_{t} = hbox{8.6} hbox{dB}$, and $hbox{PAE} = hbox{30}%$ at $V_{rm DS} = hbox{20} hbox{V}$ at 25% $I_{rm DSS}$ . To our knowledge, these are the first power measurements reported at 10 GHz for this material.   相似文献   

16.
The fluctuation of RF performance (particularly for $f_{T}$ : cutoff frequency) in the transistors fabricated by 90-nm CMOS technology has been investigated. The modeling for $f_{T}$ fluctuation is well fitted with the measurement data within approximately 1% error. Low-$V_{t}$ transistors (fabricated by lower doping concentration in the channel) show higher $f_{T}$ fluctuation than normal transistors. Such a higher $f_{T}$ fluctuation results from $C_{rm gg}$ (total gate capacitance) variation rather than $g_{m}$ variation. More detailed analysis shows that $C_{rm gs} + C_{rm gb}$ (charges in the channel and the bulk) are predominant factors over $C_{rm gd}$ (charges in LDD/halo region) to determine $C_{rm gg}$ fluctuation.   相似文献   

17.
Effects of silicon nitride (SiN) surface passivation by plasma enhanced chemical vapor deposition (PECVD) on microwave noise characteristics of AlGaN/GaN HEMTs on high-resistivity silicon (HR-Si) substrate have been investigated. About 25% improvement in the minimum noise figure $(NF_{min})$ (0.52 dB, from 2.03 dB to 1.51 dB) and 10% in the associate gain $(G_{rm a})$ (1.0 dB, from 10.3 dB to 11.3 dB) were observed after passivation. The equivalent circuit parameters and noise source parameters (including channel noise coefficient $(P)$, gate noise coefficient $(R)$, and their correlation coefficient $(C)$ ) were extracted. $P$ , $R$ and $C$ all increased after passivation and the increase of C contributes to the decrease of the noise figure. It was found that the improved microwave small signal and noise performance is mainly due to the increase of the intrinsic transconductance $(g_{{rm m}0})$ and the decrease of the extrinsic source resistance $(R_{rm s})$.   相似文献   

18.
This paper realized a broadband uniplanar phase-inverter rat-race coupler using a standard silicon process, and then analyzed this coupler under a lossy condition. A phase inverter is employed in this coupler, not only to extend the operation bandwidth, but also to generate balanced outputs by providing equal lossy paths, while symmetrical spiral-shaped coplanar striplines (CPSs) are also utilized to shrink the coupler size, as well as to construct a phase inverter in the middle of one of spiral CPSs. The lossy CPS, when designed as a distortionless line, has a real characteristic impedance, and thus, perfect port matching of the coupler can be achieved at the center frequency. The operation frequency of this silicon monolithic rat-race coupler with the size of 0.5 ${hbox {mm}}^{2}$ is extremely wide and ranges from 5 to 23 GHz. The dissipated loss, transmission coefficient, and isolation of the rat-race coupler are approximately 5.5, $-$8, and below $-$25 dB, respectively. In addition, a wideband Gilbert micromixer with an integrated uniplanar phase-inverter rat-race coupler at the local oscillator port is demonstrated using 0.35-$mu{hbox {m}}$ SiGe BiCMOS technology. This mixer works from 2.5 to 13 GHz with 12-dB conversion gain, $-$16-dBm ${rm IP}_{1 {rm dB}}$, $-$4-dBm ${rm IIP}_{3}$, and 14-dB noise figure. The chip size of the mixer with an integrated coupler is approximately 1.4 mm $times$ 1.4 mm.   相似文献   

19.
This letter presents a 30–100 GHz wideband and compact fully integrated sub-harmonic Gilbert-cell mixer using 90 nm standard CMOS technology. The sub-harmonic pumped scheme with advantages of high port isolation and low local oscillation frequency operation is selected in millimeter-wave mixer design. A distributed transconductance stage and a high impedance compensation line are introduced to achieve the flatness of conversion gain over broad bandwidth. The CMOS sub-harmonic Gilbert-cell mixer exhibits ${-}{hbox{1.5}} pm {hbox{1.5}}$ dB measured conversion gain from 30 to 100 GHz with a compact chip size of 0.35 mm$^{2}$. The OP$_{1 {rm dB}}$ of the mixer is ${-}$ 10.4 dBm and ${-}$9.6 dBm at 77 and 94 GHz, respectively. To the best of our knowledge, the monolithic microwave integrated circuit is the first CMOS Gilbert-cell mixer operating up to 100 GHz.   相似文献   

20.
We present a high-performance 94-GHz single-balanced monolithic millimeter-wave integrated-circuit (MMIC) mixer using the disk-shaped GaAs Schottky diodes grown on an n/$hbox{n}+$ epitaxial structure. Due to the superior characteristics of the GaAs diodes with high diode-to-diode uniformity, the mixer shows a conversion loss of 5.5 dB at 94 GHz, a 1-dB compression point $(P_{1 hbox{-}{rm dB}})$ of 5 dBm, and high local-oscillator to radio-frequency isolation above 30 dB in an RF frequency range of 91–97 GHz. To our knowledge, the fabricated mixer shows the best performance in terms of conversion loss at 94 GHz and $P_{1 hbox{-}{rm dB}}$ among the W-band MMIC mixers without amplifier circuits.   相似文献   

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