A floating gate CMOS signal conditioning circuit for nonlinearity correction

A high-speed signal conditioning circuit is presented that can be programmed for correction of nonlinearity in a sensor signal processing system. The function of the circuit is based on piecewise linear principles. Post-fabrication programming to adapt to existing nonidealities is done with floating gate devices fabricated in standard technology. Modeling of the sensor nonideality is not required. The circuit is a voltage-to-current converter with an input range of the full power-supply voltage swing. In a 12-module implementation in 2-µm CMOS technology less than 0.5% error over rail-to-rail input range and a speed of 10 MHz were achieved. The circuit is useful where a signal from a sensor with nonlinearity and high variation in its parameters has to be conditioned for further processing.1. The MOSIS Project, USC/ISI, 4676 Admiralty Way, Marina del Rey, CA 90292-6695.This work is supported by an NSF-Research Initiation Award, Grant MIP-90 11360, and by Analog Devices Inc.     

A versatile CMOS linear transconductor/square-law function

A simple CMOS circuit technique for realizing both linear transconductance and a precision square-law function is described. The circuit provides two separate outputs in the linear as well as square-law modes. The linear outputs both have a range of 100% or more of the total quiescent current value. The theory of operation is presented and effects of transistor nonidealities on the performance are investigated. Design optimization techniques are developed. Experimental results measured on nonoptimized prototypes are: distortion of 0.2% for input signals up to 2.4 V/SUB p-p/ in the case of linear transfer function and 1.3% in the case of the square-law transfer function, with a DC to -3-dB bandwidth of up to 20 MHz. Improved performance is expected when the optimization techniques developed are applied. The circuit is versatile in application: diverse applications are demonstrated in the fields of linear amplifiers, continuous-time filters, and nonlinear function implementation.     

Analytical model for switching transitions of submicron CMOS logics

We propose a new analytical model for the switching characteristics of CMOS logics. Our new model, named the Switching Response of CMOS logic by Convolution approach (SRC), can successfully produce the output waveforms under any switching conditions with simple analytical expressions. SRC modeling is a process of transforming CMOS logic into a linear system. This model provides procedures to determine the transfer function and the driving function (input of linear system) of the linear system from given CMOS logic, and then an output waveform, expressed as a third-order equation, is obtained by the convolution of two functions. All parameters in this model are determined in a straightforward manner from given device characteristics and layout geometry without empirical or fitting processes and presimulations. In addition, a delay equation is developed based upon the SRC model. With this delay equation, the delay can be predicted within a few percent differences compared to SPICE simulation results for the wide range of input transition time and output loading capacitance     

A Robust and Scalable Constant-$g_m$ Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without any special devices, such as floating-gate or depletion-mode transistors. Very small variations (less than ) have been achieved without sacrificing the large-signal behavior. The proposed circuit is proven effective for both long-channel and deep sub-micron CMOS technologies and is suitable for VLSI cell libraries, audio/video, embedded mixed-signal system-on-chip (SoC), and other applications. A prototype amplifier with rail-to-rail input common-mode range has been designed and fabricated in a standard 0.35-m CMOS technology. Experimental results confirm the effectiveness and robustness of proposed techniques.     

Accurate and simple CMOS 'one-over' circuit

Experimental results and analysis of a simple, highly linear CMOS circuit to compute a 'one-over' function are presented. This circuit capitalises on the linear region operation of an MOS transistor. Nonlinearity is found to be primarily produced by mobility degradation, but is easily cancelled. The circuit requires limited component matching and it operates with 8 bit accuracy for a wide input and output range.<>     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

Micro-power low-offset instrumentation amplifier IC design for biomedical system applications

This work presents a micro-power low-offset CMOS instrumentation amplifier integrated circuit with a large operating range for biomedical system applications. The equivalent input offset voltage is improved using a new circuit technique of offset cancellation that involves a two-phase clocking scheme with a frequency of 20 kHz. Channel charge injection is cancelled by the symmetrical circuit topology. With the wide-swing cascode bias circuit design, this amplifier realizes a very high power-supply rejection ratio (PSRR), and can be operated at single supply voltage in the range between 2.5-7.5 V. It was fabricated using 0.5-/spl mu/m double-poly double-metal n-well CMOS technology, and occupies a die area of 0.2 mm/sup 2/. This amplifier achieves a 160-/spl mu/V typical input offset voltage, 0.05% gain linearity, greater than 102-dB PSRR, an input-referred rms noise voltage of 45 /spl mu/V, and a current consumption of 61 /spl mu/A at a low supply voltage of 2.5 V. Experimental results indicate that the proposed amplifier can process the input electrocardiogram signal of a patient monitoring system and other portable biomedical devices.     

A linear CMOS transconductance element of an adaptively biased source-coupled differential pair using a quadritail cell

A novel circuit design technique for realizing a linear CMOS transconductance element, consisting of an adaptively biased source-coupled differential pair using a quadritail cell, is proposed. In the circuitry, the quadritail cell, which provides an output current proportional to the square of a differential input voltage, cancels a nonlinear term of the source-coupled differential pair. The circuit have a superior linearity and a wide linear input voltage range compared with the conventional linear CMOS transconductance elements because the transconductance characteristic is theoretically linear over wide input voltage range when all the MOS field-effect transistors (MOSFETs) are operating in the saturation region and the MOSFETs' behaviors are according to the relation based on the square-law characteristic. The proposed adaptively biased source-coupled differential pair was verified by using transistor-arrays and discrete components on a breadboard.     

A novel bulk-input low voltage and low power four quadrant analog multiplier in weak inversion

A new four quadrant voltage mode bulk input analog multiplier is presented .The proposed multiplier is designed to operate in weak inversion. Multiplication is done by driving the bulk terminals of the MOS devices which offers linear dynamic range of ±80 mV. The simulation shows, it has a linearity error of 5.6 %, THD of nearly 5 % and ?3 dB band width of 221 kHz. Total power consumption is very low i.e. 714 nW. The circuit operates at a supply voltage of 0.5 V and is designed using 180 nm CMOS technology. It is suitable for low power bioelectronics and neural applications.     

A gate-coupled PTLSCR/NTLSCR ESD protection circuit fordeep-submicron low-voltage CMOS ICs

A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS ICs without adding an extra ESD-implant mask. Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress. The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor. Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS ICs can be fully protected against ESD damage. Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit     

High performance analog VLSI computational circuits

Simple linear voltage/current-controlled voltage-to-current (V-T) converters, which are to first-order insensitive to the threshold voltage variation, are introduced. The circuits can be used as basic building blocks to construct simple analog computational circuits, which can perform functions such as square rooting, squaring, multiplication, sum of squares, difference of squares, etc. Some of the key features are: good linearity, floating inputs [high common-mode rejection ratio (CMRR)], simplicity, and good transconductance tuning range. The circuits can be realized with CMOS devices in saturation, however, BiCMOS devices extend their speed and input voltage range. Realistic simulations and experimental results clearly demonstrate the claims     

Novel voltage-mode biquad without external passive elements

This paper introduces a voltage-mode biquad filter using only active devices such as operational amplifiers and operational transconductance amplifiers (OTAs). The circuit configuration is obtained from Soderstrand's active-R state variable filter as a prototype. The proposed circuit can realize five different biquad transfer functions, and the circuit characteristics can be electronically tuned by adjusting the transconductance gains of the OTAs. An example is given, together with simulated results by PSPICE. The circuit configuration is very suitable for implementation in both bipolar and CMOS technologies.     

Voltage-mode active-only biquad

This paper presents a realization of a voltage-mode active-only biquadratic circuit. The proposed circuit is constructed employing solely operational amplifiers and operational transconductance amplifiers (OTAs). The circuit configuration is obtained from a second-order structure with two integrator loops. The circuit can realize low-pass, band-pass, high-pass, band-stop, low-pass notch, high-pass notch and all-pass transfer functions by suitably choosing the input and output terminals, and the circuit characteristics can be electronically tuned through adjusting the transconductance gains of OTAs. Some examples are given together with simulated results by PSPICE. The circuit configuration is very suitable for implementation in both bipolar or CMOS technologies.     

Current mode filters with reduced complexity using a single EX-CCCII

In this paper an active element Extra-X current controlled conveyor (EX-CCCII) is used to reduce the complexity of some existing circuits. Two second-order current-mode biquadratic filter circuits are proposed, each using a single active element and two grounded capacitors. The first circuit is three input single output (TISO) and the second one is single input three outputs (SITO) biquadratic filter. The First circuit can realize all the standard filter transfer functions, while the second circuit can realize LP, BP and HP responses. The study of non-idealities and parasitics of the active element and their effects on transfer functions is carried out. The new circuits are found to be simpler than the earlier ones in terms of number of transistors. The functionality of the proposed biquadratic filters is verified through detailed PSPICE simulations using 0.25 µm TSMC CMOS technology parameters.     

Wide-Linear-Range Subthreshold OTA for Low-Power, Low-Voltage, and Low-Frequency Applications

We propose a novel configuration of linearized subthreshold operational transconductance amplifier (OTA) for low-power, low-voltage, and low-frequency applications. By using multiple input floating-gate (MIFG) MOS devices and implementing a cubic-distortion-term-canceling technique, the linear range of the OTA is up to 1.1 Vpp under a 1.5-V supply for less than 1% of transconductance variation, according to testing results from a circuit designed in a double-poly, 0.8-$muhbox m$, CMOS process. The power consumption of the OTA remains below 1$muW$for biasing currents in the range between 1–200 nA. The offset voltage due to secondary effects (contributed by parasitic capacitances, errors and mismatches of parameters, charge entrapment, etc.) is of the order of a few ten millivolts, and can be canceled by adjusting biasing voltages of input MIFG MOS transistors.     

Moving average filter for spur reduction in subsampling fractional PLLs

A mono-bit digital receiver circuit for instantaneous frequency measurement is presented. The circuit is co-designed with Indium Phosphide Double Heterojunction Bipolar Transistor and complementary metal oxide semiconductor (CMOS) devices. The chip is fabricated by InP/CMOS three-dimensional (3D) heterogeneous integration using the wafer-level bonding technique. The measurable signal frequency within?+?15 to???25 dBm power is up to 7.5 GHz with a 14-GHz clock. Compared to an integrated circuit (IC) with a traditional InP or CMOS technologies, the proposed chip could benefit from both InP and CMOS technology. In the heterogeneous integration, InP devices provide high operating frequency, broad signal bandwidth, and large input signal dynamic range, while CMOS devices achieve complex function with low power consumption. In this way, the system FoM is improved for a mono-bit digital receiver while the system power consumption is kept the same. This work also shows the great potential of the 3D heterogeneous integration for the high-performance mixed-signal and multifunction radio-frequency ICs.

     

A 700-MHz switched-capacitor analog waveform sampling circuit

Analog switched-capacitor memory circuits are suitable for use in a wide range of applications where analog waveforms must be captured or delayed, such as the recording of pulse echo events and pulse shapes. Analog sampling systems based on switched-capacitor techniques offer performance superior to that of flash A/D converters and charge-coupled devices with respect to cost, density, dynamic range, sampling speed, and power consumption. This paper proposes an architecture with which sampling frequencies of several hundred megahertz can be achieved using conventional CMOS technology. Issues concerning the design and implementation of an analog memory circuit based on the proposed architecture are presented. An experimental two-channel memory with 32 sampling cells in each channel has been integrated in a 2-μm CMOS technology with poly-to-poly capacitors. The measured nonlinearity of this prototype is 0.03% for a 2.5 V input range, and the memory cell gain matching is 0.01% rms. The dynamic range of the memory exceeds 12 b for a sampling frequency of 700 MHz. The power dissipation for one channel operated from a single +5 V supply is 2 mW     

Piecewise Nonlinear Approach to the Implementation of Nonlinear Current Transfer Functions

A piecewise nonlinear approach to the nonlinear circuit design has been proposed in this paper. It is to approximate a target nonlinear transfer function by a particular combination of selected nonlinear pieces. The pieces can be produced by one or more analog blocks involving nonlinear devices. This approach can be applied to design nonlinear circuits to implement various current transfer functions. By controlling the operation modes of the transistor pair in a simple current mirror, one can modulate the current transfer function in a radical or fine-tuning manner. It is thus possible for the same current mirror to generate very different nonlinear pieces in different sections of its input range. In order that the control is done automatically by the input current, or in other words, the operation of the transistors is made to be input-current-dependent in a controlled manner, a series structure of two transistors has been proposed to be incorporated in the current mirror. The dependency can be made different by placing the structure in different places of the current mirror and/or by making the two transistors complementary or not, which makes the variations of the nonlinear function. Several current mirrors have been designed. Each of them consists of a very small number of transistors and performs a defined nonlinear current transfer function. The circuits have been simulated with HSPICE to validate the functions. The successful results have been obtained and are presented in the paper.     

Design of a very linear CMOS transconductance input stage forcontinuous-time filters

A CMOS differential input stage for transconductance amplifiers that combines a low noise excess factor, low input capacitance, and high common-mode rejection ratio with a very good linearity is described. The measured distortion is only 0.2% for a 1-V RMS input signal and only 1% for a 2-V RMS input signal on a test circuit implemented in a standard 3-μm CMOS process, using ±5-V supplies, resulting in over 85 dB of dynamic range. Applications include high-performance continuous-time filters and linear amplifiers     

Low-voltage CMOS subthreshold four-quadrant tripler

A CMOS four-quadrant tripler using transistors operated in the subthreshold region is presented. The goal of this circuit is to realize the product of three input signals. This circuit has been implemented in a 0.8 m single-poly double-metal n-well CMOS process. Experimental results show that for a power supply of ±1.5V, the linear input range of this tripler is within ±100mV with the linearity error less than 2%. The total harmonic distortion is less than 2.5% with input range up to ±100mV. The-3dB bandwidth of this tripler is measured to be about 700 kHz.