Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.     

Feasibility Study of 45-nm-Node Scaled-Down Cu Interconnects With Molecular-Pore-Stacking (MPS) SiOCH Films

A feasibility study was done for 45-nm-node Cu interconnects using a novel molecular-pore-stacking (MPS) SiOCH film (k = 2.45), taking electron scattering in the scaled-down Cu lines into consideration. The as-deposited MPS SiOCH film, formed by plasma polymerization of a robust six-member-ring (hexagonal) siloxane with large steric-hindered hydrocarbon side chains, has self-organized subnanometer pores. An oxidation-damage-free dual-hard-mask etching process, along with a benzocylobuten liner technique, preserved the low permittivity of the MPS film in the Cu lines, with excellent interline dielectric reliability. The line aspect ratio was also balanced to decrease not only the interconnect parasitic capacitance but also the Cu line resistivity, which is increased by the electron scattering in the narrow lines. By combining the above etching process and the line-aspect control, the feasibility of the MPS SiOCH film was confirmed with outstanding performance and excellent reliability for the 45-nm-node ultralarge scale integrations     

Comprehensive Chemistry Designs in Porous SiOCH Film Stacks and Plasma Etching Gases for Damageless Cu Interconnects in Advanced ULSI Devices

High performance Cu dual-damascene (DD) interconnects without process-induced damages are developed in porous SiOCH stacks with the effective dielectric constant $(k _{rm eff})$ of 2.95, in which a carbon (C)-rich molecular-pore-stacking (MPS) SiOCH film $(k=2.5)$ is stacked directly on an oxygen (O)-rich porous SiOCH $(k=2.7)$ film. The novel etch-stopperless structure is obtained by comprehensive chemistry design of C/O ratios in the SiOCH stack and the etching plasma of an ${hbox{Ar}}/ {hbox{N}} _{2} / {hbox{CF}} _{4} / {hbox{O}} _{2}$ gas mixture technique. Large hydrocarbons attached to hexagonal silica backbones in the MPS–SiOCH prevent the Si–CHx bonds from oxidation during ${hbox{O}} _{2}$-plasma ashing, suppressing the C-depleted damage area at the DD sidewall. Combining multiresist mask process with immersion ArF photolithography, strictly controlled Cu DD interconnects with 180-nm pitched lines and 65-nm-diameter vias are obtained successfully, ready for the 300-mm fabrication.      

Robust Low Oxygen Content Cu Alloy for Scaled-Down ULSI Interconnects Based on Metallurgical Thermodynamic Principles

A low oxygen content (LOC) CuAl alloy with no barrier metal (Ta) oxidation was obtained using an oxygen absorption process based on metallurgical thermodynamic principles. LOC CuAl dual damascene interconnects (DDIs) were successfully implemented into 45-nm-node LSIs with 140-nm-pitched lines and 70-nm-diameter $(phi)$ vias. An oxygen absorber of very thin Al film, which was deposited on an electrochemically deposited (ECD) Cu film, captured the oxygen atoms in the ECD Cu due to its larger negative change in the standard Gibbs-free energy of oxidation than in the Cu and the barrier (Ta), preventing the Ta barrier from oxidizing during high-temperature annealing. The high-quality Cu/barrier interface in the LOC CuAl DDIs remarkably improved the via reliability against stress-induced voiding and electromigration. No reliability degradation of the 70-nm-$phi$ vias was observed in the 45-nm-node LOC CuAl DDIs, while keeping the scalability from the 65-nm-node generation.      

Simulations of diffusion barrier deposition on porous low-k films

Implementation of Cu/low-k in advanced interconnections requires a diffusion barrier to prevent copper penetration in low-k dielectrics. The barrier should be continuous to prevent copper diffusion and thin enough to keep interconnection line resistance low. Deposition of a diffusion barrier becomes an issue when porous low-k dielectrics are used. We developed a Monte Carlo simulation model to describe deposition of a diffusion barrier on a porous low-k film. The model provided explanation for the sealing behavior of different porous film by TaN diffusion barrier. Previously we have shown that TaN barrier integrity depends on chemical nature of the substrate rather than on porous structure: the same barrier can be continuous on oxycarbide (SiOCH) but non-continuous on HSQ (hydrogen silsesquioxane) although porous structures of the two films are similar. Using the model, we show that surface diffusion of TaN during deposition plays a key role in continuous barrier formation. Presence of carbon suppresses TaN diffusion (probably by TaC formation) and the barrier does not penetrate deep into the film forming a continuous layer on the top surface. The model is also able to predict sealing behavior for different porous low-k films with different porosity/pore sizes.     

Influence of low-k dry etch chemistries on the properties of copper and a Ta-based diffusion barrier

In this study, the film properties of Cu and a Ta-based diffusion barrier deposited on organic polymer and SSQ-based low-k materials with subtractive porosity were investigated. Emphasis was put on the effects of exposure of the low-k materials to the dry etch plasmas prior to metal deposition. The metal film properties were influenced by the type of the dry etch plasma chemistry used and by the porosity of the low-k material. Thermal desorption spectra (TDS) obtained during annealing of these metal films revealed an increased amount of species with m/e 44, attributed to CO₂, and H₂O desorbing from the Cu film at high temperatures. The TDS data for the Ta film did not contain such high temperature desorption peaks for these species mentioned. Surface morphology of the Cu and Ta films observed by scanning electron microscopy (SEM) and atomic force microscopy (AFM) also showed a poor wetting of the metal films on the porous low-k materials that have been dry etch plasma treated.     

Patterning of narrow porous SiOCH trenches using a TiN hard mask

For the next technological generations of integrated circuits, the traditional challenges faced by etch plasmas (profile control, selectivity, critical dimensions, uniformity, defects, …) become more and more difficult, intensified by the use of new materials, the limitations of lithography, and the recent introduction of new device structures and integration schemes. Particularly in the field of the interconnect fabrication, where dual-damascene patterning is performed by etching trenches and vias in porous low-k dielectrics, the main challenges are in controlling the profile of the etched structures, minimizing plasma-induced damage, and controlling the impact of various types of etch stops and hard mask materials. Metallic hard masks can help thanks to their high selectivity toward low-k materials, and by avoiding low-k exposure to potentially degrading ashing plasmas. In this paper, we will present some key issues related to the patterning of narrow porous SiOCH trenches with a metallic (TiN) hard mask. Narrow trenches (down to 40 nm width) can be opened into TiN with a critical dimensions bias (around 10 nm) attributed to carbon and silicon containing deposits on the photoresist and TiN sidewalls during the etching. Porous SiOCH etching using a TiN hard mask instead of the conventional SiO₂ hard mask may lead to severe profile distortions, attributed to TiF_x compounds which settle on the trenches sidewalls. A chuck temperature of 60 °C and fluorine-rich plasmas are required to minimize those distortions. An etching process leading to almost straight porous SiOCH profiles presenting a slight bow has been developed. However a wiggling phenomenon has been evidenced for the etching of narrow and deep trenches. This phenomenon is attributed to the highly compressive residual stress in the TiN hard mask, which is released when the dielectric is not mechanically strong enough to withstand it.     

Efficiency of reducing and oxidizing ash plasmas in preventing metallic barrier diffusion into porous SiOCH

This work focuses on the efficiency of reducing and oxidizing plasma chemistries in preventing metallic barrier diffusion into porous dielectric materials (SiOCH with a k value close to 2.2, porosity content around 40%). The ash processes have been performed on SiOCH coated blanket and patterned wafers in either reactive ion etching (RIE) or downstream (DS) reactors. The Rutherford backscattering spectroscopy technique (RBS) has shown that titanium based compounds diffuse into the blanket porous SiOCH without treatment during a typical TiN barrier deposition process by chemical vapor deposition (CVD). The metallic barrier diffusion is strongly limited on blanket wafers when the porous SiOCH has been previously modified (partially or fully) by ash plasmas (RIE-O₂, RIE-NH₃, DS-H₂/N₂ and DS-O₂/N₂) while the metallic barrier diffusion occurs with no modifying ash plasmas (DS-H₂/He). We have shown that ellipsometric porosimetry (EP) measurements clearly point out that no complete pore sealing is achieved with all the investigated ash plasmas. Energy-filtering transmission electron microscopy experiments (EFTEM) performed on single damascene structures have revealed significant titanium diffusion into the porous dielectric lines for DS-H₂/He and RIE-O₂ and sidewalls modification of the porous SiOCH lines (lower C/O ratio) for all the ash plasmas. The RC product (resistance × capacitance) have been extracted from the single damascene structures and the evolution of RC product will be discussed in terms of lines modification (titanium diffusion and porous SiOCH modification).     

Interface characteristics of selective tungsten on silicon using anew pretreatment technology for ULSI application

The characteristics of selective tungsten film on silicon strongly depend on the surface properties of the underlying substrate. In this work, a new pretreatment process prior to selective tungsten film deposition has been developed. A CF₄/O₂ mixed plasma modification procedure and a subsequent O₂ plasma ashing step combine to achieve efficient surface precleaning. The damage and contamination induced by reactive ion etching (RIE) are thus eliminated. Concurrently, a subsequent anhydrous HF cleaning was used to remove the native oxide on silicon as well as to obtain a fluorine-passivated silicon surface which can avoid reoxidation during the transport of wafers. This new pretreatment technology produces tungsten films that retain superior physical properties within the aspects of deposition rate, film morphology, and selectivity. Also, excellent interface characteristics with low silicon consumption, low contact resistance, low contact leakage current, and fewer impurities of fluorine, oxygen, and carbon within the interfacial region are obtained     

Ti-Rich Barrier Layers Self-Formed on Porous Low-k Layers Using Cu(1?at.%?Ti) Alloy Films

To investigate the applicability of the technique of barrier self-formation using Cu(Ti) alloy films on porous low-k dielectric layers, Cu(1 at.% Ti) alloy films were deposited on porous SiOCH (low-k) dielectric layers in samples with and without ~6.5-nm-thick SiCN pore seals. Ti-rich barrier layers successfully self-formed on the porous low-k layer of both sample types after annealing in Ar for 2 h at 400°C to 600°C. The Ti-rich barrier layers consisted of amorphous Ti oxides and polycrystalline TiC for the samples without pore sealing, and amorphous TiN, TiC, and Ti oxides for the pore-sealed samples. The amorphous TiN originated from reaction of Ti atoms with the pore seal, and formed beneath the Cu alloy films. This may explain two peaks of Ti segregation at the interface that appeared in Rutherford backscattering spectroscopy (RBS) profiles, and suggests that the Ti-rich barrier layers self-formed by the reaction of Ti atoms with the pore seal and porous low-k layers separately. The total molar amount of Ti atoms segregated at the interface in the pore-sealed samples was larger than that in the samples without pore sealing, resulting in lower resistivity. On the other hand, resistivity of the Cu alloy films annealed on the porous low-k layers was lower than that annealed on the nonporous low-k layers. Coarser Cu columnar grains were observed in the Cu alloy films annealed on the porous low-k layers, although the molar amount of Ti atoms segregated at the interface was similar in both sample types after annealing. The cause could be faster reaction of the Ti atoms with the porous dielectric layers.     

Preparation of porous ultra low k films using different sacrificial porogen precursors for 28 nM technological node

In order to reduce resistance capacitance (RC) delay and crosstalk between adjacent interconnect lines, the porous ultra low k (PULK) film with dielectric constant value ranging from 2.4 to 2.6 was introduced to be used as an insulator of the Cu integration in back end of the line (BEOL) for 28 nm technological node. In this paper, the PULK films were deposited by plasma enhanced chemical vapor deposition (PECVD) using two different sacrificial organic porogen precursors of bicycloheptadiene (BCHD) and alpha-terpinene (ATRP), and then the above co-deposited films were expose to UV radialization for removing sacrificial organic porogens to create pores. The effects of the different sacrificial organic porogen on the PULK film properties such as the dielectric constant, pore and porosity, k shift, mechanic strength, and RC were studied in detail. Results indicated that the hardness and modulus of the PULK film for the BCHD and ATRP precursors were 0.7 and 5.1 GPa and 1.0 and 7.1 Gpa, and their pore radiuses and porosities were 1.18 nm and 25% and 0.95 nm and 23%. The dielectric constant value of the PULK film for the BCHD and ATRP precursors were measured as 2.48 and 2.59 with Hg probe. The adhesion test indicated that the interfacial strength of the PULK film for the ATRP precursor was higher than that of the PULK film for the BCHD precursor. By the RC examination, it was seen that RC curve of the PULK film for the ATRP precursor was located below the curve of the PULK film for the BCHD precursor.     

Amorphous silicon as a resist material

Lithographic properties of amorphous silicon films exposed to glow-discharge hydrogen plasma and ion beams have been investigated. The rate of film etching by a CF₄ plasma is lowered by exposure, giving rise to a negative resist behavior of the material. The sensitivity and contrast are ~10¹⁸ ions/cm² and 1.1, respectively. The effect of exposure time on etching characteristics was also studied     

Advanced CD Control Technology for 65-nm Node Dual Damascene Process

This paper describes an advanced critical dimension (CD) control technology for a 65-nm node dual damascene process and beyond. A newly developed deposition enhanced shrink etching (DESE) process was introduced into both via and trench etching. This technology realizes not only dynamic via shrink ranging 40 nm but also accurate trench CD control by feedforward technology. Etching performance was investigated by electrical results of 65-nm Cu/low-k interconnects using porous chemical-vapor deposition SiOC. The 100% yields of 60-M via chains verified the DESE process robustness.     

Reactive ion etching for VLSI

Reactive Ion Etching (RIE) is a dry etching technique that is used to etch 1-µm and submicrometer patterns into films of silicon and silicon compounds. RIE is suitable for VLSI applications because etching is anisotropic and proceeds via chemical reactions with the substrate. Anisotropic etching allows faithful reproduction of resist patterns into the films that make up a device, and chemical etching allows development of selective etching by manipulating the composition of the plasma. The RIE reactor is described and examples of its use to fabricate 1-µm MOSFET's are given. Concerns arising from the presence of a voltage between the substrates and the plasma, radiation damage of SiO2and contamination of silicon, are discussed.     

The effects of UV radiation with single and dual wavelengths on the properties of porous ultra low k film

The diethoxymethylsilane precursor as a network matrix and alpha-terpinene precursor as a sacrificial porogen were applied to co-deposit SiOCH film using a plasma enhanced chemical vapor deposition. Subsequently, the UV radiation was performed to remove the porogens from the co-deposited SiOCH film for creating pores to form porous ultra low k (p-ULK). The main purpose of this paper was to investigate the properties of the p-ULK film treated using the different UV radiation wavelengths including single wavelength emitted from H⁺ type bulb, dual wavelengths emitted from D type bulb, and dual wavelengths combined with single wavelength. Result indicated that the properties of the p-ULK film treated using the dual wavelength first and then single wavelength were the best among the above three kinds of the UV radiation methods. Nanoindentation and strain gauge test indicated that the hardness and modulus of the p-ULK film were improved about 43% and 38%. Fourier transform infrared spectroscopy examination indicated that the scission of Si–CH₃ bond was also the lowest. Transmission electron microscopy observation indicated that the undercut size in the interface between hardmask and p-ULK film was also the smallest. Therefore, the UV radiation using the D type bulb first and then H⁺ type bulb was a potential solution to improve the properties of the p-ULK film.     

Formation and characterization of porous silicon films obtained by catalyzed vapor-chemical etching

Porous silicon films obtained by the metal-assisted vapor-chemical etching technique have been characterized. For the film formation, epitaxial (100) N/P⁺, 1–5 Ω cm monocrystalline silicon wafers were used. The vapors of an alcoholic solution of H₂O₂/HF were drawn towards the silicon surface, which was previously covered with a thin layer of gold (~8 nm) for the catalytic etching. For the optical and morphological characterization of porous films, Raman spectroscopy, Ellipsometry, FTIR spectroscopy and SEM images were used. The films thickness kept a linear relationship with etching time. A porosity gradient from the surface towards the interface (65% to 12%) was observed in the films. A large amount of Si–H bonds as related to O–Si–O bonds were observed and the pore size depends on the HF concentration. Irregular morphology was found in films formed with 50% HF.     

A study of residual stress distribution through the thickness of p+ silicon films [thermal oxidation effects]

The effect of thermal oxidation on the residual stress distribution throughout the thickness of heavily-boron-doped (p⁺ ) silicon films is studied. The deflection of p⁺ silicon cantilever beams due to residual stress variation throughout the film thickness is studied for as-diffused and thermally oxidized films. Cantilevers of as-diffused p⁺ silicon films display a positive curvature (or a negative bending moment), signified by bending up of the beams. Thermal oxidation of the films prior to cantilever fabrication by anisotropic etching modifies the residual stresses in the p⁺ film, specially in the near-surface region (i.e. the top 0.3 to 0.5 μm for the oxidation times used here), and can result in beams with a negative curvature even when the oxide is removed from the p⁺ silicon cantilever surface subsequent to cantilever fabrication     

Chemical and mechanical adhesion mechanisms of sputter-depositedmetal on epoxy dielectric for high density interconnect printed circuitboards

Strong chemical reactions between metal and polymer substrates significantly enhance adhesion of the metal to the polymer. This study investigated the adhesion of three types of thin film metals, including Cu, NiCr, and Cr, to a fully epoxy-based polymer. Before depositing these thin film metals, the epoxy surface was treated with either an Ar or O₂ plasma etch. It was found that NiCr and Cr produced higher peel strengths than Cu, but NiCr and Cr did not produce different peel strengths than each other. It was also found that O₂ plasma etch produced significantly higher peel strengths than Ar plasma etch for Cu and Cr, but not for NiCr. An XPS (X-ray photoelectron spectroscopy) study was performed to investigate the reactivities and possible chemical adhesion mechanisms of the metal thin films with the epoxy. It was determined that Cr reacted more strongly than Ni in forming metal oxide at the metal-epoxy interface. Cu was not seen to react strongly in forming oxide with the epoxy. Thermodynamic information supported the relative amounts of oxides found by XPS. Thermodynamic information also suggested that O₂ plasma etch did not produce significantly higher adhesion than Ar plasma etch on the NiCr samples due to the large Ni component of the NiCr thin film. An AFM (atomic force microscopy) study was performed to investigate possible mechanical adhesion mechanisms. Implications of the AFM results were that the main adhesion mechanism for all samples was chemical and that the Cu oxide that was available on the Cu samples was beyond the detection limits of the XPS equipment     

Low-Roughness Plasma Etching of HgCdTe Masked with Patterned Silicon Dioxide

A novel mask technique utilizing patterned silicon dioxide films has been exploited to perform mesa etching for device delineation and electrical isolation of HgCdTe third-generation infrared focal-plane arrays (IRFPAs). High-density silicon dioxide films were deposited at temperature of 80°C, and a procedure for patterning and etching of HgCdTe was developed by standard photolithography and wet chemical etching. Scanning electron microscopy (SEM) showed that the surfaces of inductively coupled plasma (ICP) etched samples were quite clean and smooth. Root-mean-square (RMS) roughness characterized by atomic force microscopy (AFM) was less than 1.5 nm. The etching selectivity between a silicon dioxide film and HgCdTe in the samples masked with patterned silicon dioxide films was greater than 30:1. These results show that the new masking technique is readily available and promising for HgCdTe mesa etching.     

Effects of wafer temperature on plasma charging induced damage toMOS gate oxide

The effect of wafer temperature on damage to thin MOS gate oxide from plasma has been investigated for the first time. As the wafer surface temperature during an O₂ plasma exposure increases from 145°C to 340°C, the damage measured from charge-to-breakdown (Q_bd) increases dramatically. This result agrees with Fowler-Nordheim tunneling current mechanism for plasma charging and the temperature activated damage model. The increase of damage at higher wafer processing temperature indicates that elevated temperature plasma processes, such as plasma enhanced CVD and Cu etching, can be expected to be more susceptible to charging damage than low temperature plasma processes