考虑偏置温度不稳定性的软差错率分析

纳米工艺下,老化效应与软差错共同引发的集成电路可靠性问题至关重要。该文分析偏置温度不稳定性(BTI),包括负偏置温度不稳定性(NBTI)和正偏置温度不稳定性(PBTI)对软差错率的影响,提出从关键电荷值和延迟两个因素综合考虑。首先分析BTI效应下两个因素如何变化,推导了延迟受BTI影响的变化模型,介绍关键电荷的变化机理。然后探讨将两个因素结合到软差错率(SER)评估中,推导了融入关键电荷值的SER计算模型,提出将延迟的变化导入到电气屏蔽中的方法。基于ISCAS89基准电路上的实验验证了综合两种因素考虑BTI效应评估SER的有效性和准确性。     

基于四值脉冲参数模型的单粒子瞬态传播机理与软错误率分析方法

随着工艺尺寸的不断缩小,由单粒子瞬态(Single Event Transient, SET)效应引起的软错误已经成为影响宇航用深亚微米VLSI电路可靠性的主要威胁,而SET脉冲的产生和传播也成为电路软错误研究的热点问题。通过研究SET脉冲在逻辑链路中的传播发现：脉冲上升时间和下降时间的差异能够引起输出脉冲宽度的展宽或衰减;脉冲的宽度和幅度可决定其是否会被门的电气效应所屏蔽。该文提出一种四值脉冲参数模型可准确模拟SET脉冲形状,并采用结合查找表和经验公式的方法来模拟SET脉冲在电路中的传播过程。该文提出的四值脉冲参数模型可模拟SET脉冲在传播过程中的展宽和衰减效应,与单参数脉冲模型相比计算精度提高了2.4%。该文应用基于图的故障传播概率算法模拟SET脉冲传播过程中的逻辑屏蔽,可快速计算电路的软错误率。对ISCAS89及ISCAS85电路进行分析的实验结果表明：该方法与HSPICE仿真方法的平均偏差为4.12%,计算速度提升10000倍。该文方法可对大规模集成电路的软错误率进行快速分析。     

Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits

Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to radiation-induced single-event-upsets (SEUs). Redundancy insertion has been adopted to provide the circuit with additional transient error resiliency. However, its applicability and efficiency are limited by the tight design constraints and budgets. In this paper, we present an intelligent “constraint-aware robustness insertion” methodology. By selectively protecting sequential elements in static CMOS digital circuits, it is able to maximally improve the SEU tolerance while keeping the incurred design overhead within acceptable range. Our technique consists of three major components. The first one is a configurable hardening sequential cell design that serves as the basic building block of the framework; the second one is a robustness calibration technique that evaluates the relative error tolerance of all sequential elements and provides guidelines to the redundancy insertion; the third one is an optimization algorithm that searches for the optimal protection scheme under given design constraints and budgets. Simulation results show that the intelligent robustness insertion reduced the error rate by 46% with zero timing penalty and 10% area increase. Furthermore, by exploring the tradeoffs between reliability and design overhead, we also demonstrate the proposed technique can help achieve high reliability improvement while keeping the design overhead within acceptable range.      

基于Matlab带阻滤波器电路设计及参数寻优

各种滤波器电路在模拟电路设计中经常出现,由于在实际工程中,电阻、电容的值均连续,因此在设计电路时,电路参数计算繁冗且计算量大,并且手工计算出的结果并非是一个最优解,文中借助Matlab的计算功能,根据带阻滤波器的传递函数,建立了相应的标准电路模型以及参数最优化模型,最后使用Matlab中的数学工具箱编写出相应的求解程序,可以快速得到符合要求的电路参数,大幅提高了设计效率,有较强的实用性。     

Modeling and Simulation for Transient Thermal Analyses Using a Voltage-in-Current Latency Insertion Method

This article presents a modeling and simulation method for transient thermal analyses of integrated circuits(ICs) using the original and voltage-in-current(VinC) latency insertion method(LIM). LIM-based algorithms are a set of fast transient simulation methods that solve electrical circuits in a leapfrog updating manner without relying on large matrix operations used in conventional Simulation Program with Integrated Circuit Emphasis(SPICE)-based methods which can significantly slow down the sol...     

Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs

Radiation-induced soft errors are the major reliability threat for digital VLSI systems. In particular, field-programmable gate-array (FPGA)-based designs are more susceptible to soft errors compared to application-specific integrated circuit implementations, since soft errors in configuration bits of FPGAs result in permanent errors in the mapped design. In this paper, we present an analytical approach to estimate the soft error rate of designs mapped into FPGAs. Experimental results show that this technique is orders of magnitude faster than the fault injection method while more than 96% accurate. We also present a highly reliable and low-cost soft error mitigation technique which can significantly improve the availability of FPGA-mapped designs. Experimental results show that, using this technique, the availability of an FPGA mapped design can be increased to more than 99.99%.     

一种基于摆率增强的快速瞬态响应LDO电路北大核心

设计了一种基于摆率增强的快速瞬态响应无片外电容LDO电路。其中，误差放大器采用电流镜跨导结构，降低了频率补偿的难度系数；设计了一种可以为功率管栅极提供额外充放电电流的瞬态提升电路(TEC),能快速响应负载的变化，增大摆率，有效提升了负载瞬态响应。仿真结果表明，电路仅使用简单的密勒密勒补偿，即可实现相位裕度在全负载范围内大于60°;在0.5μs的时间内，负载在100μA和100 mA之间发生跳变，电路的下冲电压和过冲电压分别是69 mV和64 mV,稳定时间分别是0.89μs和0.86μs。相较无TEC,本文电路的下冲/过冲电压分别衰减73%和78%,负载瞬态响应显著提升。     

用Multisim分析二阶低通滤波器电路

以Multisim为平台分析了二阶低通滤波器电路。使用虚拟示波器等虚拟元件,采用交流分析方法和参数扫描分析方法仿真分析了二阶低通滤波器电路的工作特性,及各元件参数对输入输出特性的影响,并演示了Multisim中虚拟仪器及各种分析方法的使用。仿真得到了该电路在低频状态下的通带电压放大倍数AUP=2,电路的截止频率fP=148.495 2 Hz。仿真结果与理论计算相符。     

准椭圆函数滤波器原型电路参数的优化提取

准椭圆函数滤波器是一种新型的高性能滤波器形式 ,但是由于其原型电路的形式比较复杂 ,用经典综合的方法提取其参数的效率很低 ,限制了这种形式滤波器的应用。本文结合遗传算法和Solvopt算法 ,提出了一种新的有效而灵活的准椭圆函数滤波器原型电路参数的优化提取方法     

消除噪声的一种变步长自适应滤波方法

在电子系统中不可避免地会受到噪声的干扰．用固定参数的滤波器进行消除噪声有其缺陷，它对信号与噪声的先验知识需要得较多．本文讨论了用一种变步长自适应滤波器消除噪声的方法．实验仿真证明这种方法能有效地去除弱信号中的噪声．     

消除噪声的一种变步长自适应滤波方法

在电子系统中不可避免地会受到噪声的干扰。用固定参数的滤波器进行消除噪声有其缺陷,它对信号与噪声的先验知识需要得较多。本文讨论了用一种变步长自适应滤波器消除噪声的方法。实验仿真证明这种方法能有效地去除弱信号中的噪声。     

A Fast Statistical Soft Error Rate Estimation Method for Nano-scale Combinational Circuits

Nano-scale digital integrated circuits are getting increasingly vulnerable to soft errors due to aggressive technology scaling. On the other hand, the impacts of process variations on characteristics of the circuits in nano era make statistical approaches as an unavoidable option for soft error rate estimation procedure. In this paper, we present a novel statistical Soft Error Rate estimation framework. The vulnerability of the circuits to soft errors is analyzed using a newly defined concept called Statistical Vulnerability Window (SVW). SVW is an inference of the necessary conditions for a Single Event Transient (SET) to cause observable errors in the given circuit. The SER is calculated using a probabilistic formulation based on the parameters of SVWs. Experimental results show that the proposed method provides considerable speedup (about 5 orders of magnitude) with less than 5 % accuracy loss when compared to Monte-Carlo SPICE simulations. In addition, the proposed framework, keeps its efficiency when considering a full spectrum charge collections (more than 36X speedups compared to the most recently published similar work).     

Low-Power Resonant Clocking Using Soft Error Robust Energy Recovery Flip-Flops

An energy recovery or resonant clocking scheme is very attractive for saving the clock power in nanoscale ASICs and systems-on-chips, which have increased functionality and die sizes. The technology scaling followed Moore’s law, that lowers node capacitance and supply voltage, making nanoscale integrated circuits more vulnerable to radiation-induced single event upsets (SEUs) or soft errors. In this work, we propose soft-error robust flip-flops (FFs) capable of working with a sinusoidal resonant clock to save the overall chip power. The proposed conditional-pass Quatro (CPQ) FF and true single phase clock energy recovery (TSPCER) FF are based on a unique soft error robust latch, which we refer to as a Quatro latch. The proposed C²-DICE FF is based on a dual interlocked cell (DICE) latch. In addition to the storage cell, each FF consists of a unique input-stage and a two-transistor, two-input output buffer. In each FF with a sinusoidal clock, the transfer unit passes the data to the Quatro and DICE latches. The latches store the data values at two storage nodes and two redundant nodes, the latter enabling recovery from a particle-induced transient with or without multiple-node charge sharing. Post-layout simulations in 65nm CMOS technology show that the FF exhibits as much as 82% lower power-delay product compared to recently reported soft error robust FFs. We implemented 1024 proposed FFs distributed in an H-tree clock network driven by a resonant clock-generator that generates a 1–5 GHz sinusoidal clock signal. The simulation results show a power reduction of 93% on the clock tree and total power saving of up to 74% as compared to the same implementation using the conventional square-wave clocking scheme and FFs.     

采用背景提取和自适应滤波的视频降噪算法

针对监控视频图像背景固定的特点,提出一种有效去除高斯噪声和脉冲噪声的降噪算法.首先通过分析噪声设计一种提取视频序列背景图像的算法,然后对运动区域采用自适应像素域滤波算法来进行处理.该算法根据最小可觉差和视频图像特征自适应地选择谐波均值滤波、加权算术平均滤波、α-截尾均值滤波和中值滤波.为评估降噪算法性能,将降噪处理前后的视频序列分别进行MPEG-2编码,并改变目标码率对比视频质量.实验结果显示:降噪处理后的视频能够用更少的(约50%)比特数获得相同的主、客观视频质量;或者用相同的比特数获得更高的视频质量.     

Gate Circuit Layout Optimization of Power Module Regarding Transient Current Imbalance

The layout of power multichip modules is one of the key points of a module design, especially for high power densities, where couplings are enlarged. This paper focuses on dynamic current imbalance between paralleled chips. It can be principally attributed to gate circuit dissymmetry, which modifies inductances and coupling, especially with the power circuit. This paper describes the analysis of an existing power module. An optimization process based on a modification of the gate circuit geometry allows balancing current during switching phases. This approach will be validated with experimental measurements and applied on an existing module.     

基于连续校验和的模拟检错电路硬件开销的优化

基于连续校验和的模拟电路并发检错与纠错技术，可以用来设计具有容错能力的模拟电路，然而，检错电路的硬件开销在实际应用中是一个不能忽略的问题，本文对此进行了研究。     

Soft Fault Diagnosis of Analog Circuit Based on Particle Swarm Optimization

A single soft fault diagnosis method for analog circuit with tolerance based on particle swarm optimization （PSO） is proposed. The parameter deviation of circuit elements is defined as the element of particle. Node-voltage incremental equations based on the sensitivity analysis are built as constraints of a linear programming （LP） equation. Through inducing the penalty coefficient, the LP equation is set as the fitness function for the PSO program. After evaluating the best position of particles, the position of the optimal particle states whether the actual parameter is within tolerance range or not. Simulation result shows the effectiveness of the method.     

Bit Rate Reduction of Digitized Speech Using Entropy Techniques

We present the results of a study to reduce the bit rate of speech that has been digitized with a continuously variable slope delta modulator (CVSD) operating at 16, 24, and 32 kbits/s. The theoretical reduction is found from the bit stream entropy. The actual reduction, via Huffman coding, is within 1-2 Percent of the theoretical value. The conditional entropy indicates that additional bit rate reduction can be achieved if we use a set of Huffman codes, conditioned on the past CVSD bits. A third technique, tandem coding, using a maximum likelihood predictor in tandem with run length and Huffman coding, is also investigated. Using these entropy techniques, bit rate reductions of 11-25 percent are achieved for the CVSD rates considered. The paper concludes with a study of the buffer requirements needed to support these entropy coders.     

Pulse-Amplitude-Equalization Methods for the Repetition Rate Multiplication Using F-P Filter

The reason of pulse amplitude unequalization at repetition rate multiplying via Fabry-Perot (F-P) filter is analyzed. Several original methods of suppressing the amplitude unequalization are proposed. Their suppressing effects and tolerance to the F-P instability are compared and investigated.     

Fiber Optics Receiver Error Rate Prediction Using the Gram-Charlier Series

This paper applies the Gram-Charlier series method to the caculation of error probabilties in digital optical receivers. This method allows the calculation of "exact" error probabilities including the effects of avalanche noise, thermal noise, and arbitrary posidetection processing filter. The predictions of this method are compared with those of a simple Gaussian approximation and with the Chernoff bounds. Finally, the effects of modal noise are included in the theory, and some specific cases are explored numerically.