A junctionless tunnel field effect transistor with low subthreshold slope

we demonstrate the design of a triple gate n-channel junctionless transistor that we call a junctionless tunnel field effect transistor (JLTFET). The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. Simulation shows significant improvement compared to simple junctionless field effect transistor both in I _ON/I _OFF ratio and subthreshold slope. Here, junctionless tunnel field effect transistors with high-k dielectric and low-k spacers are demonstrated through simulation and shows an ON-current of 0.25 mA/μm for the gate voltage of 2 V and an OFF current of 3 pA/μm (neglecting gate leakage). In addition, our device shows optimized performance with high I _ON/I _OFF (～10⁹). Moreover, a subthreshold slope of 47 mV/decade is obtained for a 50 nm gate length of simulated JLTFET at room temperature which indicates that JLTFET is a promising candidate for switching performance.     

The role of the source and drain contacts on self-heating effect in nanowire transistors

We find that self-heating effects are not pronounced in silicon nanowire transistors with channel length 10 nm even in the presence of the wrap-around oxide. We observe a maximum current degradation of 6% for V _G =V _D =1.0 V in a structure in which the metal gates are far away from the channel. The overall small current degradation is attributed to the significant velocity overshoot effect in these structures. The lattice temperature profile shows moderate temperature rise and velocity of the carriers is slightly deteriorated due to self-heating effects when compared to isothermal simulations.     

High-blocking-voltage UMOSFETs with reformed electric field distribution

A high-performance vertical GaN metal–oxide–semiconductor field-effect transistor (MOSFET) with a U-shaped gate (UMOSFET) and high blocking voltage is proposed. The main concept behind this work is to reform the electric field distribution to achieve high blocking voltage. The proposed structure includes p-regions in the drift region, which we call reformed electric field (REF) regions. Simulations using the two-dimensional SILVACO simulator reveal the optimum doping concentration, and width and height of the REF regions to achieve the maximum depletion region at the breakdown voltage in the drift region. Also, the electric field distribution in the REF-UMOSFET is reformed by producing additional peaks, which decreases the common peaks under the gate trench. We discuss herein the impact of the height, width, and doping concentration of the REF regions on the ON-resistance (R_ON) and blocking voltage. The blocking voltage, specific ON-resistance, and figure of merit \( \left( {{\text{FOM}} = \frac{{V_{{{\text{BR}}}}^{2} }}{{R_{{{\text{ON}}}} }}} \right) \) are 1140 V, 0.587 mΩ cm² (V_GS = 15 V, V_DS = 1 V), and 2.214 GW/cm², respectively. The blocking voltage and FOM are increased by about 72 % and 171 % in comparison with a conventional UMOSFET (C-UMOSFET).     

Integration and characterization of MFISFET using Pb5Ge3O11

Abstract

The first MFIS FETs PMOS using Pt/Pb₅Ge₃O₁₁/ZrO₂/n-Si structure has been successfully fabricated. The PGO thin film was deposited by spin on method. Single phase PGO with strong c-axis orientation and low leakage current was obtained on ZrO₂ substrate. Pt was used as top electrode and the gate stack was dry etched using chlorine chemistry. Using CMOS compatible process, the integration of MFIS FETs is simple and reliable. I_D-V_G and I_D-V_D were characterized on 10 × 10 μrn (L × W) devices. The memory window obtained is about 1.3V with 200nm PGO and 13nm ZrO₂. It is also found that memory window is less dependent on device sizes.     

Ferroelectric properties of SrBi2Ta2O9 thin films on Si (100) with a LaZrO x buffer layer

To obtain a metal–ferroelectric–insulator–semiconductor (MFIS) structure, we fabricated ferroelectric SrBi₂Ta₂O₉ (SBT) film on a p-type Si (100) wafer with a LaZrO _x (LZO) buffer layer by means of a sol–gel technique. The sol–gel deposited LZO film according to the different annealing temperatures had a good surface morphology even though the crystalline phase was not an amorphous phase. In particular, the root-mean-squared (RMS) surface roughness of the 750-°C-annealed LZO film was about 0.365 nm and its leakage current density was about 8.2?×?10^?7 A/cm² at 10 V. A Au/SBT/LZO/Si structure with different SBT film was fabricated. The C–V characteristics of the Au/SBT/LZO/Si structure showed a clockwise hysteresis loop. The memory window width increased as the SBT film thickness increased. The 600-nm-thick SBT film was crystallized in a polycrystalline phase with a highly preferred (115) orientation. The memory window width of the 600-nm-thick SBT film was about 1.94 V at the bias sweep voltage ±9 V and the leakage current density was about 6.48?×?10^?8 A/cm² at 10 V.     

Structural and magnetic evolution of Fe-doped TiO<Subscript>2</Subscript> nanoparticles synthesized by sol-gel method

Nanocrystalline Ti_1-x Fe _x O₂ particles were fabricated via sol-gel method and their structures, morphology and magnetic properties were investigated. The structure of the Ti_1-x Fe _x O₂ nanospheres evolved from mixed anatase and rutile phases to pure anatase phase with increasing iron content. Additionally, it is found the evolution of magnetism: sample x = 3% shows room temperature ferromagnetism while the rests exhibit paramagnetism. The hysteresis loop of sample x = 3% is attributable to paramagnetic and ferromagnetic phase and the paramagnetic and ferromagnetic components are separated. The susceptibility of Ti_1-x Fe _x O₂ increases and then decreases with the increase of Fe content. The magnetism is explained by the BMP theory.     

Enhanced of electrical characteristics of nano-crystal floating gate memory with In2O3 nano-particles embedded in polyimide

We fabricated the nano-floating gate memory (NFGM) with In₂O₃ nano-particles embedded in polyimide gate insulators. Self-assembled In₂O₃ nano-particles were created by chemical reaction between the polymer precursor and the indium film. The particle size and density of In₂O₃ nano-particles were about 7 nm and 6?×?10¹¹ cm^?2, respectively. The electrical characterization of the NFGM with In₂O₃ nano-particles embedded in polyimide layer were measured and the memory window larger than 3.8 V was obtained from the fabricated NFGM devices due to the charging effects of In₂O₃ particles. Subthreshold swing, output current characteristics and retention time of fabricated NFGM devices were considerably improved by the post-annealing process in 3% hydrogen diluted H₂/N₂ ambient.     

Fabrication of Ferroelectric Gate Memory Device Using BLT/HfO2/Si Gate Structure

Ferroelectric gate FET's with BLT/HfO₂ structure were fabricated on 5-inch-scale Si wafer using well-refined CMOS compatible 0.8 μm-based fabrication processes for the first time. We obtained excellent device characteristics and good memory operations of the fabricated n-ch and p-ch MFIS-FET's, in which the memory window and on/off drain current ratio of typical p-ch memory device were measured to be 1.5 V at V_G of ±5 V and 8 orders-of-magnitude, respectively. We also confirmed by evaluating the gate voltage and gate size dependences of device properties that the fabricated devices showed quantitatively reasonable ferroelectric memory operations.     

Fabrication of dome-shaped PZT-epoxy actuator using modified solvent and spin coating technique

Thick film two phase, 0–3 composite PZT-epoxy dome-shaped structures have been fabricated for the first time using a modified solvent and spin coating technique, where a PZT and ethanol solution was dispersed in an epoxy matrix, combined with a hardener, spin coated onto stainless steel sheets, and poled at ~2.2 kV/mm. The electro-mechanical performances of the films were investigated as a function of volume fraction of PZT. The volume fraction of PZT was varied from 0.1 to 0.7 and the piezoelectric coefficients d ₃₁ and d ₃₃ , and the capacitance, C, were measured, and used to calculate the effective dielectric constants. The values for d₃₃, d₃₁, C and dielectric constant were 1.06 pC/N, 0.74 pC/N, 6.0 pF and 76.1 respectively, at 70 % volume fraction of PZT. The surface topography and morphology were examined via AFM and SEM. The piezoelectric strain coefficients, capacitance and effective dielectric constant increased with increasing PZT content, in addition to the surface roughness. Agglomeration of PZT particles and surface crevices were observed on sample surfaces, which are most likely due to surface tension and air bubbles formed during the mixing process.     

Low dielectric dissipation and enhanced tunability of Ba0.6Sr0.4TiO3 thin films by the modified composition and multilayer structure

Ba_0.6Sr_0.4Ti_1+yO₃ (BST, y?=?0.1, 0.15, 0.2, 0.25, 0.3) thin films were fabricated on Pt-coated silicon substrates by modified sol-gel techniques. It was found that the tunability of BST thin films and dissipation factor decreased with the increase of Ti content. The multilayer structure of Ba_0.6Sr_0.4Ti_1+yO₃(200 nm)/Ba_0.6Sr_0.4TiO₃(100 nm)/Ba_0.6Sr_0.4Ti_1+yO₃ (200 nm; y?=?0.1, 0.2, 0.25) was designed to enhance the tunability. Our results indicated that the modified composition and multilayer structure were beneficial to lowering the dielectric dissipation and enhancing the tunability simultaneously. The tunability of 26.7% and dielectric dissipation of 0.013 were achieved for modified BST thin films.     

Fabrication and characterization of Au/SBT/LZO/Si MFIS structure

Ferroelectric SrBi₂Ta₂O₉ (SBT) films on a p-type Si (100) wafer with a LaZrO _x (LZO) buffer layer have been fabricated to form a metal-ferroelectric-insulator–semiconductor (MFIS) structure. The LZO thin film and SBT films were deposited by using a sol–gel method. The equivalent oxide thickness (EOT) value of the LZO thin film was about 8.83 nm. Also, the leakage current density of the LZO thin film is about 3.3?×?10^?5 A/cm² at bias sweeping voltage of ±5 V. SBT films were crystallized in polycrystalline phase with highly preferred (115) orientation. Also, the intensity of each pick slightly increased as thickness of SBT films increased. The C–V characteristics of Au/SBT/LZO/Si structure showed clockwise hysteresis loop. The memory window width increased as the thickness of SBT films increased. The leakage current density of Au/SBT/LZO/Si structure decreased as thickness of SBT films increased.     

Transport study of gate and channel engineering on the surrounding-gate CNTFETs based on NEGF quantum theory

In this paper, we comprehensively study the effects of gate and channel engineering on the performances of surrounding-gate CNTFETs using a quantum kinetic model, which is based on two-dimensional non-equilibrium Green functions (NEGF) solved self-consistently with Poisson’s equations. The iterative approach between Poisson equation and NEGF has been discussed. For the first time, the influences of double-material-gate and linear doping structures on the CNTFETs have been investigated. The calculated results show that double-material-gate CNTFETs with conventional doping (DMG-CNTFETs) can effectively suppress the drain-induced barrier lowering (DIBL), short-channel effects (SCEs), and achieve better sub-threshold property as compared with single-material-gate CNTFETs with conventional doping (SMG-CNTFETs). Compared with conventional doping, linear doping presents lower leakage current, higher I _on /I _off ratio, and lower sub-threshold swing, which means a better ability of gate controlling. In addition, we present a detailed discussion of the performances of scaling down, and conclude that DMG structure can meet the ITRS’10 requirements better than SMG, especially that the I _on /I _off ratio is two orders of magnitude higher than that of ITRS’10 requirements.     

Ferroelectric memory FET with Ir/IrO2 electrodes

Abstract

We proposed a MFMIS structure having a floating gate as a bottom electrode between a ferroelectric thin film and the gate SiO₂. Conventional gate SiO₂ can be used and ferroelectric thin films can be grown on bottom electrodes which have a good matching with the ferroelectric materials due to adopt the MFMIS structure. Ir and IrO₂ on poly-Si were used as floating gate. When a IrO₂ layer was formed between PZT and poly-Si, a high-quality PZT thin film was obtained and the PZT films show no fatigue up to 10¹² cycles of switching pulses. From the I_D-V_G characteristics measurement for 1·2 μm P-ch MFMIS FET, the shift in V_th or the memory window for a bias sweep of ±15V was about 3·3V. The difference of I_D-V_D curves which corresponded to I_D-V_G characteristics were found between before and after a programming pulse was applied.     

Fast-switching-speed,low-forward-voltage-drop static induction (SI) thyristor

A static induction (SI) thyristor using a normally-off planar-gate structure in a low power class has been developed to be used as a power switching device in a three-phase inverter circuit. A 600 V-15 A class SI thyristor with very fast switching time (tgt, tgq) and low forward voltage drop (V_TM) was designed and created. This design was performed with a reasonable wafer structure (n^?/n/p⁺), an n^? base carrier concentration and thickness, and a gate structure (gate diffusion length and gate-gate pitch). Microscopic processing was used to obtain this SI thyristor. The performance trade-off between turn-off time and forward voltage drop is controlled by a lifetime control process using proton irradiation that results in a very fast switching time with tgt of 500 ns and tgq of 500 ns with V_TM of 1.5 V (at I_T= 18 A). At a current level of I_T = 18 A, the current density in the active area becomes 200 A/cm², which indicates that the performance of the SI thyristor is superior to that of conventional IGBTs and MOSFETs.     

SrTiO3 Based Side Gate Field Effect Transistor Realized by Submicron Scale AFM Induced Local Chemical Reactions

In this work we will show how it is possible to apply the so called nano-oxidation technique to pattern electrical circuits on oxygen deficient SrTiO₃ (STO) thin films. We will focus on two aspects: the chemical reactions which are triggered at the surface of oxygen deficient STO thin films by the voltage biased tip of an atomic force microscope (AFM) and the exploitation of this phenomenology to pattern insulating regions on oxygen deficient STO thin films in the submicron regime. Due to the insulating nature of the AFM modified regions and to the possibility to remove selectively the modified parts, planar electrical circuits entirely designed over STO thin films can be fabricated. A prototype of planar side gate field effect thin film transistor in which STO acts both as active channel and as gate electrode is presented and discussed.     

Impact of high-k spacer on device performance of a junctionless transistor

The impact of spacer dielectric on both sides of gate oxide on the device performance of a symmetric double-gate junctionless transistor (DGJLT) is reported for the first time. The digital and analog performance parameters of the device considered in this study are drain current (I _D ), ON-state to OFF-state current ratio (I _ON /I _OFF ), subthreshold slope (SS), drain induced barrier lowering (DIBL), intrinsic gain (G _m R _O ), output conductance (G _D ), transconductance/drain current ratio (G _m /I _D ) and unity gain cut-off frequency (f _T ). The effects of varying the spacer dielectric constant (k _sp ) on the electrical characteristics of the device are studied. It is observed that the use of a high-k dielectric as a spacer brings an improvement in the OFF-state current by more than one order of magnitude thereby making the device more scalable. However, the ON-state current is only marginally affected by increasing dielectric constant of spacer. The effects of spacer width (W _sp ) on device performance are also studied. ON-state current marginally decreases with spacer width.     

Dual material gate junctionless tunnel field effect transistor

This paper proposes a junctionless tunnel field effect transistor (JLTFET) with dual material gate (DMG) structure and the performance was studied on the basis of energy band profile modulation. The two-dimensional simulation was carried out to show the effect of conduction band minima on the abruptness of transition between the ON and OFF states, which results in low subthreshold slope (SS). Appropriate selection of work function for source and drain side gate metal of a double metal gate JLTFET can also significantly reduce the subthreshold slope (SS), OFF state leakage and hence gives improved I _ON/I _OFF.     

Improvement of a GDC-based composite cathode for intermediate-temperature solid oxide fuel cells

La_0.84Sr_0.16MnO_3?δ - Ce_0.8Gd_0.2O_2-δ (LSM-GDC) composite cathodes were fabricated by impregnating the LSM matrix with both LSM′ (La_0.84Sr_0.16MnO_3?δ) and GDC (or only GDC), and the ion-impregnated LSM-GDC composite cathodes showed excellent performance. At 750 °C, the value of the cathode polarization resistance (R _p ) was only 0.058 Ω cm² for an ion-impregnated LSM-GDC composite cathode which was impregnated with both LSM′ and GDC. For the performance of the single cell with the same cathode, the maximum power density was 1.1 W cm^?2 at 750 °C. The long-term test of the cell was carried out at 700 °C with a constant load of 0.3 A cm^?2 and the output voltage was stable on the whole. The results demonstrated that LSM-GDC fabricated by impregnating the LSM matrix with both LSM′ and GDC was a promising composite cathode material for the intermediate-temperature solid oxide fuel cells.     

Characterization of defect density created by stress in the gate to?drain overlap region using GIDL current model in n-channel MOSFET

In this paper we study the impact of stress on gate induced drain leakage (GIDL) current variations in MOS transistors, which manifested by tunneling in the gate to drain overlap region. The oxide thickness of n-channel transistor used is 8.5?nm. We show that this phenomenon is accentuated in high stress accumulation V _g=?3?V, V _d=3?V, but more less for stress V _g=V _d=3?V. In both cases, any constraint corresponds to an increase in accumulated charges in the transistor and hence the current GIDL.     

ESD robustness improvement for integrated DMOS transistors —the different gate‐voltage dependence of It2 between VDMOS and LDMOS transistors

This paper presents the device‐level electrostatic discharge (ESD) robustness improvement for integrated vertical double‐diffused MOS (VDMOS) and lateral double‐diffused MOS (LDMOS) transistors by changing device structure. The ESD robustness of VDMOS transistor was improved by preventing current concentration and that of LDMOS transistor was improved by relaxing the electric field under the LOCOS oxide. We found the different gate‐voltage dependence of the second breakdown current (I_t2) between VDMOS and LDMOS transistors. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.