A 0.35-/spl mu/m CMOS 2-GHz VCO in wafer-level package

This letter presents a complementary metal oxide semiconductor (CMOS) voltage-controlled oscillator (VCO) with a high-Q inductor in a wafer-level package for the LC-resonator. The on-chip inductor is implemented using the redistribution metal layer of the wafer-level package (WLP), and therefore it is called a WLP inductor. Using the thick passivation and copper metallization, the WLP inductor has high quality-factor (Q-factor). A 2-nH inductor exhibits a Q-factor of 8 at 2 GHz. The center frequency of the VCO is 2.16 GHz with a tuning range of 385 MHz (18%). The minimum phase noise is measured to be -120.2 dBc/Hz at an offset frequency of 600 kHz. The dc power consumed by the VCO-core is 1.87 mW with a supply voltage of 1.7 V and a current of 1.1 mA. The output power with a 50-/spl Omega/ load is -12.5/spl plusmn/1.3 dBm throughout the whole tuning range. From the best of our knowledge, compared with recently published 2-GHz-band 0.35 /spl mu/m CMOS VCOs in the literature, the VCO in this work shows the lowest power consumption and the best figure-of-merit.     

High-Q factor three-dimensional inductors

In this paper, the great flexibility of three-dimensional (3-D) monolithic-microwave integrated-circuit technology is used to improve the performance of on-chip inductors. A novel topology for high-Q factor spiral inductor that can be implemented in a single or multilevel configuration is proposed. Several inductors were fabricated on either silicon substrate (/spl rho/ = 30 /spl Omega/ /spl middot/ cm) or semi-insulating gallium-arsenide substrate demonstrating, more particularly, for GaAs technology, the interest of the multilevel configuration. A 1.38-nH double-level 3-D inductor formed on an Si substrate exhibits a very high peak Q factor of 52.8 at 13.6 GHz and a self-resonant frequency as high as 24.7 GHz. Our 4.9-nH double-level GaAs 3-D inductor achieves a peak Q factor of 35.9 at 4.7 GHz and a self-resonant frequency of 8 GHz. For each technology, the performance limits of the proposed inductors in terms of quality factor are discussed. Guidelines for the optimum design of 3-D inductors are provided for Si and GaAs technologies.     

An ultralow-loss and broadband micromachined RF inductor for RFIC input-matching applications

In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Q/sub max/) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (f/sub SR/) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (G/sub Amax/) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08/spl times/10/sup -4/ dB) in minimum noise figure (NF/sub min/) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss G/sub Amax//spl les/0.99 (i.e., NF/sub min//spl les/0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.     

CMOS-compatible micromachined edge-suspended spiral inductors with high Q-factors and self-resonance frequencies

This paper reports a new category of high-Q edge-suspended inductors (ESI) that are fabricated using CMOS-compatible micromachining techniques. This structure was designed based on the concept that the current was crowded at the edges of the conducting metal wires at high frequencies due to the proximity effect. The substrate coupling and loss can be effectively suppressed by removing the silicon around and underneath the edges of the signal lines. Different from the conventional air-suspended inductors that have the inductors built on membranes or totally suspended in the air, the edge-suspended structures have the silicon underneath the center of the metal lines as the strong mechanical supports. The ESIs are fabricated using a combination of deep dry etching and anisotropic wet etching techniques that are compatible with CMOS process. For a three-turn 4.5-nH inductor, a 70% increase (from 6.8 to 11.7) in maximum Q-factor and a 57% increase (from 9.1 to 14.3 GHz) in self-resonance frequency were obtained with a 11-/spl mu/m suspended edge in 25-/spl mu/m-wide lines.     

Shielded passive devices for silicon-based monolithic microwave and millimeter-wave integrated circuits

This paper introduces floating shields for on-chip transmission lines, inductors, and transformers implemented in production silicon CMOS or BiCMOS technologies. The shield minimizes losses without requiring an explicit on-chip ground connection. Experimental measurements demonstrate Q-factor ranging from 25 to 35 between 15 and 40 GHz for shielded coplanar waveguide fabricated on 10 /spl Omega//spl middot/cm silicon. This is more than a factor of 2 improvement over conventional on-chip transmission lines (e.g., microstrip, CPW). A floating-shielded, differentially driven 7.4-nH inductor demonstrates a peak Q of 32, which is 35% higher than an unshielded example. Similar results are realizable for on-chip transformers. Floating-shielded bond-pads with 15% less parasitic capacitance and over 60% higher shunt equivalent resistance compared to conventional shielded bondpads are also described. Implementation of floating shields is compatible with current and projected design constraints for production deep-submicron silicon technologies without process modifications. Application examples of floating-shielded passives implemented in a 0.18-/spl mu/m SiGe-BiCMOS are presented, including a 21-26-GHz power amplifier with 23-dBm output at 20% PAE (at 22 GHz), and a 17-GHz WLAN image-reject receiver MMIC which dissipates less than 65 mW from a 2-V supply.     

High-Q Above-IC Inductors Using Thin-Film Wafer-Level Packaging Technology Demonstrated on 90-nm RF-CMOS 5-GHz VCO and 24-GHz LNA

High-Q inductors are important for the realization of high-performance, low-power RF-circuits. In this paper, on-chip inductors with Q-factors above 40 have been realized above the passivation of a 90-nm RF-CMOS process using wafer-level packaging (WLP) techniques . The influence of a patterned polysilicon and metal ground shield on the inductor-Q is compared and the influence of highly doped active area underneath the inductors is shown. A 5-15 GHz above-IC balun has been realized on 20 Omegamiddotcm silicon with the use of patterned ground shield. The technology is demonstrated by a low-power 90-nm RF-CMOS 5-GHz VCO with a core current consumption of only 150 muA with a 1.2-V supply, and a 10% tuning range with a worst case phase noise of -111 dBc/Hz at 1-MHz offset. A 24-GHz single-stage common-source low-noise amplifier has been realized, with a noise figure of 3.2 dB, a gain of 7.5 dB, and a low power consumption of 10.6 mW     

Q-factor definition and evaluation for spiral inductors fabricated using wafer-level CSP technology

A novel Q-factor definition and evaluation method are proposed for low-loss high-Q spiral inductors fabricated by using the wafer-level chip-size package (WLP) on silicon substrates, where the copper wiring technology with a polyimide isolation layer is used. In conventional Q-factor evaluation for inductors, a short-circuited load condition is used, where the Q factor is represented by using Y-parameters as Q=Im{1/Y/sub 11/}/Re{1/Y/sub 11/}. This conventional method provides a Q factor of 20 with 2-5-nH inductance around 3.9 GHz. However, since structures for the spiral inductors are asymmetrical, the short-circuited load condition and short-circuited source condition give different Q values, respectively. The Q-value differences of approximately 100% have often been observed in the WLP. The differences mainly come from differences in loss estimation. In a novel method, a complex conjugate impedance-matching condition is retained both at an input port and an output port of the inductor. The maximum available power gain (G/sub AMAX/) is introduced to evaluate the energy loss in one cycle. This condition provides a unique insertion loss of passive devices. Thus, the difference of the Q factor depends only on the difference of magnetic and electric energy. The difference of the Q value is reduced.     

High Q multilayer spiral inductor on silicon chip for 5/spl sim/6 GHz

High Q-values of spiral inductors at frequency around 5/spl sim/6 GHz have been achieved with a multilayer spiral (MLS) structure on a high loss silicon substrate. Compared to a one-layer spiral (OLS) inductor, the Q-value of a 4-nH inductor has been improved by about 80% at 5.65 GHz. The impact of the structure on Q-value and resonant frequency has been analyzed, which shows that an optimal height for the via of MLS inductors should be considered when inductors are designed. The fabrication process is compatible with Cu/SiO/sub 2/ interconnect technology.     

CMOS-compatible surface-micromachined suspended-spiral inductors for multi-GHz silicon RF ICs

Fully CMOS-compatible, highly suspended spiral inductors have been designed and fabricated on standard silicon substrates (1/spl sim/30 /spl Omega//spl middot/cm in resistivity) by surface micromachining technology (no substrate etch involved). The RF characteristics of the fabricated inductors have been measured and their equivalent circuit parameters have been extracted using a conventional lumped-element model. We have achieved a high peak Q-factor of 70 at 6 GHz with inductance of 1.38 nH (at 1 GHz) and a self-resonant frequency of over 20 GHz. To the best of our knowledge, this is the highest Q-factor ever reported on standard silicon substrates. This work has demonstrated that the proposed microelectromechanical systems (MEMS) inductors can be a viable technology option to meet the today's strong demands on high-Q on-chip inductors for multi-GHz silicon RF ICs.     

SOI technology for radio-frequency integrated-circuit applications

This paper presents a silicon-on-insulator (SOI) integration technology, including structures and processes of OFF-gate power nMOSFETs, conventional lightly doped drain (LDD) nMOSFETs, and spiral inductors for radio frequency integrated circuit (RFIC) applications. In order to improve the performance of these integrated devices, body contact under the source (to suppress floating-body effects) and salicide (to reduce series resistance) techniques were developed for transistors; additionally, locally thickened oxide (to suppress substrate coupling) and ultra-thick aluminum up to 6 /spl mu/m (to reduce spiral resistance) were also implemented for spiral inductors on high-resistivity SOI substrate. All these approaches are fully compatible with the conventional CMOS processes, demonstrating devices with excellent performance in this paper: 0.25-/spl mu/m gate-length offset-gate power nMOSFET with breakdown voltage (BV/sub DS/) /spl sim/ 22.0 V, cutoff frequency (f/sub T/)/spl sim/15.2 GHz, and maximal oscillation frequency (f/sub max/)/spl sim/8.7 GHz; 0.25-/spl mu/m gate-length LDD nMOSFET with saturation current (I/sub DS/)/spl sim/390 /spl mu/A//spl mu/m, saturation transconductance (g/sub m/)/spl sim/197 /spl mu/S//spl mu/m, cutoff frequency /spl sim/ 25.6 GHz, and maximal oscillation frequency /spl sim/ 31.4 GHz; 2/5/9/10-nH inductors with maximal quality factors (Q/sub max/) 16.3/13.1/8.95/8.59 and self-resonance frequencies (f/sub sr/) 17.2/17.7/6.5/5.8 GHz, respectively. These devices are potentially feasible for RFIC applications.     

30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

Silicon planar and three-dimensional inductors and transformers were designed and characterized on-wafer up to 100 GHz. Self-resonance frequencies (SRFs) beyond 100 GHz were obtained, demonstrating for the first time that spiral structures are suitable for applications such as 60-GHz wireless local area network and 77-GHz automotive RADAR. Minimizing area over substrate is critical to achieving high SRF. A stacked transformer is reported with S/sub 21/ of -2.5 dB at 50 GHz, and which offers improved performance and less area (30 /spl mu/m/spl times/30 /spl mu/m) than planar transformers or microstrip couplers. A compact inductor model is described, along with a methodology for extracting model parameters from simulated or measured y-parameters. Millimeter-wave SiGe BiCMOS mixer and voltage-controlled-oscillator circuits employing spiral inductors are presented with better or comparable performance to previously reported transmission-line-based circuits.     

Record Q symmetrical inductors for 10-GHz LC-VCOs in 0.18-/spl mu/m gate-length CMOS

We report a single-loop inductor suitable for integration in a differential voltage-controlled oscillator (LC-VCO) with 0.6-nH inductance and record quality factors of 18 at 10 GHz and 20 at 15 GHz fabricated in an industrial CMOS process on a 10 /spl Omega/cm substrate. A new lumped element model which accurately describes the inductor performance without the need for frequency-dependent elements is presented. During the course of this work, we found that a patterned ground shield significantly improves the inductor performance at these frequencies, but only when the polysilicon bars are connected from the center of the inductor.     

Selective metal parallel shunting inductor and its VCO application

The methodology to calculate the parasitic capacitances in differential symmetric inductors will be presented in this paper. Inspired by the proposed methodology, a method called selective metal parallel shunting (SMPS) can move f/sub Qmax/ onto the desired frequency without additional processing steps. Based on the proposed methodology, a customized program is developed to predict Q/sub max/s and f/sub Qmax/s of on-chip inductors. Differential symmetric inductors and spiral ones with planar, all metal parallel shunting (AMPS), and SMPS configurations have been implemented in a 1P4M 0.35-/spl mu/m CMOS process to verify the proposed method. Moreover, three 2.3-2.4 GHz voltage-controlled oscillators (VCOs) using planar, AMPS, and SMPS inductors, have also been realized. The phase noise of the VCO using SMPS inductors can be improved by 9.3 and 6 dB at 100-kHz offset frequency, respectively, compared to the VCOs using planar and AMPS inductors. The proposed SMPS technique can not only be applicable to VCO but also other RF circuits.     

Experimental analysis of the effect of metal thickness on the quality factor in integrated spiral inductors for RF ICs

The effect of metal thickness on the quality (Q-) factor of the integrated spiral inductor is investigated in this paper. The inductors with metal thicknesses of 5/spl sim/22.5 /spl mu/m were fabricated on the standard silicon substrate of 1/spl sim/30 /spl Omega//spl middot/cm in resistivity by using thick-metal surface micromachining technology. The fabricated inductors were measured at GHz ranges to extract their major parameters (Q-factor, inductance, and resistance). From the experimental analysis assisted by FEM simulation, we first reported that the metal thickness' effect on the Q-factor strongly depends on the innermost turn diameter of the spiral inductor, so that it is possible to improve Q-factors further by increasing the metal thickness beyond 10 /spl mu/m.     

Miniature and tunable filters using MEMS capacitors

Microelectromechanical system (MEMS) bridge capacitors have been used to design miniature and tunable bandpass filters at 18-22 GHz. Using coplanar waveguide transmission lines on a quartz substrate (/spl epsiv//sub r/ = 3.8, tan/spl delta/ = 0.0002), a miniature three-pole filter was developed with 8.6% bandwidth based on high-Q MEMS bridge capacitors. The miniature filter is approximately 3.5 times smaller than the standard filter with a midband insertion loss of 2.9 dB at 21.1 GHz. The MEMS bridges in this design can also be used as varactors to tune the passband. Such a tunable filter was made on a glass substrate (/spl epsiv//sub r/ = 4.6, tan/spl delta/ = 0.006). Over a tuning range of 14% from 18.6 to 21.4 GHz, the miniature tunable filter has a fractional bandwidth of 7.5 /spl plusmn/ 0.2% and a midband insertion loss of 3.85-4.15 dB. The IIP/sub 3/ of the miniature-tunable filter is measured at 32 dBm for the difference frequency of 50 kHz. The IIP/sub 3/ increases to >50 dBm for difference frequencies greater than 150 kHz. Simple mechanical simulation with a maximum dc and ac (ramp) tuning voltages of 50 V indicates that the filter can tune at a conservative rate of 150-300 MHz//spl mu/s.     

High-performance large-inductance embedded inductors in thin array plastic packaging (TAPP) for RF system-in-package applications

We report the first demonstration of high-Q embedded inductors fabricated using a thin-array-plastic-packaging (TAPP) technology. The TAPP technology provides a platform that integrates digital, analog, RF integrated circuits, along with high-performance passive components for system-in-package implementation. Embedded inductors ranging from 14 to 300 nH were fabricated. All the inductors with inductance less than 100 nH exhibit self-resonant frequency above 1 GHz. For a 14-nH inductor, Q factor of 35 was achieved at 1.6 GHz and the self-resonance frequency was measured at 6.15 GHz.     

A miniaturized Wilkinson power divider with CMOS active inductors

A miniaturized Wilkinson power divider implemented in a standard 0.18-/spl mu/m CMOS process is presented in this letter. By using active inductors for the circuit implementation, a significant area reduction can be achieved due to the absence of distributed components and spiral inductors. The power divider is designed at a center frequency of 4.5GHz for equal power dividing with all ports matched to 50/spl Omega/. Drawing a dc current of 9.3mA from a 1.8-V supply voltage, the fabricated circuit exhibits an insertion loss less than 0.16dB and a return loss better than 30dB at the center frequency while maintaining good isolation between the output ports. The active area of the miniaturized Wilkinson power divider is 150/spl times/100/spl mu/m/sup 2/, which is suitable for system integration in monolithic microwave integrated circuit (MMIC) applications.     

A regenerative comparator structure with integrated inductors

We employ on-chip inductors to improve the sampling speed and power consumption of regenerative comparators. Since these inductors are far smaller than those used in typical RF designs, the addition of inductors has little impact on area. Simulations based on accurate inductor models indicate more than a doubling of comparator sampling speed for a given power consumption, or a halving in power consumption for a given sampling speed. We present a detailed analysis of the new scheme. The technique is verified with test measurements of 16 comparators, implemented in 0.18-/spl mu/m digital CMOS, sampling at 3.84 GHz.     

High transmission gain integrated antenna on extremely high resistivity Si for ULSI wireless interconnect

We have demonstrated the highest transmission gain integrated dipole antenna on Si reported so far, to use as an integrated antenna for the purpose of ULSI on-chip wireless interconnection. A 2-mm long and 10-/spl mu/m wide dipole antenna pair at a distance of 1 cm shows a transmission gain of -36.5 dB at 18 GHz, which is 20 dB higher than the previously reported gain. This large increase in gain is achieved by proton implantation on the Si substrate, which increased the resistivity from 10 /spl Omega/-cm to 0.1 M/spl Omega/-cm. It is also found that transmission gain can be maximized for a given resistivity by optimizing the Si substrate thickness or by inserting a low-k dielectric layer below the substrate.     

Attenuation mechanisms of aluminum millimeter-wave coplanar waveguides on silicon

The loss mechanisms of silicon coplanar waveguides (CPW) with aluminum metallization are investigated up to 40 GHz. Three main parts contribute to the attenuation of coplanar waveguides (CPWs): the frequency-dependent conductor losses of the metallization, frequency-independent substrate losses, and the specifically investigated bias-dependent interface losses caused by free charges at the Si-SiO/sub 2/ interface. The minimum losses found in 50-/spl Omega/ CPWs with 45-/spl mu/m signal line width were 0.19 db/mm at 10 GHz and 0.33 dB/mm at 40 GHz. High-purity silicon from a float zone (FZ) process was used as substrate. Substrates with lower purity from a Czochralski (CZ) process (resistivity 50-100 /spl Omega/cm) resulted in somewhat higher (0.2-0.3 dB/mm) losses for the same CPW geometry.