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基于FPGA的高速椭圆曲线标量乘法结构 总被引:2,自引:0,他引:2
椭圆曲线密码系统是最近十几年来获得迅速发展的一类密码系统.为了提高椭圆曲线密码系统的处理速度,针对其中最关键的运算--椭圆曲线标量乘法设计并实现了一种基于FPGA的硬件结构,完成GF(2m)上的椭圆曲线标量乘法计算.该结构最大程度地对标量乘算法的内部模块进行了并行处理,缩短最大延迟路径,从而达到提高运算速度的目的.这一结构在FPGA上实现后,计算一次GF(2 163)上的椭圆曲线标量乘法只需要36μs,这一性能是目前国际上已知的基于FPGA的标量乘法器中最好的. 相似文献
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分析了GF(2~n)域上的椭圆曲线的运算法则,提出了一种串-并行结构的基于优化正规基(ONB)的高速有限域运算单元,比较了域划分D对芯片实现速度和硬件资源占用的影响,完成了域GF(2191)上基于ONB的ECC芯片快速实现。FPGA验证表明,GF(2191)域上一次点加运算需要183个时钟,一次点倍运算需要175个时钟,完成一次求乘法逆运算的总时钟数为133。在50MHz时钟下,完整的点乘运算速度平均为981次/s。 相似文献
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AES中有限域运算的优化及算法高速实现 总被引:1,自引:0,他引:1
介绍有限域的概念及Rijndael算法的结构,详细分析了算法中基于加法、乘法的运算过程,为使运算更适合在FP—GA平台实线,可使用一些技巧达到优化目的。详细阐述了使用FPGA高速实现运算关键部分的设汁思路。针对FPGA设计中对速度与面积两项指标的不同要求,给出了两种设计方案。最后,给出算法在FPGA实现方式下的性能比较。 相似文献
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基于DSP/FPGA的嵌入式实时目标跟踪系统 总被引:1,自引:1,他引:1
提出了一套基于DSP/FPGA的协处理器结构用以实现实时目标跟踪的嵌入式视觉系统。系统由DSP作为主处理器进行全局控制,利用具有流水线并行处理结构的FPGA作为协处理器实时完成DSP分配的处理任务。系统由FPGA快速完成最初的运动估计的结果,DSP在此基础上进一步分析和校正,并将校正信息反馈给FPGA,实现快速而准确的跟踪。 相似文献
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为了满足尺度不变特征变换(SIFT)算法临场处理大尺寸无人机(UAV)组网遥感观测影像的实时快速需求,提出一种基于数字信号处理器(DSP)内核的硬件乘法器来处理单精度浮点型像素数据乘法的算法实现方案。首先,根据DSP内核的硬件乘法器的数据输入、输出特性,重构SIFT算法的图像数据结构和图像函数,以实现硬件乘法器对SIFT算法单精度浮点型像素数据的乘法计算;其次,采用软件流水技术重新编排迭代计算,以增强算法的并行计算能力;最后,将在算法计算过程中产生的动态数据迁移至第三代双倍速率同步动态随机存储器(DDR3)中,以提升算法数据的存储空间。实验结果表明,DSP平台的SIFT算法可以实现对1 000×750的UAV遥感影像的高精度快速处理,所提方案满足无人机组网遥感影像临场处理对SIFT算法的实时快速要求。 相似文献
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Heiko Hinkelmann Peter Zipf Jia Li Guifang Liu Manfred Glesner 《Microprocessors and Microsystems》2009,33(1):2-12
Multiplication is a vital function for practically any DSP system. Some common DSP algorithms require different multiplication types, specifically integer or Galois Field (GF) multiplication. Since both functions share similarities in their structures, the potential is given for efficiently combining them in a single reconfigurable VLSI circuit, leading to competitive designs in terms of area, performance, and power consumption. This will be analysed and discussed in detail for 10 reconfigurable multiplier alternatives that are based on different strategies for the combination of integer and GF multiplication. Each result is compared to a reference architecture, showing area savings of up to 20% at a marginal increase in delay, and an increase in power consumption of 25% and above. This gives evidence that function-specific reconfigurable circuits can achieve considerable improvements in at least one design objective with only a moderate degradation in others. From this perspective, function-specific reconfigurable circuits can be considered feasible alternatives to standard ASIC solutions. 相似文献
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Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier. 相似文献
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提出了一种应用于椭圆曲线密码体制中的有限域乘法器结构,基于已有的digit-serial结构乘法器,利用局部并行的bit-parallel结构,有效地省去了模约简电路,使得乘法器适用于任意不可约多项式;通过使用数据接口控制输入数据的格式并内嵌大尺寸乘法器,可以配置有限域乘法器的结构,用以实现基于多项式基的有限域乘法运算。该结构可以有效满足椭圆曲线密码体制的不同安全需求。 相似文献
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Recently, cryptographic applications based on finite fields have attracted much attention. The most demanding finite field arithmetic operation is multiplication. This investigation proposes a new multiplication algorithm over GF(2^m) using the dual basis representation. Based on the proposed algorithm, a parallel-in parallel-out systolic multiplier is presented, The architecture is optimized in order to minimize the silicon covered area (transistor count). The experimental results reveal that the proposed bit-parallel multiplier saves about 65% space complexity and 33% time complexity as compared to the traditional multipliers for a general polynomial and dual basis of GF(2^m). 相似文献
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Wang CC Truong TK Shao HM Deutsch LJ Omura JK Reed IS 《IEEE transactions on computers. Institute of Electrical and Electronics Engineers》1985,(8):709-717
Finite field arithmetic logic is central in the implementation of Reed-Solomon coders and in some cryptographic algorithms. There is a need for good multiplication and inversion algorithms that can be easily realized on VLSI chips. Massey and Omura recently developed a new multiplication algorithm for Galois fields based on a normal basis representation. In this paper, a pipeline structure is developed to realize the Massey-Omura multiplier in the finite field GF(2m). With the simple squaring property of the normal basis representation used together with this multiplier, a pipeline architecture is developed for computing inverse elements in GF(2m). The designs developed for the Massey-Omura multiplier and the computation of inverse elements are regular, simple, expandable, and therefore, naturally suitable for VLSI implementation. 相似文献
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为了提高伽罗华有限域乘法器的通用性,降低实现的复杂度,采用自然基算法,用简单的逻辑门电路实现乘法运算过程。提出可重构的迭代计算结构,能满足域长m为3~8的乘法器,并用FPGA实现。结果表明,可重构有限域乘法器能够满足多种标准RS码的乘法运算的需要。 相似文献