微硅型光机电系统休成化技术中的金属布线

针对微硅型光机电系统集成化技术中电路和金属布线与硅微向向异性深腐蚀工艺之间的不相容问题、从寻求一种电路和金属布线保护层的思想出发，提出了用ＳｉＯ２／Ｃｒ复合膜电路和布线保护膜的新工艺方法。解决了微硅型光机电系统集成技术中长期存在的电路和布线中的关键技术。     

扭摆式微硅型加速度计

本文介绍了一种扭摆式微硅型加速度计的工作原理，制作方法和测试电路。     

高性能的频率合成器Q3036电路

Ｑ３０３６是美国Ｑｕａｌｃｏｍｍ公司推出的单片高性能频率合成器集成电路，工作电压为５Ｖ，工作频率从ＵＨＦ段到Ｌ波段，采用双层多晶硅层金属布线氧化物隔离硅双极工艺技术制作，广泛用于通讯，雷达，仪器仪表等领域。本文介绍了该电路的原理，主要电参数和性能特点。     

硅基多层布线集成组装技术

本文叙述了多芯片组件和多层布线集成组装技术的研究和进展，介绍了硅基多层布线集成组装技术的特点和设计考虑，扼要地叙述了硅基多层布线的制造工艺，并讨论了工艺中所出现的问题。     

厚膜多层电路的布线设计

<正> 前言以半导体芯片为主体的微组装技术使电路的集成度大大提高,并且使电路功能更为复杂与完善。厚膜多层电路是微组装技木中一种主要的电路形式,应用广泛。布线设计是多层电路试制与生产的关键工序,有必要研究实用的布线技术,加快试制和生产的进程,提高电路性能。本文主要从实用的观点     

低噪音放大器(LNA)多层板设计

介绍了低噪音放大器电路的多芯片技术设计与工艺分析.详细介绍了低噪音放大器多层布线版图以及每层的工艺实现步骤;通过对低噪音放大器电路的多层结构的设计与工艺实现,可以知道多层布线的发展是使电路小型化的一种途径,逐步提高电路的微型化的设计与制造的技术,最终实现电路微集成化的工作.     

硅基有机发光微显示像素驱动电路设计

由于微型显示像素面积的限制,硅基有机发光微显示像素驱动电路需要实现足够小的驱动电流.文章提出的三管电压控制型像素驱动电路与常规的采用电流镜电路的电流控制型像素驱动电路都能实现微显示所需的小电流驱动.利用Synopsys公司的H-spice软件对两种电路仿真比较,发现电流控制型电路具有线性灰度和较宽的有效灰度范围,但是通过调整电压控制型电路中与OLED并联的晶体管的宽长比,即可使其有效灰度范围与电流控制型电路可比.同时也发现电流控制型电路的功耗是电压控制型电路的4倍以上,且电路形式较复杂,工艺要求较高.所以三管电压控制型电路更适合于硅基有机发光微显示驱动电路.     

LCoS平板微显示驱动技术研究

研究了硅基液晶(LCoS)微显示驱动电路的制备工艺、电路设计、版图绘制以及显示功能测试.采用化学机械抛光(CMP)工艺实现硅片表面平坦化方案,满足了LCoS微显示对表面平整度的要求;合理布设两层金属布线,巧妙实现遮光作用;利用剥离的方法制备Ag反射电极,解决了Ag工艺与标准CMOS集成电路工艺的兼容问题;在硅基片上制作出U形PAD,通过导电胶与公共电极ITO相接.电路设计中采用了对台阶电平计数的办法实现DA转换的功能,既降低了电路设计难度,又方便测试过程中对灰度电平的调整.制备出LCoS微显示驱动面板,实现了QVGA分辨率、16级灰度LCoS、帧频50 HZ的视频显示.     

埋置型多层布线技术中的光刻工艺研究

埋置型薄膜多层布线与其它多层布线技术相比有更高的集成度。本文讨论了埋置型薄膜多层布线基板的制备在光刻工艺中的技术问题及解决措施。并成功地在埋置型双层混合电路中进行了应用。     

利用反向补偿原理控制硅CVD外延层中的金属杂质和微缺陷

本文分析了硅ＣＶＤ外延生长中金属杂质沾污、吸附－解吸机理模型和微缺分布规律，提出了用反向补偿原理优化外延工艺，有效地解决了硅外延层的金属杂质和微缺陷。     

A new air-isolation process for monolithic integrated circuits

A new air-isolation process is described which overcomes many of the problems of existing isolation technologies. The process consists of standard integrated circuit processing except for the p-n junction isolation process which is omitted. After metal mask, the device wafer is glass bonded face down to a supporting silicon wafer. Subsequent backlapping, masking, and mesa etching steps yield an air-isolated integrated circuit. As one application of this technology, the fabrication of a radiation-hardened operational amplifier is described.     

日立化成的弹性薄基板的最新发展（11）

日立化成开发了应用于超薄多层板的新基板，它是由超薄玻璃纤维与一种新低弹性模量热固性树脂体系组成，用相同树脂体系可以形成许多组合，包括板材（TC—c）、半固化片（TC—P）、涂树脂铜箔（TC—F）、粘接膜（TC—A）。通过使用这些组合，可能形成多种薄多层PCB的种类。特别是使用TC-C和TC—F能够容易地制造弯曲部分和多层部分成为一个整体，就不必使用覆盖层与粘接膜，进而可以制造更是薄的高密度PCB。此外，由于简化了线路加工，使得更薄而且可以弯曲的多层PCB具有更高的可靠性。     

The Electronic Circuit Composition and Structure of Thread for a Novel Braid Electronics-Systems by Kumihimo Structure

The new integrated circuit concept that forms electronic equipment by the textile structure using the flexible fiber has been proposed. In this report, we propose another integrated system-concept of flexible electronics based on "braid structure." The braid integrated system forms electronic equipment constructed by the filamentous body. Electronic integrated circuits are constructed with kumihimo-structure by weaving more than eight threads on which field effect transistors, photoelectric transducers, contact electrode pad and wiring pattern are mounted periodically. The circuit composition and a concrete structure of threads for kumihimo are discussed.     

Laser-patterned interconnect for thin-film hybrid wafer-scale circuits

High-performance electronic systems are often constrained by conventional packaging and interconnection technologies. A new technique is described for electrically connecting integrated circuit chips to a silicon wafer interconnection substrate, enabling future fabrication of hybrid wafer-scale circuits to be performed exclusively with thin-film interconnection technology. Thin-film wiring is fabricated down beveled edges of the chips and patterned using discretionary laser etching techniques. Interconnections on a 25-µm pitch (1600 wires around a 1-cm square chip) were achieved with this approach. Functioning hybrid memory modules have been fabricated to demonstrate feasibility of the technology.     

微波单片陶瓷电路技术研究

微波单片陶瓷电路(MMCC)是一项新兴的薄膜集成技术,是将构成微波电路的要素尽可能采用薄膜电路的实现方式集成于陶瓷基片上,并采用微细实心金属孔及空气桥、介质跨接等工艺实现接地、跨接和互联,可大大提高集成度,改善微波产品的性能.对该项技术进行了简要的介绍,并对主要的工艺技术如微小实心孔及金属化、集成电容技术、介质桥技术进行了重点阐述,同时应用MMCC技术设计和制作了微波鉴相电路,达到了预期效果.     

A 3-ns 1-kbit RAM using super self-aligned process technology

A high speed 1-kbit ECL RAM with a typical access time of 2.7 ns and power dissipation of 500 mW has been developed, using a novel LSI fabrication process technology, together with a new reference circuit configuration. This paper describes an integrated transistor structure using this novel process technology, fabrication steps, a new sense circuit and performance of the RAM.     

Chip-to-Chip Optical Link System Using an Optical Wiring Method

A practical optical link system was prepared with a transmitter (Tx) and receiver (Rx). The optical TRx module consisted of a metal optical bench, a module printed circuit board, a driver/receiver integrated circuit, a vertical-cavity surface-emitting laser/photodiode array, and an optical link block composed of plastic optical fiber (POF). For the optical interconnection between the light-sources and detectors, an optical wiring method has been proposed to enable easy assembly. The optical wiring link was constructed with POFs mounted on a v-grooved polymethylmethacrylate bench. The data transfer measurements were presented successfully.     

双π型RF EMIF的一种薄膜集成制造方法

基于双兀型电磁干扰滤波器(EMIF)的电路结构,借鉴了集成电路超微细加工技术,提出了与等平面超大规模集成电路工艺完全兼容的双兀型EMIF电路的薄膜集成制造方法.该方法可用于制作满足未来电子系统的高频化、小型化、轻型化和片式化信号处理EMIF电路的应用需求,改善双兀型EMIF电路的信号处理性能,还可将其与VLSI一起片上集成.     

新颖的常规硅工艺实现的侧向螺线型片上集成电感

提出了一种用常规硅工艺实现的片上集成电感的螺线型新结构．制造工艺使用标准双层金属布线的常规硅工艺．测量了螺线型集成电感的S参数，从测量数据计算了集成电感的参量．实验的侧向螺线型片上集成电感的Q值峰值为1.3，电感量为22nH．对用两层金属层实现的侧向螺线型片上集成电感和单层金属的常规平面螺旋电感的实验结果进行了比较，电感量和Q值与常规平面螺旋电感有可比性．     

Metal-ceramic constraints for multilayer electronic packages

Ceramic formulations set in an organic binder are currently being cast in thin paper-like sheets. These sheets may be punched, screened with metal pastes, and laminated to form a composite of metal and ceramic particles held together by an organic medium. By slowly burning off the organic binder and then sintering the ceramic and metal together, a substrate with many layers of interconnecting wiring may be obtained. The coincident sintering of the ceramic and metal phases presents compatibility constraints. Temperature considerations with respect to shrinkage and coefficient of expansion match between the ceramic and metal phases as well as solid/solid and solid/ambient interactions are important constraints in the fabrication of these composites. High conductivity metals (e.g., Ag, Cu) are generally not available for co-firing because sintering temperatures of important ceramic formulations are higher than the melting points of these metals. This constraint has been minimized through the use of capillary infiltration of molten metals into the ceramic structure. Consequently, it is now possible for multilayer ceramic structures to provide the interconnection wiring densities and conductivities necessary to respond to the needs of greater circuit densities of integrated circuit chips. Material selections are reviewed on the basis of electrical properties, ambient interactions, stresses due to sintering shrinkage, and thermal coefficient of expansion. Certain problems, tradeoffs, and procedures used in the fabrication of a multilayer substrate with Cu-filtrated lines are discussed.