一种新颖的微电子封装:圆片级封装

本文介绍了一种当前正在快速发展的微电子器件的新颖封装－圆片级封装（WLP）的定义，主要优缺点，焊盘再分布和植球等主要工艺过程等。     

圆片级封装技术展望

圆片级封装(Wafer-Level Packa-ging,WLP)已成为先进封装技术的重要部分。全圆片级封装虽然能够为芯片封装带来批量加工的规模经济效益,但由于系统集成方面的某些因素限制了其在主流应用中的推广。在圆片规模上开始加工,但结束于芯片规模的部分圆片级封装将在面型阵列倒装芯片的封装中得到日益广泛的应用。圆片级封装加工将成为业界前端和后端之间的高性能衔接桥梁。     

圆片级封装时代已经到来

所谓圆片级封装,是指封装和测试是在未分离的圆片上进行的,并且能在世界范围内被投入生产,主要是建立在薄膜凸点和再分布技术的基础上。采用这些技术的低引线数的硅器件和无源射频集成元件在今天的手持式电信产品中正在兴起。要使这项极具希望的技术获得很好的应用,圆片级老化和测试是必需的。     

圆片级封装散热问题

本文结合低功率和高功率应用中不同散热要求,对圆片级封装系统散热特性进行分析。     

技术评价:圆片级封装

本文对圆片级封装的定义、演变、进展状况及支撑技术进行了介绍和分析评论。     

现代圆片级封装技术的发展与应用

本文论述了圆片级封装的发展、优势、种类、应用、研究课题及产业化注意事项。     

圆片级封装技术——超CSPTM

文章论述了超CSPTM圆片级封装技术工艺。在封装制造技术方面此CSP封装技术的优越性在于其使用了标准的IC工艺技术。这不仅便于圆片级芯片测试和老炼筛选,而且在圆片制造末端嵌入是理想的。同时,文章也论述了超CSP封装技术的电热性能特征。     

封装技术的新潮流——圆片级封装

本文叙述了圆片级封装的概念、现状及发展方向。对超级CSP与MOST(Microspring on Silicon Technology)两种圆片级封装重点进行推介,并详细介绍了其典型工艺。     

再布线圆片级封装板级跌落可靠性研究

再布线圆片级封装通过对芯片焊区的重新构造以及无源元件的集成可以进一步提升封装密度、降低封装成本。再布线圆片级封装器件广泛应用于便携式设备中,在实际的装载、运输和使用过程中抗冲击可靠性受到高度重视。按照JEDEC标准对再布线圆片级封装样品进行了板级跌落试验,首先分析了器件在基板上不同组装点位的可靠性差异;然后依次探讨了不同节距和焊球尺寸、再布线结构对器件可靠性的影响;最后,对失效样品进行剖面制样,采用数字光学显微进行形貌表征。在此基础上,结合有限元分析对再布线结构和铜凸块结构的圆片级封装的可靠性和失效机理进行深入地阐释。     

用于圆片级封装的金凸点研制

介绍了电镀法进行圆片级封装中金凸点制作的工艺流程,并对影响凸点成型的主要工艺因素进行了研究.凸点下金属化层(UBM,under bump metallization)溅射、厚胶光刻和厚金电镀是其中的工艺难点,通过大量的实验研究,确定了TiW/Au的UBM体系,得到了优化的厚胶光刻工艺.同时,研制了用于圆片级封装金凸点制作的垂直喷镀设备,选用不同的电镀液体系和光刻胶体系,对电镀参数进行了控制和研究.对制作的金凸点与国外同类产品的基本特性进行了对比,表明其已经达到可应用水平.     

晶圆级封装的优化散热分析

通过有限元分析软件ANSYS,对一款晶圆级封装的产品进行有限元分析仿真,讨论了空气对流系数、环境温度、基板厚度、焊球间距等因素对芯片热阻的影响。结果表明:考虑成本、散热等综合因素,选择空气对流系数为25×10–6W/(mm·℃)基板厚度为0.10 mm、焊球间距为0.5 mm为最优参数,可满足实际生产需要。     

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

A wide range of requests coming from customer appears to demonstrate the feasibility of the TSV for a large range of via size and via AR either for process point of view or for performances point of view. The main application in the market is the CMOS image sensor with the integration of via at AR1. Now based on this first wafer level package of CMOS Image Sensor (CIS), the integration on the z axe will continue by the wafer lens integration for a continuous form factor and low cost module.First 3Di applications with TSV is entering the market with the via-last approach, more simply to be developed in semiconductor manufacturing in order to secure the 3Di technologies and to promote the 3Di to customers. Then specific design and electrical models will be developed and optimized allowing a fast and prosperous development of the via-first approach.A challenge in the modelisation of the TSV is the understanding of the mechanical impact of the trench and the metal filling on the behavior of the CMOS components and the reliability. These types of researches are progressing in various institutes and are essential for an increasing integration of TSV.Because actually, the technology continues to drive the 3D roadmap, the mechanical and thermal modelisation and 3D design tool need to be more activated to be developed faster in order to optimize the 3D module. Then the electrical testing will be a real challenge to be able to distinguish drift in the right strata, to be able to isolate a via within more than 10000 via in a module. The electrical testing will be strictly linked to mechanical and electrical failure analysis to get feed-back in technology, actual drawback of the 3D development.The cost of the 3Di and the TSV integration is more and more important and looks as a primary driver even if the functionalities increase faster than cost! Some steps have been already identified to be more costly steps: bonding and via filling. Indeed, throughput and material used have a direct impact on the final price.Continuous perspectives of TSV integration are progressing in order to optimise actual applications or to develop new integration. First challenging integration is the interposers with 3D interconnection allowing devices mounting on both side, like passive device integration or building of micro-cooling channels. The main interest of the 3D silicon interposer is the fact that it can connect chips at different locations and sizes, as example memory over digital IC. The usage of silicon as an interposer leads to an increase in the cost, but it will boost performances and reduce power consumption. One other advantage of the introduction of 3D interposer is the simplification of the required substrate implying a better mismatch of CTE lowering the packaging failure.In the wafer level package, TSV is now introduced to reduce the package footprint and mainly simplify the capping of device, similar to that for the MEMS. Indeed by integrating TSV, the capping must only protect the device against external environment, and not also take into account the electrical path in the bond layer degrading the hermiticity performance.To finish this paper, the sentence of Yann Guillou is the right situation: “The (3D) roadmaps need to be based on application requirements and not driven by technology ONLY. 3D Integration with TSV is not a scaling based concept Does it make sense today to think about submicron via diameter or dice thinner than 30 μm for example?” Applications need to take a risk by using 3D TSV technology!     

Interfacial reaction study on a solder joint with Sn-4Ag-0.5Cu solder ball and Sn-7Zn-Al (30 ppm) solder paste in a lead-free wafer level chip scale package

The interfacial reactions of solder joints between the Sn-4Ag-0.5Cu solder ball and the Sn-7Zn-Al (30 ppm) presoldered paste were investigated in a wafer level chip scale package (WLCSP). After appropriate surface mount technology (SMT) reflow process on the printed circuit board (PCB) with organic solderability preservative (Cu/OSP) and Cu/Ni/Au surface finish, samples were subjected to 150°C high-temperature storage (HTS), 1,000 h aging. Sequentially, the cross-sectional analysis is scrutinized using a scanning electron microscope (SEM)/energy-dispersive spectrometer (EDS) and energy probe microanalysis (EPMA) to observe the metallurgical evolution in the interface and solder buck itself. It was found that Zn-enriched intermetallic compounds (IMCs) without Sn were formed and migrated from the presolder paste region into the solder after reflow and 150°C HTS test.     

高可靠先进微系统封装技术综述

在人工智能、航空航天、国防武器装备电子系统小型化、模块化、智能化需求驱动下,系统级封装设计及关键工艺技术取得了革命性突破。新型的系统封装方法可把不同功能器件集成在一起,并实现了相互间高速通讯功能。封装工艺与晶圆制造工艺的全面融合,使封装可靠性、封装效率得到极大的提升,封装寄生效应得到有效抑制。文章概述了微系统封装结构及类型,阐述了高可靠晶圆级芯片封装(WLP)、倒装焊封装(BGA)、系统级封装(SIP)、三维叠层封装、TSV通孔结构的实现原理、关键工艺技术及发展趋势。     

Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.     

Application of Au-Sn eutectic bonding in hermetic radio-frequency microelectromechanical system wafer level packaging

Development of packaging is one of the critical issues toward realizing commercialization of radio-frequency-microelectromechanical system (RF-MEMS) devices. The RF-MEMS package should be designed to have small size, hermetic protection, good RF performance, and high reliability. In addition, packaging should be conducted at sufficiently low temperature. In this paper, a low-temperature hermetic wafer level packaging scheme for the RF-MEMS devices is presented. For hermetic sealing, Au-Sn eutectic bonding technology at temperatures below 300°C is used. Au-Sn multilayer metallization with a square loop of 70 μm in width is performed. The electrical feed-through is achieved by the vertical through-hole via filling with electroplated Cu. The size of the MEMS package is 1 mm × 1 mm × 700 μm. The shear strength and hermeticity of the package satisfies the requirements of MIL-STD-883F. Any organic gases or contamination are not observed inside the package. The total insertion loss for the packaging is 0.075 dB at 2 GHz. Furthermore, the robustness of the package is demonstrated by observing no performance degradation and physical damage of the package after several reliability tests.     

Wafer level hermetic packaging based on Cu-Sn isothermal solidification technology

A novel wafer level bonding method based on Cu-Sn isothermal solidification technology is established. A multi-layer sealing ring and the bonding processing are designed, and the amount of solder and the bonding parameters are optimized based on both theoretical and experimental results. Verification shows that oxidation of the solder layer, voids and the scalloped-edge appearance of the Cu6Sn5 phase are successfully avoided. An average shear strength of 19.5 MPa and an excellent leak rate of around 1.9 × 10-9 atm cc/s are possible, meeting the demands of MIL-STD-883E.     

大尺寸硅片背面磨削技术的应用与发展

集成电路芯片不断向高密度、高性能和轻薄短小方向发展，为满足IC封装要求，图形硅片的背面减薄成为半导体后半制程中的重要工序。随着大直径硅片的应用，硅片的厚度相应增大，而先进的封装技术则要求更薄的芯片，超精密磨削作为硅片背面减薄主要工艺得到广泛应用。本文分析了几种常用的硅片背面减薄技术，论述了的基于自旋转磨削法的硅片背面磨削的加工原理、工艺特点和关键技术，介绍了硅片背面磨削技术面临的挑战和取得的新进展。     

MEMS低温圆片级键合密封工艺研究

研究了一种使用非光敏苯并环丁烯(BCB)材料的低温硅片级键合,并将其用于压力谐振传感器封装.采用AP3000作为BCB中的黏结促进剂,将谐振片与硅片或Pyrex 7740玻璃晶圆键合,程序简单,低成本,密封性能较高,且键合温度低于250℃.通过拉伸实验,这种键合的剪切强度高于40 MPa.所以此硅片级键合适用于压力传感器的封装.