共查询到20条相似文献,搜索用时 31 毫秒
1.
2.
The dynamic partial reconfiguration technology of FPGA has made it possible to adapt system functionalities at run-time to changing environment conditions. However, this new dimension of dynamic hardware reconfigurability has rendered existing CAD tools and platforms incapable of efficiently exploring the design space. As a solution, we proposed a novel UML-based hardware/software co-design platform (UCoP) targeting at dynamically partially reconfigurable network security systems (DPRNSS). Computation-intensive network security functions, implemented as reconfigurable hardware functions, can be configured on-demand into a DPRNSS at run-time. Thus, UCoP not only supports dynamic adaptation to different environment conditions, but also increases hardware resource utilization. UCoP supports design space exploration for reconfigurable systems in three folds. Firstly, it provides reusable models of typical reconfigurable systems that can be customized according to user applications. Secondly, UCoP provides a partially reconfigurable hardware task template, using which users can focus on their hardware designs without going through the full partial reconfiguration flow. Thirdly, UCoP provides direct interactions between UML system models and real reconfigurable hardware modules, thus allowing accurate time measurements. Compared to the existing lower-bound and synthesis-based estimation methods, the accurate time measurements using UCoP at a high abstraction level can more efficiently reduce the system development efforts. 相似文献
3.
当前国内自动测试系统存在实时性差、测试资源冗余、成本高等问题,针对以上问题,提出了基于FPGA部分动态重构技术的自动测试系统,该系统基于FPGA动态可重构技术并结合嵌入式操作系统实现测试资源的动态管理,并开发了用于测试过程的硬件自动测试任务编程模型,提出了一种用于重构任务加载的ICAP控制器;该系统实现测试过程的并发执行,从而增强自动测试系统测试的实时性,进而提高测试的准确性与覆盖性。在验证试验中,将动态重构测试系统应用于自动测试实例中,试验结果表明硬件重构测试任务加载正常,各测试资源功能执行正确 相似文献
4.
《Real》2002,8(4):277-289
Field programmable gate array (FPGA) components are widely used nowdays to implement various algorithms, such as digital filtering, in real time. The emergence of dynamically reconfigurable FPGAs made it possible to reduce the number of necessary resources to carry out an image-processing task (tasks chain). In this article, an image-processing application, image rotation, that exploits the FPGAs dynamic reconfiguration method is presented. This paper shows that the choice of an implementation, static or dynamic reconfiguration, depends on the nature of the application. A comparison is carried out between the dynamic and the static reconfiguration using two criteria: cost and performance. It appears that, according to the nature of the application, the dynamic reconfiguration can be less or more advantageous. In order to be able to test the validity of our approach in terms of algorithm and architecture adequacy, we realized an AT40K40-based board “ARDOISE”. 相似文献
5.
Reconfigurable architectures are increasingly often applied in various industrial data processing applications, due to the possibility for performing parallel computations and achieving a simplified Systemon-Chip design flow. Furthermore, the exploitation of dynamic and partial hardware reconfiguration has been investigated in different research projects, often in systems based on Xilinx Virtex 2/4 FPGA families, by time-multiplexing hardware resources for multiple functions. This paper describes the exploitation of partial reconfiguration for dynamic power management in a low-power Spartan 3-based level measurement application. The reconfiguration process is thereby applied to optimize system implementation according to the applications requirements on power consumption and performance. 相似文献
6.
《Journal of Parallel and Distributed Computing》1994,22(2):268-278
Routing performance of optical interconnection networks is limited by both switch complexity and network connectivity. One way to overcome these limitations is to allocate the network bandwidth in a time-division multiplexed (TDM) fashion. With this technique, an appropriate subset of input-to-output connections can be established during a time slot and all possible connections can be established over several time slots. Emulating a fully connected network, however, requires a large multiplexing degree, and thus introduces latencies which may be prohibitive. As a solution, we propose a technique called reconfiguration with time-division multiplexing (RTDM). With RTDM, only a subset, as required by applications, of all possible connections needs to be multiplexed in the network by letting the network go through a sequence of configurations. Network reconfiguration with TDM can be done either statically or dynamically. Static RTDM is applied when communication requirements of an application are known a priori. This paper deals mainly with dynamic RTDM, which requires run time control to accommodate dynamic connection requests. We show that reconfiguration overhead can be amortized over a sequence of configurations. In particular, we describe how the complexity of a dynamic reconfiguration control algorithm can be reduced through pipelined processing of requests. Our simulations show that dynamic RTDM allows for fair and fast allocation of network resources to connection requests. As a result, network service time decreases and communication efficiency increases. 相似文献
7.
8.
近年来,随着可重构计算方法和可重构硬件特性的不断演进,基于FPGA动态部分重构技术构建运行时可重构加速器已经成为解决传统加速器设计中硬件资源限制问题的重要途径.然而,区别于传统静态重构加速器,FPGA的动态重构开销是影响硬件加速整体性能的重要因素,而目前尚缺少能够在可重构硬件设计的早期阶段进行动态重构开销精确估算的相关... 相似文献
9.
可重构资源管理及硬件任务布局的算法研究 总被引:1,自引:0,他引:1
可重构系统具有微处理器的灵活性和接近于ASIC的计算速度,可重构硬件的动态部分重构能力能够实现计算和重构操作的重叠,使系统能够动态地改变运行任务,可重构资源管理和硬件任务布局方法是提高可重构系统性能的关键.提出了基于任务上边界计算最大空闲矩形的算法(TT-KAMER),能够有效地管理系统的空闲可重构资源;在此基础上使用FF和启发式BF算法进行硬件任务的布局.实验表明,算法能够有效地实现在线资源分配与任务布局,获得较高的资源利用率. 相似文献
10.
Reconfigurable machines based on field programmable gate array (FPGA) chips adapt to applications’ needs through hardware
reconfiguration. Partial reconfiguration allows the configuration of a portion of a chip while the rest of the chip is busy
working on tasks. This paper considers a two-dimensional partially reconfigurable FPGA chip that allows the dynamic swap in
and out of circuit modules. Such a chip supports the concurrent execution of multiple applications or an application that
is otherwise too large to fit. A challenging issue for 2-D runtime partial reconfiguration is how to support the efficient
connection, or routing, between circuit modules or between modules and I/O pins, when those modules may be placed on any area
of a chip. Because commercial chips are not efficient in 2-D runtime routing, a new FPGA architecture is proposed based on
an array of clusters of configurable logic blocks and a mesh of segmented buses. To evaluate the runtime performance of the
architecture, an operating system is specified and implemented which takes care of the scheduling, placement, and routing
of circuits on the architecture. Simulation is used to evaluate the efficiency of the OS kernel and to determine the optimal
cluster size of the architecture. 相似文献
11.
12.
13.
《Journal of Parallel and Distributed Computing》1994,23(2):177-189
In this paper we consider the partial multinode broadcast and the partial exchange communication tasks in d-dimensional meshes. The partial multinode broadcast in an N-processor network is the task in which each of M ≤ N arbitrary nodes broadcasts a packet to all the remaining N − 1 nodes. Correspondingly, in the partial exchange there are M ≤ N nodes that wish to send a separate, personalized packet to each of the other nodes. We propose algorithms for the d-dimensional mesh network that execute the partial multinode broadcast and the partial exchange communication tasks in near-optimal time. No assumption is made concerning the locations of the M source nodes. The communication algorithms proposed are "on line" and distributed. We further look at a dynamic version of the broadcasting problem, where broadcast requests are generated at random times. In particular, we assume that the broadcast requests are generated at each node of the mesh according to a Poisson distribution with rate λ. Based on the partial multinode broadcast algorithm, we propose a dynamic decentralized scheme to execute the broadcasts in this dynamic environment. We find an upper bound on the average delay required to serve each broadcast. We prove that the algorithm is stable for network utilization ρ close to 1, and the average delay is of the order of the diameter for any load in the stability region. 相似文献
14.
With technology progress, more and more applications are integrated into a single chip. This requires a large number of processing elements (PEs) in a system, such that computation can be effectively enhanced through parallel processing. To support more efficient parallel processing, the Network-on-Chip (NoC) is being increasingly adopted as an interconnection architecture. Nevertheless, for NoC-based reconfigurable systems, the issue of mapping tasks to the PEs becomes more complex, due to the characteristic of hardware reconfiguration. This work proposes a novel Elastic Superposition Mapping (ESM) that introduces a useful PE reservation heuristic along with dynamic cross-application superposition. The ESM can provide a great elasticity for an NoC-based reconfigurable system to map more applications. Thus, the task load on PE will increase. Experiments show that, compared to the state-of-the-art mapping methods, 7% to 49% more applications can be executed, the average task load on PE can be increased by 5.5% to 56%, and the application waiting time can be reduced by 11% to 54%. 相似文献
15.
Radha Guha Author Vitae Nader Bagherzadeh Author Vitae Author Vitae 《Computers & Electrical Engineering》2009,35(2):258-285
There are many design challenges in the hardware-software co-design approach for performance improvement of data-intensive streaming applications with a general-purpose microprocessor and a hardware accelerator. These design challenges are mainly to prevent hardware area fragmentation to increase resource utilization, to reduce hardware reconfiguration cost and to partition and schedule the tasks between the microprocessor and the hardware accelerator efficiently for performance improvement and power savings of the applications.In this paper a modular and block based hardware configuration architecture named memory-aware run-time reconfigurable embedded system (MARTRES) is proposed for efficient resource management and performance improvement of streaming applications. Subsequently we design a task placement algorithm named hierarchical best fit ascending (HBFA) algorithm to prove that MARTRES configuration architecture is very efficient in increased resource utilization and flexible in task mapping and power savings. The time complexity of HBFA algorithm is reduced to O(n) compared to traditional Best Fit (BF) algorithm’s time complexity of O(n2), when the quality of the placement solution by HBFA is better than that of BF algorithm. Finally we design an efficient task partitioning and scheduling algorithm named balanced partitioned and placement-aware partitioning and scheduling algorithm (BPASA). In BPASA we exploit the temporal parallelism in streaming applications to reduce reconfiguration cost of the hardware, while keeping in mind the required throughput of the output data. We balance the exploitation of spatial parallelism and temporal parallelism in streaming applications by considering the reconfiguration cost vs. the data transfer cost. The scheduler refers to the HBFA placement algorithm to check whether contiguous area on FPGA is available before scheduling the task for HW or for SW. 相似文献
16.
Duato J. Lysne O. Pang R. Pinkston T.M. 《Parallel and Distributed Systems, IEEE Transactions on》2005,16(5):412-427
This paper develops theoretical support useful for determining deadlock properties of dynamic network reconfiguration techniques and also serves as a basis for the development of design methodologies useful for deriving deadlock-free reconfiguration techniques. It is applicable to interconnection networks typically used in multiprocessor servers, network-based computing clusters, and distributed storage systems, and also has potential application to system-on-chip networks. This theory builds on basic principles established by previous theories while pioneering new concepts fundamental to the case of dynamic network reconfiguration. 相似文献
17.
《Journal of Systems Architecture》2000,46(10):951-954
We present an algorithm for dynamic reconfiguration from a set of processor nodes connected using a multistage interconnection network into a set of m-ary trees of height h. The algorithm allows parameterization based on the branching factor m, the height of the tree h and bias B and produces a set of isomorphic trees for each value of the bias B. The computation of the identities of the neighbors by the nodes is performed using simple binary operations in parallel. 相似文献
18.
19.
As a hotspot of machine learning research, deep learning is applied in many fields. Embedded systems are becoming more and more complex and networked, so the real-time performance of embedded systems and the security of network embedded devices face severe challenges. Based on this, this paper studies the real-time task scheduling problem for complex embedded systems and the security of embedded network devices. For real-time, this paper proposes a comprehensive task scheduling algorithm. Based on the task classification in the embedded system, different scheduling methods are adopted for different tasks, and the scheduling mode is flexibly changed as the system load changes. A dynamic integrity measurement model is established based on the star trust chain structure, and the hardware implementation mechanism of constructing dynamic trust chain in embedded system is studied. The dynamic reconfigurable hardware design method based on FPGA is applied to the construction of dynamic trust chain, and a verification system is designed to verify the dynamic measurement mechanism. This can solve the security problem of deep network embedded devices to a certain extent. 相似文献