Model-based mapping of reconfigurable image registration on FPGA platforms

Image registration is a computationally intensive application in the medical imaging domain that places stringent requirements on performance and memory management efficiency. This paper develops techniques for mapping rigid image registration applications onto configurable hardware under real-time performance constraints. Building on the framework of homogeneous parameterized dataflow, which provides an effective formal model of design and analysis of hardware and software for signal processing applications, we develop novel methods for representing and exploring the hardware design space when mapping image registration algorithms onto configurable hardware. Our techniques result in an efficient framework for trading off performance and configurable hardware resource usage based on the constraints of a given application. Based on trends that we have observed when applying these techniques, we also present a novel architecture that enables dynamically-reconfigurable image registration. This proposed architecture has the ability to tune its parallel processing structure adaptively based on relevant characteristics of the input images.

Parallel microprogramming tools for a horizontally reconfigurable architecture

Software systems that allow the user to effectively exploit parallelism in an architecture are rare. This is a report on three software development tools designed for the DRAFT horizontally reconfigurable architecture machine: reconfiguring microassembler, a debug simulator, and an operating environment. In all of these tools a high priority has been placed on ease of use and minimization of the programmer's responsibility for management of parallelism. At the time of this writing, the first two of these tools have been implemented and are currently in use. The operating environment, like the prototype machine, is in the final stages of construction.Research supported in part by the National Science Foundation and the National Security Agency under grants NSF DCR 83-115-80 and NSA MDA 904-85-H-0006.     

ReKonf: Dynamically reconfigurable multiCore architecture

The increased transistor count resulting from ever-decreasing feature sizes has enabled the design of architectures containing many small but efficient processing units (cores). At the same time, many new applications have evolved with varying performance requirements. The fixed architecture of multiCore platforms often fails to accommodate the inherent diverse requirements of different applications. We present a dynamically reconfigurable multiCore architecture that detects program phase change at runtime and adapts to the changing program behavior by reconfiguring itself. We introduce simple but efficient performance counters to monitor vital parameters of reconfigurable architectures. We also present static, dynamic and adaptive reconfiguration techniques for reconfiguring the architecture. Our evaluation of the proposed reconfigurable architecture using an adaptive reconfiguration technique shows an improvement of up to 23% for multi-threaded applications and up to 27% for multiprogrammed workloads over that on statically chosen architectures, and up to 41% over the baseline SMP configuration.     

Design of a reconfigurable pseudorandom number generator for use in intelligent systems

This paper deals with the design of a network-on-chip reconfigurable pseudorandom number generation unit that can map and execute meta-heuristic algorithms in hardware. The unit can be configured to implement one of the following five linear generator algorithms: a multiplicative congruential, a mixed congruential, a standard multiple recursive, a mixed multiple recursive, and a multiply-with-carry. The generation unit can be used both as a pseudorandom and a message passing-based server, which is able to produce pseudorandom numbers on demand, sending them to the network-on-chip blocks that originate the service request. The generator architecture has been mapped to a field programmable gate array, and showed that millions of numbers in 32-, 64-, 96-, or 128-bit formats can be produced in tens of milliseconds.     

基于观测器的可重构机械臂分散自适应模糊控制

提出一种基于观测器的可重构机械臂分散自适应模糊控制方案.将可重构机械臂的动力学描述为一个交联子系统的集合,子系统控制器由自适应模糊系统和鲁棒控制项组成.基于状态观测器观测值构建的自适应模糊系统用于逼近子系统动力学模型和交联项,鲁棒控制项用于抵消模糊逼近误差对轨迹跟踪的影响.数值仿真证明了所提出的分散控制方案的有效性.     

Parallel stereocorrelation on a reconfigurable multi-ring network

A reconfigurable network termed as the reconfigurable multi-ring network (RMRN) is described. The RMRN is shown to be a truly scalable network in that each node in the network has a fixed degree of connectivity and the reconfiguration mechanism ensures a network diameter of O(log₂ N) for anN-processor network. Algorithms for the two-dimensional mesh and the SIMD or SPMD n-cube are shown to map very elegantly onto the RMRN. Basic message passing and reconfiguration primitives for the SIMD/SPMD RMRN are designed for use as building blocks for more complex parallel algorithms. The RMRN is shown to be a viable architecture for image processing and computer vision problems using the parallel computation of the stereocorrelation imaging operation as an example. Stereocorrelation is one of the most computationally intensive imaging tasks. It is used as a visualization tool in many applications, including remote sensing, geographic information systems and robot vision.An earlier version of this paper was presented at the 1995 International Conference on Parallel and Distributed Processing Techniques and Applications.     

从IRAM计算机结构看计算机体系结构发展的新特点

处理器与存储器之间的带宽差距越来越大,存储器带宽已经严重限制了计算机性能的有效提高。Ｃａｌｉｆｏｒｎｉａ大学贩ＩＲＡＭ（Ｉｎｔｅｌｌｉｇｅｎｔ ＲＡＭ）计算机系统结构在单个ＤＲＡＭ芯片中集成一定逻辑功能,能有效解决这一问题,代表了体系结构研究的一个新方向。     

计算机体系结构的新发展：通用重构计算技术

重构计算技术在众多的专用应用领域具有通用计算机技术所无法比拟的性能。现在，通过将通用计算机与重构计算硬件结合，可以进行有效的通用重构计算。     

Real-time human action recognition on an embedded, reconfigurable video processing architecture

In recent years, automatic human action recognition has been widely researched within the computer vision and image processing communities. Here we propose a real-time, embedded vision solution for human action recognition, implemented on an FPGA-based ubiquitous device. There are three main contributions in this paper. Firstly, we have developed a fast human action recognition system with simple motion features and a linear support vector machine classifier. The method has been tested on a large, public human action dataset and achieved competitive performance for the temporal template class of approaches, which include “Motion History Image” based techniques. Secondly, we have developed a reconfigurable, FPGA based video processing architecture. One advantage of this architecture is that the system processing performance can be reconfigured for a particular application, with the addition of new or replicated processing cores. Finally, we have successfully implemented a human action recognition system on this reconfigurable architecture. With a small number of human actions (hand gestures), this stand-alone system is operating reliably at 12 frames/s, with an 80% average recognition rate using limited training data. This type of system has applications in security systems, man–machine communications and intelligent environments.

A process-driven computing model for reconfigurable semiconductor manufacturing

Reconfigurability is essential for semiconductor manufacturing systems to remain competitive. Reconfigurable systems avoid costly modifications required to change and adapt to changes in product, production and services. A fully automated, collaborative, and integrated while reconfigurable manufacturing system proves cost-effective in the long term and is a promising strategy for the semiconductor manufacturing industry. However, there is a lack of computing models to facilitate the design and development of control and management systems in a truly reconfigurable manner. This paper presents an innovative computing model for reconfigurable systems and controlled manufacturing processes while allowing for the integration of modern technologies to facilitate reconfiguration, such as radio frequency identification (RFID) and reconfigurable field programmable gate array (FPGA). Shop floor manufacturing activities are modeled as processes from a business perspective. A process-driven formal method that builds on prior research on virtual production lines is proposed for the formation of a reconfigurable cross-facility manufacturing system. The trajectory of the controlled manufacturing systems is optimized for on-demand production services. Reconfigurable process controllers are introduced in support of the essential system reconfigurability of future semiconductor manufacturing systems. Implementation of this approach is also presented.     

A reconfigurable architecture for autonomous visual-navigation

Abstract. This paper describes the design of a reconfigurable architecture for implementing image processing algorithms. This architecture is a pipeline of small identical processing elements that contain a programmable logic device (FPGA) and double port memories. This processing system has been adapted to accelerate the computation of differential algorithms. The log-polar vision selectively reduces the amount of data to be processed and simplifies several vision algorithms, making possible their implementation using few hardware resources. The reconfigurable architecture design has been devoted to implementation, and has been employed in an autonomous platform, which has power consumption, size and weight restrictions. Two different vision algorithms have been implemented in the reconfigurable pipeline, for which some experimental results are shown. Received: 30 March 2001 / Accepted: 11 February 2002 RID="*" ID="*" This work has been supported by the Ministerio de Ciencia y Tecnología and FEDER under project TIC2001-3546 Correspondence to: J.A. Boluda     

A novel methodology to measure the responsiveness of RMTs in reconfigurable manufacturing system

Reconfigurable manufacturing systems are designed to deliver exact functionality and capacity that is needed, when it is needed. The reconfigurable machine tool (RMT) plays a pivotal role in the accomplishment of this objective through their built in modular structure consisting of basic and auxiliary modules along with the open architecture software.     

SOA in reconfigurable supply chains: A research roadmap

Originally coming from the business world, service-oriented architecture (SOA) paradigm is expanding its range of application into several different environments. Industrial automation is increasingly interested on adopting it as a unifying approach with several advantages over traditional automation. In particular, the paradigm is well indicated to support agile and reconfigurable supply chains due to its dynamic nature. In this domain, the main goals are short time-to-market, fast application (re)configurability, more intelligent devices with lifecycle support, technology openness, seamless IT integration, etc. The current research challenges associated to the application of SOA into reconfigurable supply chains are enumerated and detailed with the aim of providing a roadmap into a major adoption of SOA to support agile reconfigurable supply chains.     

A virtual prototyping system with reconfigurable actuators for multi-material layered manufacturing

Proliferation of layered manufacturing (LM) in various sectors has been calling for fabrication of large, complex products with more materials and efficiency. We address this issue by integrating reconfigurable manufacturing (RM) with LM. This paper first analyses the benefits of such integration, and then presents a virtual prototyping system with reconfigurable actuators (VPRA) that can increase the number of materials, speed, and build volume to improve the efficiency and flexibility of multi-material layered manufacturing (MMLM). The VPRA system offers a test bed for design, visualization, and validation of MMLM facilities and processes. It takes advantage of the convenient graphics platform of SolidWorks™ for constructing a virtual MMLM facility by selecting reconfigurable actuators from predefined templates. The characteristics, including the dimensions and relative spatial constraints, of the actuators can be conveniently configured to suit design requirements. The mechanism and the operation process of the resulting MMLM facility can then be simulated and validated through digital fabrication of complex objects. Case studies are presented to demonstrate some possible applications of the VPRA system. Overall, the VPRA system gives insights into the characteristics of a reconfigurable MMLM system, which can be subsequently materialized for physical fabrication of multi-material objects. This approach highlights a possible direction for development of MMLM technology.     

Automatic folding of cartons using a reconfigurable robotic system

This paper proposes new theories and methodology for the study of folding carton and reconfigurable packaging systems and presents both virtual and experimental systems to support the theories. Equivalent mechanisms of cartons were established by describing carton creases as joints and carton panels as links. With the analysis of the equivalent mechanism, the gusset vertexes of cartons were analyzed based on their equivalent spherical linkages and were identified as guiding linkages that determine folding. A reconfigurable robotic system was developed to demonstrate the ability to erect diverted cartons in the reconfigurable packaging system which could previously only be achieved manually.     

基于多Agent的可重构制造系统集成模型

应用控制、管理和维护一体化的自动化技术,建立了基于多Agent的可重构制造系统RMS（Reconfigurable Manufacturing System）集成模型。该模型集成了基于多Agent 的RMS重构模型、控制模型和故障诊断模型,将RMS的控制、管理和维护联系起来,并给出了该模型的UML（Unified Modeling Langurage）活动图,最后举例验证了模型的可行性。     

A reconfigurable VLSI-based double-lens tracking camera

Watching and tracking an object while seeing a much wider view is one of advantages of the eye system. We proposed and developed a tracking camera system that mimics the eyes by using double-lens modules. In the system, a wide view is captured through the wide-lens module, while the target in it is tracked and magnified through the telescopic lens module. Electronic circuits for tracking control are implemented onto the reconfigurable VLSI or FPGA in order to embed the parallelism in the tracking algorithm into the hardware. A successfully developed FPGA-based prototype performs high-speed tracking at the video-rate. This work was present in part at the 12th International Symposium on Artificial Life and Robotics, Oita, Japan, January 25–27, 2007     

Dynamically reconfigurable hardware-software architecture for partitioning networking functions on the SoC platform

We present an issue of the dynamically reconfigurable hardware-software architecture which allows for partitioning networking functions on a SoC (System on Chip) platform. We address this issue as a partition problem of implementing network protocol functions into dynamically reconfigurable hardware and software modules. Such a partitioning technique can improve the co-design productivity of hardware and software modules. Practically, the proposed partitioning technique, which is called the ITC (Inter-Task Communication) technique incorporating the RT-IJC² (Real-Time Inter-Job Communication Channel), makes it possible to resolve the issue of partitioning networking functions into hardware and software modules on the SoC platform. Additionally, the proposed partitioning technique can support the modularity and reuse of complex network protocol functions, enabling a higher level of abstraction of future network protocol specifications onto the SoC platform. Especially, the RT-IJC² allows for more complex data transfers between hardware and software tasks as well as provides real-time data processing simultaneously for given application-specific real-time requirements. We conduct a variety of experiments to illustrate the application and efficiency of the proposed technique after implementing it on a commercial SoC platform based on the Altera’s Excalibur including the ARM922T core and up to 1 million gates of programmable logic.     

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

To meet both flexibility and performance requirements, particularly when implementing high-end real-time image/video processing algorithms, the paper proposes to combine the application specific instruction-set processor (ASIP) paradigm with the reconfigurable hardware one. As case studies, the design of partially reconfigurable ASIP (r-ASIP) architectures is presented for two classes of algorithms with widespread diffusion in image/video processing: motion estimation and retinex filtering. Design optimizations are addressed at both algorithmic and architectural levels. Special processor concepts used to trade-off performance versus flexibility and to enable new features of post-fabrication configurability are shown. Silicon implementation results are compared to known ASIC, DSP or reconfigurable designs; the proposed r-ASIPs stand for their better performance–flexibility figures in the respective algorithmic class.

A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

We address routing in Networks-On-Chip (NoC) architectures that use irregular mesh topologies with Long-Range Links (LRL). These topologies create difficult conditions for routing algorithms, as standard algorithms assume a static, regular link structure and exploit the uniformity of regular meshes to avoid deadlock and maintain routability. We present a novel routing algorithm that can cope with these irregular topologies and adapt to run-time LRL insertion and topology reconfiguration. Our approach to accommodate dynamic topology reconfiguration is to use a new technique that decomposes routing relations into two stages: the calculation of output ports on the current minimal path and the application of routing restrictions designed to prevent deadlock. In addition, we present a selection function that uses local topology data to adaptively select optimal paths.The routing algorithm is shown to be deadlock-free, after which an analysis of all possible routing decisions in the region of an LRL is carried out. We show that the routing algorithm minimises the cost of sub-optimally placed LRL and display the hop savings available. When applied to LRLs of less than seven hops, the overall traffic hop count and associated routing energy cost is reduced. In a simulated 8 × 8 network the total input buffer usage across the network was reduced by 6.5%.