Raman spectroscopic study of In2S3 films prepared by spray pyrolysis

Indium sulfide (In₂S₃) thin films are of interest as buffer layers in chalcopyrite absorber based solar cells; and as media providing two-photon absorption for intermediate-band solar cells. We investigated the suitability of chemical spray pyrolysis (CSP) for growing In₂S₃ thin films in a structural order where indium atoms are preferentially in the octahedral sites. We sprayed aqueous or alcoholic solutions of indium chloride (InCl₃) and thiourea (SC(NH₂)₂) precursors onto a substrate with surface temperatures (T_S) of 205, 230, 275 and 320 °C. The as-deposited films grown from aqueous solutions were annealed in 5% H₂S containing atmosphere at 500 °C. We used Raman spectroscopy, X-ray diffraction and Energy Dispersive X-ray spectroscopy to evaluate the effect of growth temperature and the effect of annealing on the film structure and stoichiometry. The use of alcoholic solvent instead of aqueous allows us to use much lower T_S while preserving the quality of the β-In₂S₃ films obtained. Similarly, films with increased stoichiometry and quality are present at a higher T_S; and when annealed. The annealing of the films grown at T_S of 205 °C results in a much higher gain of the crystal quality compared to the gain when annealing the films grown at T_S of 320 °C, although the quality remain higher when deposited at T_S of 320 °C. Simultaneously with the increase of the film quality, there is a sign of increased quality of the crystal ordering with indium in the octahedral sites. Such a crystal ordering favor the use of CSP deposited In₂S₃ films in the intermediate band solar cells.     

Infrared spectroscopy of bonded silicon wafers

Infrared spectra of multiple frustrated total internal reflection and transmission for silicon wafers obtained by direct bonding in a wide temperature range (200–1100°C) are studied. Properties of the silicon oxide layer buried at the interface are investigated in relation to the annealing temperature. It is shown that the thickness of the SiO₂ layer increases from 4.5 to 6.0 nm as the annealing temperature is increased. An analysis of the optical-phonon frequencies showed that stresses in the SiO₂ relax as the annealing temperature is increased. A variation in the character of chemical bonds at the interface between silicon wafers bonded at a relatively low temperature (20–400°C) is studied in relation to the chemical treatment of the wafers’ surface prior to bonding. Models of the process of low-temperature bonding after various treatments for chemical activation of the surface are suggested.     

Effect of the tin content on the composition and optical and electrical properties of ITO films deposited onto silicon and glass by ultrasonic spray pyrolysis

With the aim of optimizing the properties of tin-doped indium oxide (ITO) films as applied to silicon solar cells, ??100-nm-thick ITO films were deposited onto (nn ⁺)-Cz-Si and glass substrates by ultrasonic spray pyrolysis in argon at a temperature of 380°C. The relative Sn and In content in the film-forming solution was varied in the range of [Sn]/[In] = 0?C12 at %. Optimal parameters are exhibited by the films produced at [Sn]/[In] = 2?C3 at % in the solution ([Sn]/([In] + [Sn]) = 5.2?C5.3 at % in the film). For such films deposited onto glass substrates, the effective absorptance weighted over the solar spectrum in the wavelength range from 300 to 1100 nm is 1.6?C2.1%. The sheet resistance R _s of the films deposited onto silicon and glass is, correspondingly, 45?C55 and 165?C175 ???^?1. After eight months of storage in air, the resistance R _s of the optimal films remained unchanged; for the other films, the resistance R _s increased: for the films on silicon and glass, the resistance R _s became up to 2 and 14 times higher, respectively.     

Effect of substrate temperature on indium tin oxide (ITO) thin films deposited by jet nebulizer spray pyrolysis and solar cell application

This study focused on the effect of substrate temperature (350 °C, 400 °C, and 450 °C) on morphological, optical, and electrical properties of indium tin oxide (ITO) films deposited onto porous silicon/sodalime glass substrates through jet nebulizer spray pyrolysis for use in heterojunction solar cells. X-ray diffraction analysis confirmed the formation of pure and single-phase In₂O₃ for all the deposited films whose crystallinity was enhanced with increasing substrate temperature, as shown by the increasing (222) peak intensity. Morphological observations were conducted using scanning electron microscopy to reveal the formation of continuous dense films composed of nanograins. The UV–vis spectra revealed that the transmittance increased with increasing substrate temperature, reaching a value of over 80% at 450 °C. The photoelectric performance of the solar cell was studied using the I–V curve by illuminating the cell at 100 mW/cm². A high efficiency (η) of 3.325% with I_sc and V_oc values of 14.8 mA/cm² and 0.60 V, respectively, was attained by the ITO solar cell annealed at 450 °C.     

Specific Contact Resistance Measurement of Screen-Printed Ag Metal Contacts Formed on Heavily Doped Emitter Region in Multicrystalline Silicon Solar Cells

Multicrystalline silicon (mc-Si) wafers are widely used to develop low-cost high-efficiency screen-printed solar cells. In this study, the electrical properties of screen-printed Ag metal contacts formed on heavily doped emitter region in mc-Si solar cells have been investigated. Sintering of the screen-printed metal contacts was performed by a co-firing step at 725°C in air ambient followed by low-temperature annealing at 450°C for 15 min. Measurement of the specific contact resistance (ρ _c) of the Ag contacts was performed by the three-point probe method, showing a best value of ρ _c = 1.02 × 10^?4 Ω cm² obtained for the Ag contacts. This value is considered as a good figure of merit for screen-printed Ag electrodes formed on a doped mc-Si surface. The plot of ρ _c versus the inverse of the square root of the surface doping level (N _s ^?½ ) follows a linear relationship for impurity doping levels N _s ≥ 10¹⁹ atoms/cm³. The power losses due to current traveling through various resistive components of finished solar cells were calculated by using standard expressions. Cross-sectional scanning electron microscopy (SEM) views of the Ag metal and doped mc-Si region show that the Ag metal is firmly coalesced with the doped mc-Si surface upon sintering at an optimum firing temperature of 725°C.     

Fluxless Bonding of Large Silicon Chips to Ceramic Packages Using Electroplated Eutectic Au/Sn/Au Structures

A fluxless process of bonding large silicon chips to ceramic packages has been developed using a Au-Sn eutectic solder. The solder was initially electroplated in the form of a Au/Sn/Au multilayer structure on a ceramic package and reflowed at 430°C for 10 min to achieve a uniform eutectic 80Au-20Sn composition. A 9 mm × 9 mm silicon chip deposited with Cr/Au dual layers was then bonded to the ceramic package at 320°C for 3 min. The reflow and bonding processes were performed in a 50-mTorr vacuum to suppress oxidation. Therefore, no flux was used. Even without any flux, high-quality joints were produced. Microstructure and composition of the joints were studied using scanning electron microscopy with energy-dispersive x-ray spectro- scopy. Scanning acoustic microscopy was used to verify the joint quality over the entire bonding area. To employ the x-ray diffraction method, samples were made by reflowing the Au/Sn/Au structure plated on a package. This was followed by a bonding process, without a Si chip, so that x-rays could scan the solder surface. Joints exhibited a typical eutectic structure and consisted of (Au,Ni)Sn and (Au,Ni)₅Sn phases. This novel fluxless bonding method can be applied to packaging of a variety of devices on ceramic packages. Its fluxless nature is particularly valuable for packaging devices that cannot be exposed to flux such as sensors, optical devices, medical devices, and laser diodes.     

Silicon Nitride Films Deposited by RF Sputtering for Microstructure Fabrication in MEMS

In the present work, we report silicon nitride films deposited by a radio- frequency (RF) sputtering process at relatively low temperatures (<260°C) for microelectromechanical system (MEMS) applications. The films were prepared by RF diode sputtering using a 3-inch-diameter Si₃N₄ target in an argon ambient at 5 mTorr to 20 mTorr pressure and an RF power of 100 W to 300 W. The influence of the film deposition parameters, such as RF power and sputtering pressure, on deposition rate, Si-N bonding, surface roughness, etch rate, and stress in the films was investigated. The films were deposited on single/double-side polished silicon wafers and transparent fused-quartz substrates. To explore the RF-sputtered silicon nitride film as a structural material in MEMS, microcantilever beams of silicon nitride were fabricated by bulk, surface, and surface-bulk micromachining technology. An RF-sputtered phosphosilicate glass film was used as a sacrificial layer with RF-sputtered silicon nitride. Other applications of sputtered silicon nitride films, such as in the local oxidation of silicon (LOCOS) process, were also investigated.     

Selective bonding and encapsulation for wafer-level vacuum packaging of MEMS and related micro systems

A laser-assisted bonding technique is demonstrated for low temperature region selective processing. A continuous wave carbon dioxide (CO₂) laser (λ=10.6 μm) is used for solder (Pb37/Sn63) bonding of metallized silicon substrates (chips or wafers) for MEMS applications. Laser-assisted selective heating of silicon led to the reflow of an electroplated, or screen-printed, intermediate solder layer which produced silicon–solder–silicon joints. The bonding process was performed on fixtures in a vacuum chamber at an air pressure of 10⁻³ Torr to achieve fluxless soldering and vacuum encapsulation. The bonding temperature at the sealing ring was controlled to be close to the reflow temperature of the solder. Pull test results showed that the joint was sufficiently strong. Helium leak testing showed that the leak rate of the package met the requirements of MIL-STD-883E under optimized bonding conditions and bonded packages survived thermal shock testing. The testing, based on a design of experiments method, indicated that both laser incident power and scribe velocity significantly influenced bonding results. This novel method is especially suitable for encapsulation and vacuum packaging of chips or wafers containing MEMS and other micro devices with low temperature budgets, where managing stress distribution is important. Further, released and encapsulated devices on the sealed wafers can be diced without damaging the MEMS devices at wafer level.     

Possibility of the use of intermediate carbidsiliconoxide nanolayers on polydiamond substrates for gallium nitride layers epitaxy

The results of using carbidsiliconoxide (a-C:SiO1_.5) films with a thickness of 30–60 nm, produced by the pyrolysis annealing of oligomethylsilseskvioksana (CH₃–SiO_1.5)_n with cyclolinear (staircased) molecular structure, as intermediate films in the hydride vapor phase epitaxy of gallium nitride on polycrystalline CVD-diamond substrates are presented. In the pyrolysis annealing of (CH₃–SiO_1.5)_n films in an atmosphere of nitrogen at a temperature of 1060°C, methyl radicals are carbonized to yield carbon atoms chemically bound to silicon. In turn, these atoms form a SiC monolayer on the surface of a-C:SiO_1.5 films via covalent bonding with silicon. It is shown that GaN islands grow on such an intermediate layer on CVD-polydiamond substrates in the process of hydride vapor phase epitaxy in a vertical reactor from the GaCl–NH₃–N₂ gas mixture.     

Microstructure evolution of gold-tin eutectic solder on Cu and Ni substrates

The microstructures of the eutectic Au20Sn (wt.%) solder that developed on the Cu and Ni substrates were studied. The Sn/Au/Ni sandwich structure (2.5/3.75/2 μm) and the Sn/Au/Ni sandwich structure (1.83/2.74/5.8 μm) were deposited on Si wafers first. The overall composition of the Au and the Sn layers in these sandwich structures corresponded to the Au20Sn binary eutectic. The microstructures of the Au20Sn solder on the Cu and Ni substrates could be controlled by using different bonding conditions. When the bonding condition was 290°C for 2 min, the microstructure of Au20Sn/Cu and Au20Sn/Ni was a two-phase (Au₅Sn and AuSn) eutectic microstructure. When the bonding condition was 240°C for 2 min, the AuSn/Au₅Sn/Cu and AuSn/Au₅Sn/Ni diffusion couples were subjected to aging at 240°C. The thermal stability of Au20Sn/Ni was better than that of Au20Sn/Cu. Moreover, less Ni was consumed compared to that of Cu. This indicates that Ni is a more effective diffusion barrier material for the Au20Sn solder.     

Fabrication and Microstructures of Sequentially Electroplated Sn-Rich Au-Sn Alloy Solders

Three Sn-rich, Au-Sn alloy solders with eutectic, hypoeutectic, and hypereutectic Sn compositions were fabricated by sequential electroplating of Au and Sn and then the dual-layer films were reflowed at 250°C. The microstructures and phase compositions of the deposited Au/Sn dual-layer film and the reflowed Sn-rich Au-Sn alloys were studied. Microhardness values of the different phases or phase zones for the reflowed alloys were also tested. Finally, two Si wafers were bonded together with the eutectic Sn-rich Au-Sn alloy solder. For as deposited Au/Sn dual-layer films, reaction between Au and Sn occurs at room temperature leading to the formation of Au₅Sn, AuSn, and AuSn₂ at the Au/Sn interface. After reflowing at 250°C, two phases remain, Sn and AuSn₄, with the morphology and phase distribution depending on the original solder composition. In the Sn-rich, eutectic Au-Sn alloy, AuSn₄ particles are distributed uniformly in the Sn matrix. In the Sn-rich hypoeutectic/hypereutectic Au-Sn alloys, the proeutectic phase, AuSn₄ (Vickers hardness, Hv 125) or Sn (Hv 14.2), is larger in size and is surrounded by the eutectic zone (Sn + AuSn₄) (Hv 16.1). In all cases, the TiW adhesion and barrier layer remains intact during annealing. After reflowing at 250°C under a pressure of 13 kPa, two Si wafers are joined by the Sn-rich eutectic Au-Sn alloy solder, without crack or void formation at the Si wafer/solder interface or within the solder.     

C-V characteristics of metal-titanium dioxide-silicon capacitors

Titanium dioxide capacitors were fabricated on silicon wafers using electron-beam evaporation. The TiO₂ films varied in thickness from 500 to 2000 Å. Post-deposition oxidation at 1000°C in dry O₂ was used to promote stoichiometric conversion of the films to the rutile phase. Capacitive densities of greater than 2 pf/sq. mil were obtained (dielectric constants ranged from 4 to 40). For long oxidation times, significant silicon dioxide grows under the TiO₂ as a result of oxygen diffusing through the TiO₂ film. Titanium was also shown to diffuse into the silicon during the oxidation cycle resulting in an n-type diffusion. Surface state densities ranging from 10¹¹ to 5 × 10¹¹ cm^?2 eV^?1 at midgap were obtained for good devices. Longer oxidation times result in lower capacitance, leakage current and surface state density.     

Low temperature annealing behaviors of the titanium films formed by the ionized sputtering process on (001) silicon substrates

We investigated the low temperature reactions between the Ti films created by the ionized sputtering process and the (001) single crystal silicon wafers using high resolution transmission electron microscopy and x-ray diffractometry. We observed that the amorphous Ti-Si intermixed layer is formed at the Ti-Si interface whose thickness increased with the thickness of the deposited Ti films. The amorphous interlayer grew upon annealing treatments at the temperatures below 450°C. We also observed that the crystallization of the amorphous interlayer occurred upon annealing at 500°C. The first formed phase is Ti₅Si₃ in contact with Ti films, which is epitaxial with Ti films. Upon further annealing at 500°C, the Ti₅Si₄ phase and C49 TiSi₂ phase formed in the regions close to Ti films and Si substrates, respectively.     

Improving the performance of radial n-i-p junction Si nanowire solar cells by catalyst residue removal

It is hoped that silicon nanowire (SiNW)-based solar cells will provide the basis for a new generation of photovoltaics. However, metal-catalyzed SiNWs contain metal residues (such as indium) which may degrade the performance of solar cells. In this study, we prepared SiNW solar cells by plasma-enhanced chemical vapor deposition using indium as the catalyst to grow the SiNWs. The SiNWs were treated with hydrochloric acid to reduce the indium contamination at different concentrations, C_HCl (1–5%). We found the decreasing the indium contamination improved the performance of the solar cells at optimum C_opHCl. However, the performance of the solar cells decreased when C_HCl exceeded C_opHCl. This was attributed to the variation in the conduction-band offset ΔE_c between the n type amorphous silicon layer (E_c n-a-Si) and the n type crystalline silicon nanowires (E_c n-c-SiNWs). Finally, a conversion efficiency (Eff) improvement from 2.11% to 6.18% was obtained with the optimized C_HCl.     

Bifacial concentrator Ag‐free crystalline n‐type Si solar cell

We report results obtained using an innovative approach for the fabrication of bifacial low‐concentrator thin Ag‐free n‐type Cz‐Si (Czochralski silicon) solar cells based on an indium tin oxide/(p⁺nn⁺)Cz‐Si/indium fluorine oxide structure. The (p⁺nn⁺)Cz‐Si structure was produced by boron and phosphorus diffusion from B‐ and P‐containing glasses deposited on the opposite sides of n‐type Cz‐Si wafers, followed by an etch‐back step. Transparent conducting oxide (TCO) films, acting as antireflection electrodes, were deposited by ultrasonic spray pyrolysis on both sides. A copper wire contact pattern was attached by low‐temperature (160°C) lamination simultaneously to the front and rear transparent conducting oxide layers as well as to the interconnecting ribbons located outside the structure. The shadowing from the contacts was ~4%. The resulting solar cells, 25 × 25 mm² in dimensions, showed front/rear efficiencies of 17.6–17.9%/16.7–17.0%, respectively, at one to three suns (bifaciality of ~95%). Even at one‐sun front illumination and 20–50% one‐sun rear illumination, such a cell will generate energy approaching that produced by a monofacial solar cell of 21–26% efficiency. Copyright © 2014 John Wiley & Sons, Ltd.     

Tuning the Phase and Microstructural Properties of TiO<Subscript>2</Subscript> Films Through Pulsed Laser Deposition and Exploring Their Role as Buffer Layers for Conductive Films

Titanium oxide (TiO₂) is a semiconducting oxide of increasing interest due to its chemical and thermal stability and broad applicability. In this study, thin films of TiO₂ were deposited by pulsed laser deposition on sapphire and silicon substrates under various growth conditions, and characterized by x-ray diffraction (XRD), atomic force microscopy (AFM), optical absorption spectroscopy and Hall-effect measurements. XRD patterns revealed that a sapphire substrate is more suitable for the formation of the rutile phase in TiO₂, while a silicon substrate yields a pure anatase phase, even at high-temperature growth. AFM images showed that the rutile TiO₂ films grown at 805°C on a sapphire substrate have a smoother surface than anatase films grown at 620°C. Optical absorption spectra confirmed the band gap energy of 3.08 eV for the rutile phase and 3.29 eV for the anatase phase. All the deposited films exhibited the usual high resistivity of TiO₂; however, when employed as a buffer layer, anatase TiO₂ deposited on sapphire significantly improves the conductivity of indium gallium zinc oxide thin films. The study illustrates how to control the formation of TiO₂ phases and reveals another interesting application for TiO₂ as a buffer layer for transparent conducting oxides.     

Carboxylate-Passivated Silver Nanoparticles and Their Application to Sintered Interconnection: A Replacement for High Temperature Lead-Rich Solders

Lead-free silver nanoparticle pastes have been tested as a replacement for high temperature lead-rich solders used in electronic manufacturing. The pastes contain a small amount of solvent, and primarily consist of submicron-silver powder and passivated silver nanoparticles. The nanoparticles were synthesized from Ag₂CO₃ and a long-chain alcohol by a method that produced a passivating layer consisting almost exclusively of the carboxylate of the reactant alcohol. The pastes were used to connect a silicon diode chip to copper bases without applied pressure when sintered at 350°C under nitrogen. Diode packages made with sintered silver interconnects had electrical and thermal properties equal to those with lead-soldered interconnects, even after 3000 thermal cycles between −55°C and +150°C. The mechanical strength was half that of lead-rich solder joints, but still strong enough for practical use.     

Characteristics of a-Si solar cells prepared by the super chamber at a high substrate temperature

A new approach to high-performance a-Si solar cells was studied. a-Si films prepared at a high substrate temperature (> 250°C) have a higher absorption coefficient and a low Si H₂ bond density. the effect of deposition temperature on the open-circuit voltage (V_oc) has been investigated systematically for glass/SnO2 Ipin/metal and glass/metal/nip/indium tin oxide (ITO) structure a-Si solar cells. The V_oc is found to depend strongly on the thermal history of the p/i interface. A short-circuit current of 19.5 mA/cm⁻⁻² was achieved for an a-Si solar cell using an a-Si i-layer with a thickness of 4000 Å, which was prepared at a substrate temperature of 270°C.     

Gettering by heat thermal processing: application in crystalline silicon solar cells

The aim of this work is to getter unwanted impurities from solar grade crystalline silicon (Si) wafers and then to enhance their electronic properties. This was done by forming a sacrificial porous silicon (PS) layer on both sides of the Si wafers and by performing infrared (IR) thermal annealing treatments (at around 950 °C) in a SiCl₄/N₂ controlled atmosphere. The process allows concentrating unwanted impurities in the PS layer and near the PS/silicon interface. These treatments reduce the resistivity by about two orders of magnitude at a depth of about 40 μm and improve the minority carrier diffusion length from 75 to 210 μm. This gettering method was also tested on silicon wafers where grooved fingers and back contacts were achieved using a chemical vapor etching (CVE) method. Front buried metallic contacts and small holes for local back surface field were then achieved after the gettering stage in order to realize silicon solar cells. It was shown that the photovoltaic parameters of gettered silicon solar cells were improved as regard to ungettered ones.     

Parallel angle resolved XPS investigations on 12 in. wafers for the study of W and WSix oxidation in air

Parallel angle resolved X-ray photoelectron spectroscopy (ARXPS) was used to study the oxidation of W and WSi_x thin films CVD-deposited on 12 in. silicon wafers. The thin films were exposed to air during defined periods of time. Immediately after layer deposition, the wafers were rapidly loaded in a vacuum carrier in order to measure various aspects of the oxidation kinetic by XPS. Angle resolved data were exploited to obtain accurate tungsten oxide thicknesses measurements and the results were compared with X-ray reflectometry (XRR). A precise in-depth evolution of the W oxidation kinetic, in term of oxidation velocity and bonding environment, was obtained. Non-destructive profiles of the first five nanometers of a WSi_x surface were extracted from Angle Resolved data. These profiles were compared to ToF-SIMS analysis, and we clearly show the presence of a stoichiometric silicon dioxide passive layer covering WSi_x silicide.