Breakdown voltage characteristics of thin oxides and their correlation to defects in the oxide as observed by the EBIC technique

Thin oxides are widely used as the tunneling dielectric in floating gate EEPROM devices and as gate dielectric in short-channel MOS devices. The oxides are required to have high breakdown voltage and low defect density for reliable operation of the devices. With the Electron Beam Induced Current (EBIC) technique, defects in the oxide which lead to lower values of the oxide breakdown voltage have been observed.     

Future challenges of flash memory technologies

Flash memory application has seen explosive growth in recent years and this trend is likely to continue because new and more demanding applications are constantly added partly due to the need for low power solid-state storage and partly due to rapidly declining prices. Conventional floating gate flash memories, no matter in NOR or NAND architecture, however, face steep challenges. For NOR flash, the junction breakdown and short channel effects have essentially squeezed out the device design space below 45 nm node. For NAND flash, the tight spacing, floating gate interference and the need for sufficient gate control (gate coupling ratio) have also ruled out the continuation of the conventional floating gate device below approximately 32 nm node. Charge trapping devices, exploiting high-K inter-poly dielectric (IPD) or by innovative tunneling barrier engineering, are proposed to continue scaling flash memories. Eventually, when too few electrons are stored and the logic level retention becomes smeared by statistical fluctuation over the life time of the device, 3-D layering of devices may provide the ultimate solution.     

Gate-induced floating body effect excess noise in partially depleted SOI MOSFETs

Low frequency excess noise associated to gate-induced floating body effect is for the first time reported in Partially Depleted SOI MOSFETs with ultrathin gate oxide. This was investigated with respect to floating body devices biased in linear regime. Due to a body charging from the gate, a Lorentzian-like noise component superimposes to the conventional 1/f noise spectrum. This excess noise exhibits the same behavior as the Kink-related excess noise previously observed in Partially Depleted devices in saturation regime.     

Oxide charge measurements in EEPROM devices

A method to measure “on site” programmed charges in EEPROM devices is presented. Electrical AFM based techniques (Electric Force Microscopy (EFM) and Scanning Kelvin Probe Microscopy (SKPM)) are used to probe directly floating gate potentials. Both preparation and probing methods are discussed. Sample preparation to access floating gate/oxide interfaces at a few nanometers distance without discharging the data reveals to be the key point, more than the probing technique itself.     

A new technique for measuring coupling coefficients and 3-Dcapacitance characterization of floating-gate devices

The characteristics of the capacitance in floating-gate devices are comprehensively investigated. The capacitive coupling coefficient (α_c) between the control and floating gates is measured simultaneously, by a new technique, with the shift in threshold voltage during the programming. The present results are compared with those found from other methods and the dependence of α_c on applied voltages is examined. It is also shown that the α_c -data from a set of test patterns with varying floating-gate widths leads to the 3-D characterization of small geometry floating gate devices down to subfemto Farads. These measured characteristics are discussed in correlation with the effects of both the short channel length and of the narrow gate width     

Study of internal behavior in a vertical DMOS transistor under short high current stress by an interferometric mapping method

Current distribution in vertical double-diffused MOS (DMOS) transistors of a Smart Power Technology are investigated under high current, short duration operation conditions by means of a backside laser interferometric thermal mapping technique. DMOS devices of different areas are studied under pulsed gate forward operation mode and under electrostatic discharge (ESD)-like stress with floating and grounded gate. The internal behavior of the devices observed by thermal mapping under these stress conditions is correlated with the electrical characteristics.     

Fatigue phenomena of FTMIS memory transistors

Two operation modes of long endurance and their fatigue properties are described for a nonvolatile charge storage memory device which employs a floating silicon gate tunnel injection MIS (FTMIS) structure. The device is composed of an n-channel metal gate field effect transistor with a floating gate over tunnelable (20-35 Å) SiO2. The floating gate consists of highly resistive polycrystalline Si grains. Gate oxidation isolates each poly-Si grain, resulting in a structure of islands. This improves retention characteristics. The primary feature of these devices is that no fatigue phenomena are observed for 2 × 10¹²cycles continuous write-erase operation in the conventional operation mode. In addition, it is possible both to write and erase in the other operation mode with only positive pulses to the gate electrode. Furthermore, stored data is retained more than one year without any external power supply. Therefore the device is an excellent candidate for nonvolatile RAM applications as a semiconductor memory device.     

An erase model for FAMOS EPROM devices

A physical model is presented which explains the various features of the UV erase process in FAMOS EPROM devices. An erase sensitivity factor is defined in this model, and correlated with experimental results. The erase sensitivity factor was found to be proportional to the floating-gate photoinjecting area, and inversely proportional to oxide thickness and total capacitance of the floating gate. Photoinjection of electrons from thin strips on the floating-gate edges are shown to be responsible for the charge removal from the floating gate. Quantum yields in the order of 10^-4were measured for this erase process and correlated with values found in the literature. In addition, theI-Vand spectral characteristics of photoinjected currents as low as 10^-15A from poly-Si to SiO2in FAMOS devices were measured and compared to data from Si-SiO2structures. Special features pertaining to the erase of a fully covered floating-gate FAMOS cell were investigated: the decrease in erase rate at lowDelta V_{t}is discussed, as well as the optical access to the floating gate in these devices. Based on experimental and theoretical grounds, hole injection is discounted as a possible erase mechanism in the structures investigated.     

Charge storage in InAlAs/InGaAs/InP floating gate heterostructures

Charge retention in floating gate InAlAs/InGaAs/InP field effect transistors is limited by lateral electron motion along the storage channel, a different direction for motion than found for AlAs/GaAs devices. Storage times as a function of temperature for the InP based alloy devices are reported and compared with similar AlAs/GaAs devices by using Poisson equation models.<>     

Well-driven floating gate transistors

A new layout structure for floating gate MOS devices on top of an isolating n-well is proposed. The well provides the floating device with noise isolation from the substrate and can also be used as an additional input for threshold voltage control or signal modulation     

Requirements for accurate MOS-SOI device simulations

Simulations of the electrical behavior of MOS-SOI devices pose a difficult numerical problem due to the floating substrate region. The numerical analysis techniques required to solve the floating region problem are discussed. Models for the carrier mobilities and lifetime variation with depth into the silicon film are introduced to fit measured SOS device data. The current-voltage characteristics of SOS transistors, including the kink, are accurately simulated and compared to measurements. The floating potential variation with applied gate and drain bias predicted by the simulation is discussed     

Au纳米晶MIS结构存储性能研究

从器件结构和能带的角度分析了提高非易失性存储器性能的可能途径,建立了纳米晶浮栅结构的存储模型,并在模型中考虑了量子限制效应对纳米晶存储性能的影响.基于模型计算,分析了纳米晶材料、高k隧穿介质材料及其厚度对纳米晶浮栅结构存储性能的影响.同时,制作了MIS结构(Si/ZrO2/Au Ncs/SiO2/Al)的存储单元,针对该存储单元的电荷存储能力和电荷保持特性进行测试,并对测试结果进行分析.     

Influence of Floating Body Effect on Radiation Hardness of PD SOI nMOSFETs

H-gate and closed-gate PD SOI nMOSFETs are fabricated on SIMOX substrate,and the influence of floating body effect on the radiation hardness is studied.All the subthreshold characteristics of the devices do not change much after radiation of the total dose of 1e6rad(Si).The back gate threshold voltage shift of closed-gate is about 33% less than that of Hgate device.The reason should be that the body potential of the closed-gate device is raised due to impact ionization,and an electric field is produced across the BOX.The floating body effect can improve the radiation hardness of the back gate transistor.     

PD SOI nMOSFETs中浮体效应对辐照性能的影响

在SIMOX衬底上制备了H形栅和环形栅PD SOI nMOSFETs,并研究了浮体效应对辐照性能的影响.在106rad(Si)总剂量辐照下,所有器件的亚阈特性未见明显变化.环形栅器件的背栅阈值电压漂移比H型栅器件小33%,其原因是碰撞电离使环形栅器件的体区电位升高,在埋氧化层中形成的电场减小了辐照产生的损伤.浮体效应有利于改进器件的背栅抗辐照能力.     

PD SOI MOSFET低频噪声研究进展

随着器件尺寸的不断减小,PD SOI器件的低频噪声特性对电路稳定性的影响越来越大.研究了PD SOI器件低频过冲噪声现象,分析了此类器件在发生浮体效应、栅致浮体效应以及前背栅耦合效应时低频过冲噪声的产生机理及影响因素.最后指出,可以通过添加体接触或将PD SOI器件改进为双栅结构,达到有效抑制低频过冲噪声的目的.     

Multibit Optoelectronic Memory in Top‐Floating‐Gated van der Waals Heterostructures

Nonvolatile memories based on van der Waals heterostructures have been proved to be promising candidates for next‐generation data storage devices. However, little attention has been focused on the structure with separated floating and control gates (the floating gates and control gates distribute at the different side of the channels), which were recently predicted to be capable of further improving device performance. Here, nonvolatile multibit optoelectronic memories are demonstrated using MoS₂, hexagonal boron nitride (h‐BN), and graphene in a top‐floating‐gated structure. With separated top graphene floating gate, the devices show a large memory window (≈95 V) via sweeping gate voltage from 80 to ?80 V, a high on/off ratio (≈10⁶) with an ultralow dark current (≈10^?14 A), as well as excellent retention characteristic (≈10⁴ s) and cyclic endurance. In addition, these devices can also be erased by a laser illumination with broadband spectrum after being electrically programmed. For the multilevel storage property, 7/6 stages controlled by different electrical operations, and 13/6/3 stages by different laser pulse illuminations are gained. The obtained results show a promising performance for nonvolatile optoelectronic memory using a top‐floating‐gated structure.     

A floating well method for exact capacitance-voltage measurement of nano technology

Small gate area with short gate length reduces the C-V distortion of ultrathin oxide devices, but results in high parasitic capacitance/total capacitance ratio. The floating well method can exclude the parasitic capacitance to obtain accurate inversion oxide thickness without using any dummy pattern. It is suitable for nano technology.     

Simultaneous quality improvement of tunneling- and interpoly-oxides of nonvolatile memory devices by NH/sub 3/ and N/sub 2/O nitridation

This brief presents a new nitridation process on a floating poly-Si gate to improve the quality of both tunneling oxide and interpoly-oxide of nonvolatile memories. Three types of poly-Si for a floating gate have been investigated. We found in-situ doped poly-Si shows the best performance in terms of breakdown field, charge-to-breakdown (Q/sub BD/) and trapping rate. The Q/sub BD/ of interpoly-oxide can be reached as high as 35 C/cm/sup 2/. This scheme is very promising for nonvolatile memory devices.     

Characteristics of a new EPROM cell structure with a sidewall floating gate

A new EPROM cell with a sidewall floating gate is proposed and evaluated. The cell structure is similar to that of the usual n-channel MOSFET and has good compatibility, in regard to its fabrication process, with future VLSI devices. The new cell does not require such large coupling capacitance between control gate and floating gate, which results in higher density integration with reduced programming voltages as low as 8 V or less. In actual use of the new cell, the roles of source and drain are reversed in the program mode and in the readout mode. It is shown that the apparent programming characteristics depend on the bias conditions in the readout mode. Very good tolerance to unintentional programming is obtained in the read-out mode, and also in the program mode at half selection.     

Flash存储器浮栅单元的总剂量效应统计性分析

针对核设施机电设备中控制系统存储单元耐辐射可靠性评价的需要,以国产NOR型Flash存储器为研究对象,对器件存储阵列浮栅单元的总剂量损伤阈值开展了实验研究。综合利用SMOTE算法和Bootstrap法建立了一种基于极小子样的器件耐辐照可靠性评价方法,对被测样品校验失效剂量进行了统计分析。实验结果表明,器件浮栅单元的主要失效模式为浮栅电荷损失造成的阈值电压降低,平均校验错误剂量为(631.89±103.64)Gy(Si)。统计分析表明,器件总剂量损伤阈值服从对数正态分布。基于SMOTE-Bootstrap的可靠性评价方法避免了传统Bootstrap再生样本过于集中的问题,可应用于极小子样的可靠性评价。