32 nm node BEOL integration with an extreme low-k porous SiOCH dielectric k = 2.3

A 32 nm node BEOL integration scheme is presented with 100 nm metal pitch at local and intermediate levels and 50 nm via size through a M1-Via1-M2 via chain demonstrator. To meet the 32 nm RC performance specifications, extreme low-k (ELK) porous SiOCH k = 2.3 is introduced at line and via level using a Trench First Hard Mask dual damascene architecture. Parametrical results show functional via chains and good line resistance. Integration validation of ELK porous SiOCH k = 2.3 is investigated using a multi-level metallization test vehicle in a 45 nm mature generation.     

Capacitance-voltage analysis of InAs quantum dots grown on InAlAs/InP(0 0 1)

The electronic properties of InAs quantum dots (QDs) grown on InAlAs/InP(0 0 1) were studied by using capacitance-voltage (C-V) analysis and photoluminescence (PL) measurements. The level positions of electrons and holes could be studied separately by using n- and p-type InAlAs matrices, respectively. The holes are found to be more confined than electrons in these kinds of dots.     

FinFET based SRAM bitcell design for 32 nm node and below

The methodology of designing FinFET bitcell is presented in detail. Determination of Fin configuration (i.e., Fin thickness, space, height, and number) in the bitcell involves consideration of both layout and electrical optimization. Once optimized through the proposed method, FinFET bitcell can provide higher cell current, lower leakage current and much lower V_ccmin with smaller bitcell area, as compared to planar bitcell, which allows continuous scaling of SRAM bitcell <0.1 μm² below 32 nm node.     

Behaviour of CPW and TFMS lines at high temperature for RF applications in sub-45 nm nodes

Coplanar waveguide (CPW) and thin film microstrip (TFMS) lines integrating porous ultra low-k as inter-metal dielectric layers (k = 2.5) and copper as metal, are for the first time experimentally measured up to 110 GHz and under different temperature conditions, up to 200 °C. The extracted attenuation and propagation coefficients of those transmission lines are compared to simulations performed with MAGWEL software, a frequency domain 3-D Maxwell solver. Based on the characterization results some guidelines related to interconnect design are presented for future applications.     

Growth and fabrication of AlGaN/GaN HEMT based on Si(1 1 1) substrates by MOCVD

AlGaN/GaN high electron mobility transistor (HEMT) hetero-structures were grown on the 2-in Si (1 1 1) substrate using metal-organic chemical vapor deposition (MOCVD). Low-temperature (LT) AlN layers were inserted to relieve the tension stress during the growth of GaN epilayers. The grown AlGaN/GaN HEMT samples exhibited a maximum crack-free area of 8 mm×5 mm, XRD GaN (0 0 0 2) full-width at half-maximum (FWHM) of 661 arcsec and surface roughness of 0.377 nm. The device with a gate length of 1.4 μm and a gate width of 60 μm demonstrated maximum drain current density of 304 mA/mm, transconductance of 124 mS/mm and reverse gate leakage current of 0.76 μA/mm at the gate voltage of −10 V.     

Impact of process parameters on circuit performance for the 32 nm technology node

As IC dimensions scale down to the 32 nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications.     

Impact of porous SiOCH on propagation performance measured for narrow interconnects of the 45 nm node

With the dimensions scaling down at each new technology node, introduction of porous dielectric materials is required to reduce the interconnect capacitance. Nevertheless, these materials are very prone to damage during integration, thus increasing their K-value (2.5 as deposited for the 45 nm node) in the final circuit. In order to characterize these effects, high-frequency measurements and electromagnetic simulations were carried out on specific microstrip structures. Taking into account typical circuit characteristics, time-domain extraction of delay values and crosstalk levels were then performed, enabling a precise analysis of moisture uptake effects from a performance point of view.     

New materials of spin-on organic hardmask for sub-70 nm devices

In ArF lithography for sub-80 nm L/S, amorphous carbon layer (ACL) deposition becomes an inevitable process, because thin ArF resist itself cannot provide suitable etch selectivity to sub-layers. One of the problems of the ACL hardmask is the presence of surface particles, which are more problematic in mass production. Limited capacity, high cost-of-ownership, and low process efficiency also make ACL hardmasks a dilemma, which cannot be ignored by device makers. One of the answers to these problems is using a spin-on organic hardmask (SOH) material instead of ACL hardmask. Therefore, several processes including bi-layer resist process, tri-layer resist process (TLR), and multi-layer resist process have been investigated. In this paper, we have described new SOH materials applicable to 70 nm memory devices. Applications to the TLR were investigated in terms of photo property, etch property and process compatibility. Based on the test results described in this paper, our spin-on organic hardmask materials are expected to be used in mass production.