Reliability of charge trapping memories with high-k control dielectrics (Invited Paper)

In this paper, we evaluate the potentiality of high-k materials (Al₂O₃, HfO₂ and HfAlO) for interpoly application in non-volatile memories. A study of the leakage currents of high-k based capacitors allowed to discuss the retention performances at room and high temperatures of high-k interpoly dielectrics. High-k materials are then integrated as control dielectrics in silicon nanocrystal and SONOS (Si/SiO₂/Si₃N₄/SiO₂/Si) memories. The role of the high-k layer on the memory performances is discussed; a particular attention being devoted to the retention characteristics. Analytical models, combined with experimental results obtained on various structures allowed to analyze the mechanisms involved during retention.     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Electrical characterization of high-k gate dielectrics fabricated using plasma oxidation and post-deposition annealing of a Hf/SiO2/Si structure

High permittivity (high-k) gate dielectrics were fabricated using the plasma oxidation of Hf metal/SiO₂/Si followed by the post-deposition annealing (PDA), which induced a solid-phase reaction between HfO_x and SiO₂. The oxidation time and PDA temperature affected the equivalent oxide thickness (EOT) and the leakage current density of the high-k dielectric films. The interfacial structure of the high-k dielectric film/Si was transformed from HfO_x/SiO₂/Si to HfSi_xO_y/Si after the PDA, which led to a reduction in EOT to 1.15 nm due to a decrease in the thickness of SiO₂. These high-k dielectric film structures were investigated by X-ray photoelectron spectroscopy. The leakage current density of high-k dielectric film was approximately four orders of magnitude lower than that of SiO₂.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.     

Fully strained Si0.75Ge0.25 epitaxial films with HfSiO gate dielectrics for high mobility channel metal-oxide semiconductor devices

The authors report on fully strained Si_0.75Ge_0.25 metal-oxide-semiconductor capacitors with HfSiO₂ high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si_0.75Ge_0.25 films are directly grown on Si substrates below the critical thickness. HfSiO₂ high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO₂ gate oxides by >100×. Interfacial oxide of the HfSiO₂/Si_0.75Ge_0.25 stack consists primarily of SiO₂ with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO₂/SiGe gate stack.     

BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO₃/HfAlO/SiO₂. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure HfAlO and AlLaO₃ replace Si₃N₄ and the top SiO₂ layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.     

A low-frequency noise model for advanced gate-stack MOSFETs

A new unified noise model is presented that accurately predicts the low-frequency noise spectrum exhibited by MOSFETs with high dielectric constant (high-k), multi-stack gate dielectrics. The proposed multi-stack unified noise (MSUN) model is based on number and correlated mobility fluctuations theory developed for native oxide MOSFETs, and offers scalability with respect to the high-k/interfacial layer thicknesses. In addition, it incorporates the various electronic properties of high-k/interfacial layer materials such as energy barrier heights between different gate layers, and dielectric trap density with respect to band energy and position in the dielectric. For verification of the new model, the low-frequency noise, DC and conventional split C-V measurements were performed in the 78-350 K temperature range on TaSiN/HfO₂ n-channel MOSFETs. The interfacial layer in these devices was either thermal SiO₂ by Stress Relieved Pre-Oxide (SRPO) pretreatment or chemical SiO₂ resulting from standard RCA (Radio Corporation of America) clean process. Using the experimental noise data, the channel carrier number fluctuations mechanism was at first established to be the underlying mechanism responsible for the noise observed at all temperatures considered. Secondly, the normalized noise exhibited a weak dependence on temperature implying that the soft optical phonons, although known to result in mobility degradation, have no effect on the noise characteristics in these high-k gate stack MOSFETs. Finally, the new model was shown to be in excellent agreement with the measured noise in 1-100 Hz frequency range at temperatures of 78-350 K for both gate stacks.     

Resistive switching effects of HfO2 high-k dielectric

Resistive switching behavior of HfO₂ high-k dielectric has been studied as a promising candidate for emerging non-volatile memory technology. The low resistance ON state and high resistance OFF state can be reversibly altered under a low SET/RESET voltage of ±3 V. The memory device shows stable retention behavior with the resistance ratio between both states maintained greater than 103. The bipolar nature of the voltage-induced hysteretic switching properties suggests changes in film conductivity related to the formation and removal of electronically conducting paths due to the presence of oxygen vacancies induced by the applied electric field. The effect of annealing on the switching behavior was related to changes in compositional and structural properties of the film. A transition from bipolar to unipolar switching behavior was observed upon O₂ annealing which could be related to different natures of defect introduced in the film which changes the film switching parameters. The HfO₂ resistive switching device offers a promising potential for high density and low power memory application with the ease of processing integration.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

Analysis of reliability characteristics of high capacitance density MIM capacitors with SiO2-HfO2-SiO2 dielectrics

In this paper, reliability as well as electrical properties of high capacitance density metal-insulator-metal (MIM) capacitor with hafnium-based dielectric is analyzed in depth. The fabricated MIM capacitor exhibits not only high capacitance density but also low voltage coefficient of capacitance (VCC) and low temperature coefficient of capacitance (TCC). It also has a low leakage current level of about ∼1 nA/cm² at room temperature and 1 V. However, it is shown that voltage linearity has a different dependence on the polarity of applied bias as temperature increases maybe due to the bulk traps between the metal electrode and high-k dielectric interface. In addition, the effect of charge trapping and de-trapping on the voltage linearity is analyzed under constant voltage stress.     

Challenges and performance limitations of high-k and oxynitride gate dielectrics for 90/65 nm CMOS technology

For low power applications, the increase of gate leakage current, caused by direct tunneling in ultra-thin oxide films, is the crucial factor eliminating conventional SiO₂-based gate dielectrics in sub-90 nm CMOS technology development. Recently, promising performance has been demonstrated for poly-Si/high-k and poly-Si/SiON gate stacks in addressing gate leakage requirements for low power applications. However, the use of poly-Si gate electrodes on high-k created additional issues such as channel mobility and reliability degradations, as well as Fermi level pinning of the effective gate work function. Therefore, oxynitride gate dielectrics are being proposed as an intermediate solution toward the sub-65/45 nm nodes. Apparently, an enhanced SiON gate dielectric stack was developed and reported to achieve high dielectric constant and good interfacial properties. The purpose of this paper is to provide a comprehensive review some of the device performance and limitation that high-k and oxynitride as dielectric materials are facing for sub-65/45 nm node.     

Characteristics of metal-oxide-semiconductor (MOS) device with Er metal gate on SiO2 film

We have investigated the structural and electrical properties of metal-oxide-semiconductor (MOS) devices with Er metal gate on SiO₂ film. Rapid thermal annealing (RTA) process leads to the formation of a high-k Er-silicate gate dielectric. The in situ high-voltage electron microscopy (HVEM) results show that thermally driven Er diffusion is responsible for the decrease in equivalent oxide thickness (EOT) with an increase in annealing temperature. The effective work function (Φ_m,eff) of Er metal gate, extracted from the relations of EOT versus flat-band voltage (V_FB), is calculated to be ∼2.86 eV.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

Dielectric anisotropy in the integration of Cu-SiLK™ system

As device density and performance continue to improve, low dielectric constant (k) materials are needed for interlevel dielectric (ILD) applications. The dielectric anisotropy of polymers with low k is an important property to consider for developing ILD. This is on-going research on the integration aspects of Cu-SiLK™ system. In this study, the dielectric anisotropy of SiLK polymer was evaluated with two test structures: the metal-insulator-metal (MIM) parallel capacitor structure for the out-of-phase dielectric constant (k_⊥) and comb-and-serpentine interdigitated structure for the in-plane dielectric constant (k_∥). A k_⊥ of 2.65, a k_∥ of 2.75, and a dielectric anisotropy of 3.77% were obtained for SiLK. However, SiLK exhibits larger leakage current as compared to amorphous SiO₂ films. The reliability issue on the integration of Cu-SiLK is discussed.     

Characterization of transient currents in HfO2 capacitors in the short timescale

We present a detailed experimental investigation of transient currents in HfO₂ capacitors in the short timescale. We show that the transient currents flowing through the capacitor plates when the gate voltage is reset to zero after a low voltage stress period follow a power-law time dependence t^−α (with α ? 1) over more than eight decades of time and down to the μs timescale. As transient currents in HfO₂ are largely increased with respect to the SiO₂ case, these results confirm that transient effects can be a severe issue for the successful integration of high-k dielectrics.     

The correlation of the electrical properties with electron irradiation and constant voltage stress for MIS devices based on high-k double layer (HfTiSiO:N and HfTiO:N) dielectrics

This paper describes the influence of e-beam irradiation and constant voltage stress on the electrical characteristics of metal-insulator-semiconductor structures, with double layer high-k dielectric stacks containing HfTiSiO:N and HfTiO:N ultra-thin (1 and 2 nm) films. The changes in the electrical properties were caused by charge trapping phenomena which is similar for e-beam irradiation and voltage stress cases. The current flow mechanism was analyzed on the basis of pre-breakdown, soft-breakdown and post-breakdown current-voltage (J-V) experiments. Based on α-V analysis (α=d[ln(J)]/d[ln(V)]) of the J-V characteristics, a non-ideal Schottky diode-like current mechanism with different parameters in various ranges of J-V characteristics is established, which limits the current flow in these structures independent of irradiation dose or magnitude of applied voltage during stress.     

高介电常数栅介质/二氧化硅界面偶极子成因研究

The formation of an electric dipole at the high-k/SiO2 interface is quantitatively analyzed. The band lineups and physical origin of dipole formation at the high-k/SiO2 interface are explained by the dielectric contact induced gap states(DCIGS). The charge neutrality level(CNL) of the DCIGS, which represents a distribution of high-k and SiO2 contact induced gap states, is utilized to study the dipole moment. The charge transfer due to different CNLs of high-k and SiO2 is considered as the dominant origin of dipole formation. The theoretically calculated dipole strengths of high-k/SiO2 systems based on this model are in good agreement with the experimental data.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.