Fabrication and characterization of Zr-rich Zr-aluminate films for high-κ gate dielectric applications

Two kinds of Zr-rich Zr-aluminate films for high-κ gate dielectric applications with the nominal composition of (ZrO₂)_0.8(Al₂O₃)_0.2 and (ZrO₂)_0.9(Al₂O₃)_0.1, were deposited on n-type silicon wafer by pulsed laser deposition (PLD) technique at different deposition conditions. X-ray diffraction (XRD) reveals that the (ZrO₂)_0.8(Al₂O₃)_0.2 film could remain amorphous after being rapid thermal annealed (RTA) at the temperature above 800 °C, while the other one displays some crystalline peaks at 700 °C. The energy gap calculated from optical transmittance spectrum of (ZrO₂)_0.8(Al₂O₃)_0.2 film on quartz is about 6.0 eV. Sputtering depth profile of X-ray photoelectron spectroscopy and Auger electron spectroscopy indicate that a Zr-Si-O interfacial layer was formed at the near surface of the silicon substrate. The dielectric constant of the (ZrO₂)_0.8(Al₂ O₃)_0.2 film has been determined to be 22.1 by measuring a Pt/(ZrO₂)_0.8(Al₂ O₃)_0.2/Pt MIM structure. An EOT of 1.76 nm with a leakage current density of 51.5 mA/cm² at 1 V gate voltage for the film deposited in N₂ were obtained. Two different pre-treatments of Si substrates prior to depositions were also carried out and compared. The results indicate that a surface-nitrided Si substrate can lead to a lower leakage current density. The amorphous Zr-rich Zr-aluminate films fabricated by PLD have promising structure and dielectric properties required for a candidate material for high-κ gate dielectric applications.     

Correction of the method of current-voltage characteristics for determination of density of surface states in the system of germanium-rare-earth element fluoride

The results of studies of the interface of Ge with fluorides of Dy, La, and Sm in the metal-insulator-semiconductor structure are reported. The character of the energy spectrum and density of surface states for the interface of Ge with various fluorides of rare-earth elements is determined. For this purpose, the comparative analysis of the results obtained based on two methods, namely, the methods of current-voltage and capacitance-voltage characteristics, was carried out. The analysis showed that the information found from the current-voltage characteristics should be corrected taking into account the results obtained using other measurements, for example, the capacitance-voltage characteristics. This comparison also provided additional data on the properties of the interface; specifically, the thickness of the layer of the tunneling-thin insulator was determined.     

Ge volatilization products in high-k gate dielectrics

GeO molecules are often emitted by Ge substrates under high-temperature annealing and, in the case of gate stacks, they diffuse through high-k oxides. Here we use first-principles quantum-mechanical calculations to probe the stability of these impurities in La₂O₃ and HfO₂ and their effect on the electronic properties of the host systems. We find that the GeO species introduce several different levels inside the energy band gaps of La₂O₃ and HfO₂. As a result, the impurities may act as charge carrier traps. Hydrogenation of the GeO defects modifies the position and numbers of gap states, but does not eliminate the carrier trap levels completely. The results suggest a possible role of Ge volatilization in enhancing leakage currents and degradation in high-k gate stacks of Ge-based devices.     

Characterization of Ni/Ho and Ni/Er fully silicided metal gates on SiO2 gate dielectric

This paper investigates the effects of Ho and Er on the sheet resistance and crystallinity of Ni(Ho) and Ni(Er) silicides, the work function (WF) modulation of Ni(Ho) and Ni(Er) fully silicided (FUSI) gate electrodes on SiO₂ dielectric, and the FUSI gated SiO₂/Si interface trap properties by using high-frequency capacitance-voltage (C-V) and photonic high-frequency C-V measurements. It was found that as the thickness percentage of rare earth (RE) metal in the Ni(Ho) or Ni(Er) increases, the sheet resistance of the silicide increases. The crystallinity decreases in the Ni(Ho) and Ni(Er) silicides, and the crystallinity decreases as the Ho thickness percentage increases. As the thickness percentage of Ho in the Ni(Ho) increases from 13% to 30%, the flatband voltage (V_FB) shift increases from −0.19 to −0.27 V. The V_FB shifts negatively 0.17 V due to 10% Er incorporation in the Ni(Er). The V_FB shift can be attributed to the effective WF decrease which may be due to the crystallinity decrease of Ni(Ho) and Ni(Er) FUSI. The interface trap density D_it calculated from the photonic high-frequency C-V curves is in good agreement with that calculated from the high-frequency and photonic high-frequency C-V curves. The Ho or Er addition does not increase the D_it.     

High quality silicon nitride deposited by Ar/N2/H2/SiH4 high-density and low energy plasma at low temperature

The high-quality PECVD silicon nitride has been deposited by high-density and low-ion-energy plasma at 400 °C and the effect of the process parameters, such as silane and nitrogen flow rate, pressure, on its structure and electrical properties has been investigated. The experimental results show that silane flow rate is the most sensitive parameter for determining deposition rate and N/Si atomic ratio of silicon nitride in the range of process parameters employed. The change of nitrogen flow rate leaded to slightly change in deposition rate, however, it effects significantly on the refractive index or densification of silicon nitride. With the addition of hydrogen gas in plasma, the hysteresis of C-V characteristics of MIS structure decreases from 0.4 to 0.1 V. The moderate increment of ion energy makes further reduction in the hysteresis of C-V characteristics of MIS from 0.1 V to below 0.05 V. The interface trap density of 6.2×10¹⁰ (ev⁻¹ cm^-2), deduced from the high frequency and quasistatic C-V characteristics of the MIS structure, is about the same as that of LPECVD silicon nitride deposited at the range of 750-850 °C. The stoichiometric silicon nitride of excellence electric and structural properties is obtained by Ar/N₂/H₂/SiH₄ high-density and low ion energy plasma.     

Barrier characteristics of gold Schottky contacts on moderately doped n-InP based on temperature dependent I-V and C-V measurements

The temperature dependences of current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the gold Schottky contacts on moderately doped n-InP (Au/MD n-InP) Schottky barrier diodes (SBDs) have been systematically investigated in the temperature range of 60-300 K. The main diode parameters, ideality factor (n) and zero-bias barrier height (apparent barrier height) were found to be strongly temperature dependent and while the decreases, the n and the increase with decreasing temperature. According to Thermionic Emission (TE) theory, the slope of the conventional Richardson plot [In(J₀/T²) vs. 1000/T] should give the barrier height. However, the experimental data obtained do not correlate well with a straight line below 160 K. This behaviour has been interpreted on the basis of standard TE theory and the assumption of a Gaussian distribution of the barrier heights due to barrier inhomogeneities that persist at the metal-semiconductor interface. The linearity of the apparent barrier height vs. 1/(2kT) plot that yields a mean barrier height of 0.526 eV and a standard deviation (σ_s0) of 0.06 eV, was interpreted as an evidence to apply the Gaussian distribution of the barrier height. Furthermore, modified Richardson plot [ vs. 1/T] has a good linearity over the investigated temperature range and gives the and the Richardson constant (A^∗) values as 0.532 eV and 15.90 AK⁻²cm⁻², respectively. The mean barrier heights obtained from both plots are appropriate with each other and the value of A^∗ obtained from the modified Richardson plot is close to the theoretical value of 9.4 AK⁻²cm⁻² for n-InP. From the C-V characteristics, measured at 1 MHz, the capacitance was determined to increase with increasing temperature. C-V measurements have resulted in higher barrier heights than those obtained from I-V measurements. The discrepancy between Schottky barrier heights(SBHs) obtained from I-V and C-V measurements was also interpreted. As a result, it can be concluded that the temperature dependent characteristic parameters for Au/MD n-InP SBDs can be successfully explained on the basis of TE mechanism with Gaussian distribution of the barrier heights.     

The effect of blocking layer of Al2O3 on thermal stability and electrical properties of HfO2 dielectric films deposited on SiGe layer

HfO₂ dielectric films with a blocking layer (BL) of Al₂O₃ on Si_0.8Ge_0.2 were treated with rapid thermal annealing process. The effect of BL on thermal stability and electrical properties was reported. X-ray photoelectron spectroscopy suggested that BL could suppress the further growth of the interfacial layer composed of SiO_x and GeO_x, and lead to the decomposition of GeO_x and the saturation of O vacancy in SiO_x structure. High-resolution transmission electron microscopy indicated that BL would keep HfO₂ amorphous after annealed treatment. Electrical measurements indicated that there was no stretch-out in capacitance-voltage curves, the accumulation region was flat, and leakage current was reduced for the sample with BL.     

Negative capacitance peculiarities in a-Si:H/c-Si rectifier structure

Nontrivial negative capacitance (NC) effect, observed in a-Si:H/c-Si heterostructure devices, is discussed emphasizing the theoretical interpretation of experimental data. To explain NC effect, we have performed dark current voltage (I-V) and admittance measurements (C-V, G-V, C-f and G-f). The calculated values of series resistance (R_s) and barrier height (Φ_Bo) have the values from 100 to 114.7 Ω and 0.94 to 0.83 eV, respectively. Also, below 50% helium dilution rate, diode ideality factor (n) becomes bigger than 2, because tunneling at junction interface plays a major role. The measured room temperature (294 K) dark I-V result has been used during the fitting process for suggested capacitance model (Eq. (18)). The measured NC values exhibit strongly voltage depended behavior. This unexpected behavior is attributed to the presence of inductively coupled space charge region which might possibly be stemmed from the helium diluted a-Si:H material. It is seen that the measured NC values are well fitted with suggested capacitance model (Eq. (18)). Application of suggested correction formula on to experimental C-V data yields satisfactory results. It is shown that the calculated inductance values of the investigated device range from 10 to 42 μH and after correction, NC values are no longer observed in the C_d-V data.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

Series resistance calculation for Ag contacts on single crystal layered p-SnS and p-SnSe compound semiconductors in the wide temperature range

This paper summarizes the first results of characteristics parameters obtained from current-voltage (I-V) measurements for Ag/p-SnS and Ag/p-SnSe structure. The reverse and forward bias current-voltage characteristics of Ag Schottky contacts on a Bridgman-Stockbarger grown p-SnS and p-SnSe layered semiconducting material have been measured at various temperatures. We have tried to determine contact properties such as apparent barrier heights Φ_B0, ideality factor n and series resistance R_s. The apparent barrier height and ideality factor calculated by using thermionic emission theory were found to be strongly temperature dependent. Evaluating forward I-V data reveals a decrease at the apparent barrier height, but an increase at the ideality factor with decrease in temperature. It is shown that the values of R_s estimated from Cheung’s method were strongly temperature dependent and decreased with increasing temperature. It has been found that both contacts are of Schottky type.     

On the scaling issues and high-κ replacement of ultrathin gate dielectrics for nanoscale MOS transistors

According to the recent prediction made by the Semiconductor Industry Association (SIA) in International Technology Roadmap for Semiconductors (ITRS), the silicon technology will continue its historical rate of advancement with the Moore’s law for at least a couple of decades. With this trend, the silicon gate oxide will be scaled down to its physical limit in order to maintain proper control of the nanosize MOS transistors. This work reviews several critical issues of MOS gate dielectrics in the nanometer range.Although it was suggested that the conventional oxide can be scaled down, in principle, to two atomic layers of about 7 Å, this is not practically feasible because of the non-scalabilities of interface, trap capture cross-section, leakage current, and the statistical parameters of fabrication processes. Introducing a high-κ material can help solving most of the problems by using physically thicker high-κ gate dielectric films but several other reliability problems of the MOS devices rises. Being used in the extreme fine structure, the requirements for the material properties of the new high-κ are very stringent. Unfortunately, most of the high-κ materials are ionic metal oxides. This fundamental physics results in several undesirable instability issues when interfacing with silicon and with the CMOS processes. Bulk type thin oxynitride/high-κ stack could be a good solution for the coming technology nodes.     

Exciton enhancement effect on the third harmonic generation in ZnS/CdSe quantum dot quantum well

Exciton enhancement effect on the third-order optical nonlinearities of a ZnS/CdSe quantum dot quantum well (QDQW) has been theoretically studied. The wave functions and eigenenergies of excitons in QDQW have been calculated under the effective-mass approximation. By solving a three-dimensional nonlinear Schrödinger equation and by means of compact density matrix method, the third-order nonlinear susceptibilities for third-harmonic generation (THG) have been calculated in a two energy levels model of QDQW. Firstly, we studied the size effect on THG in QDQW. Then we compared the value of THG with the case that only considering electron states. The results show that the THG is greatly enhanced when compared with the condition just considering electron states.     

The correlation of the electrical properties with electron irradiation and constant voltage stress for MIS devices based on high-k double layer (HfTiSiO:N and HfTiO:N) dielectrics

This paper describes the influence of e-beam irradiation and constant voltage stress on the electrical characteristics of metal-insulator-semiconductor structures, with double layer high-k dielectric stacks containing HfTiSiO:N and HfTiO:N ultra-thin (1 and 2 nm) films. The changes in the electrical properties were caused by charge trapping phenomena which is similar for e-beam irradiation and voltage stress cases. The current flow mechanism was analyzed on the basis of pre-breakdown, soft-breakdown and post-breakdown current-voltage (J-V) experiments. Based on α-V analysis (α=d[ln(J)]/d[ln(V)]) of the J-V characteristics, a non-ideal Schottky diode-like current mechanism with different parameters in various ranges of J-V characteristics is established, which limits the current flow in these structures independent of irradiation dose or magnitude of applied voltage during stress.     

Parallel angle resolved XPS investigations on 12 in. wafers for the study of W and WSix oxidation in air

Parallel angle resolved X-ray photoelectron spectroscopy (ARXPS) was used to study the oxidation of W and WSi_x thin films CVD-deposited on 12 in. silicon wafers. The thin films were exposed to air during defined periods of time. Immediately after layer deposition, the wafers were rapidly loaded in a vacuum carrier in order to measure various aspects of the oxidation kinetic by XPS. Angle resolved data were exploited to obtain accurate tungsten oxide thicknesses measurements and the results were compared with X-ray reflectometry (XRR). A precise in-depth evolution of the W oxidation kinetic, in term of oxidation velocity and bonding environment, was obtained. Non-destructive profiles of the first five nanometers of a WSi_x surface were extracted from Angle Resolved data. These profiles were compared to ToF-SIMS analysis, and we clearly show the presence of a stoichiometric silicon dioxide passive layer covering WSi_x silicide.