Investigation of the delamination mechanism of the thin film dielectric structure in flip chip packages

As the electronics industry continues its efforts in miniaturizing the integrated circuit (IC), an IC chip with copper/low-k stacked Back End of Line (BEoL) structures has been developed for reducing R-C delay in order to obtain high-speed signal communication. However, its reliability might become a concern owing to the considerably lower adhesive strength, as well as the greater coefficient of thermal expansion (CTE) of the low-k materials. In this paper, the global-local finite element method, specified boundary condition (SBC) method, is employed as a bridge to estimate the impact from package level to the deep submicron BEoL structure of the flip chip package. The results show that the defect in the stacking structure at the center of the silicon has a lower tendency to crack than that at the corner region. In addition, the higher underfill CTE shows the disadvantage of the defect.     

铜钼叠层基板的热学特性仿真研究

采用有限元方法,仿真研究了不同层数和材料厚度比的铜钼叠层基板对芯片散热特性的影响。结果表明,2层和3层的铜钼叠层材料均可以有效综合Cu高热导率和Mo低膨胀系数的优点。在相同铜钼总厚度比的情况下,相比于2层材料,3层材料可以实现更好的散热特性。对于1 mm的基板厚度,铜钼铜厚度比为0.2∶0.6∶0.2时可以同时实现较低的温度和热应力。通过调整基板结构参数,可以显著改变芯片的最高温度和最大热应力,满足不同封装领域的需求。     

铜互连应力模拟分析

建立了三维有限元模型,采用ABAQUS有限元分析软件,模拟计算了Cu互连系统中的热应力分布;通过改变通孔直径、铜线余量、层间介质等,对比分析了互连结构对热应力分布的影响。结果表明,互连应力在金属线中通孔正下方铜线顶端处存在极小值,应力和应力梯度在下层铜线互连顶端通孔两侧处存在极大值。应力和应力梯度随着通孔直径或层间介质材料介电常数的减小而下降,应力随铜线余量长度的减小而增大。双通孔结构相对于单通孔结构而言,靠近下层金属线末端的通孔附近应力较大,但应力梯度较小。     

曲折状CoFeSiB三明治薄膜及其巨磁阻抗效应

利用射频磁控溅射技术及MEMS技术,制备了曲折状三明治结构的CoFeSiB/Cu/CoFeSiB多层膜,在l～40 MHz频率下,研究了多层膜的纵向和横向巨磁阻抗效应以及相应的电阻、电抗变化率。结果表明:曲折状三明治结构多层膜的巨磁阻抗效应,比单层膜有较大的提高,纵向和横向最大GMI效应分别为12.2%和–18.6%。     

Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization

Integration of Cu with low k dielectrics provided solution to reduce both resistance-capacitance time delay and parasitic capacitance of BEOL interconnections for 130 nm and beyond technology node. The motivation of this work is to study and improve electrical and reliability performance of two-level Cu/CVD low k SiOCH metallization from the results of diffusion barrier deposition schemes. Barrier deposition schemes are (a) high-density-plasma 250 Å Ta; (b) surface treatment of forming gas followed by high-density-plasma 250 Å Ta and (c) bi-layer of 100 Å Ta(N)/150 Å Ta. In this work, we demonstrated the superior and competency of high-density-plasma Ta deposition for Cu/CVD low k metallization and achieved excellent electrical and reliability results. Wafers fabricated with high-density-plasma Ta barrier scheme resulted in the best electrical yields, >90% for testing vehicles of dense via chains (via size=200 nm) and interspersed comb structures (width/space=200 nm/200 nm). Dielectric breakdown strength of the interspersed comb structures obtained at electric field of 0.3 MV/cm was ∼4 MV/cm.     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

纯铜表面激光熔覆TiB2/Cu涂层的组织及导电性能

为了满足电磁导轨的使用要求,采用激光熔覆技术在纯铜表面通过预置粉的方式制备了不同成分TiB2/Cu涂层,用光学显微镜、扫描电镜和X射线衍射分析了涂层的微观结构及相组成。涂层由Cu和TiB2两相组成,当TiB2的质量分数分别为0.02,0.05和0.1时,涂层的显微硬度分别约为95HV0.1,105HV0.1和152HV0.1,电导率为22.9MS/m,20.4MS/m和16.4MS/m。涂层与基体呈良好冶金结合,无裂纹在,TiB2颗粒存在团聚现象,熔覆层组织为外延生长的柱状晶。结果表明,随着TiB2的含量增大,涂层显微硬度升高,涂层的电导率下降。     

Development of compatible wet-clean stripper for integration of CoWP metal cap in Cu/low-k interconnects

Implementation of CoWP metal caps into Cu/low-k integration schemes requires a wet stripper that not only gives efficient cleaning but also has good compatibility to CoWP and low-k dielectrics. This paper describes a novel non-fluoride CoWP compatible stripper, developed based on a systematic study of the effect of stripper components, i.e. solvent, corrosion inhibitor, and stripper pH. Electrochemical methods were used to characterize galvanic corrosion of the CoWP/Cu couple and to estimate CoWP etch rate. Our studies showed that a traditional fluoride stripper caused severe damage to CoWP capping layer. The new stripper achieved a good balance between cleaning efficiency and compatibility to CoWP and low-k dielectrics, and demonstrated significant advantages in electrical properties over the traditional fluoride stripper.     

曲折型三明治结构FeNi/Cu/FeNi多层膜巨磁阻抗效应研究

采用微机电系统(MEMS)技术在玻璃基片上制备了曲折型三明治结构FeNi/Cu/FeNi多层膜,在电流频率1～40 MHz范围内研究了FeNi/Cu/FeNi多层膜的巨磁阻抗(GMI)效应,并分别通过改变FeNi薄膜的宽度、厚度和Cu薄膜的宽度,研究了尺寸对巨磁阻抗效应的影响,当磁场Ha施加在薄膜的纵轴时,巨磁阻抗变化...     

Ti/Ag/Cu活性焊料的封接特性

Ti／Ag／Cu活性焊料法广泛应用于陶瓷与金属的焊接中，但该焊料在陶瓷表面的浸润性较差，在金属表面易发生偏析的现象。本文对该焊料的流散特性进行了讨论，对陶瓷与金属的封接界面进行了分析，对封接机理进行了讨论，结果表明在封接界面生成Ti的氧化物主要是TiO2。     

Reliability of In-48Sn solder/Au/Ni/Cu BGA packages during reflow process

The interfacial reactions and shear properties of In-48wt.%Sn/Au/Ni/Cu solder joints were investigated in terms of reflow conditions, i.e., reflow temperature and duration time. The thickness of an AuIn₂ intermetallic compound (IMC) layer, formed at the solder/substrate interface, slightly increased with the duration time. The spalling of the AuIn₂ intermetallics in the solder led to the formation of a Ni₃(Sn,In)₄ IMC layer between the solder and exposed Ni layer. The longer duration time resulted in the spalling and grain growth of Ni₃(Sn,In)₄ intermetallics. The higher reflow temperature accelerated the interfacial reactions between the solder and substrate. From the ball shear test results, the formation and growth of a continuous plate-shaped AuIn₂ IMC layer increased the shear force of the solder joints, whereas the spalling and grain growth of cubic-shaped AuIn₂ intermetallics significantly decreased the shear force. The formation and spalling of cubic-shaped Ni₃(Sn,In)₄ intermetallics increased the shear force, whereas the spalling and grain growth of polyhedron-shaped Ni₃(Sn,In)₄ intermetallics decreased the shear force. The crack propagated at the Au-rich/AuIn₂/solder interface in the initial reflow stage, then toward the AuIn₂ intermetallics dispersed in the solder matrix, and finally along the Ni₃(Sn,In)₄ intermetallics spalling off in the solder.     

Cr/Cu/Al/Cr薄膜电极的防氧化性能

采用Al作为Cu导电层的主要防氧化保护层,在普通浮法玻璃上利用磁控溅射和湿法刻蚀技术制备Cr/Cu/Al/Cr复合薄膜及其电极,研究不同的热处理温度对复合薄膜及其电极的结构、表面形貌和导电性能的影响。由于有Al层作为保护层,在热处理过程中,Al先与穿过Cr保护层的氧进行反应,从而可以更有效地保护Cu膜层在较高的温度下不被氧化,所制备的薄膜在经过600℃的热处理之后仍然具有较好的导电性能。而对于Cr/Cu/Al/Cr电极,侧面裸露的金属层在热处理过程中的氧化是其导电性能逐渐下降的主要原因,退火温度超过500℃之后,电极侧面裸露部分的氧化范围不断往电极的中间扩散,导致了薄膜电极导电性能显著恶化。虽然如此,Cr/Cu/Al/Cr薄膜电极在430℃附近仍然具有较好的导电性能,电阻率为7.3×10-8Ω.m,符合FED薄膜电极的要求。以此薄膜电极构建FED显示屏,通过发光亮度均匀性的测试验证了Cr/Cu/Al/Cr电极的抗氧化性。     

铜钼化合物氢还原制备铜钼复合粉研究

通过对铜钼化合物氢还原过程进行热力学分析,找到了制备均匀细颗粒铜钼复合粉的热力学途径。设计了封闭还原系统,用此系统进行氢气热还原,不仅使氢气得到充分利用,而且容易判断反应终点。通过系统内的特殊装置除水,降低了还原温度,在650℃下还原得到了混合均匀的铜钼复合粉。系统能彻底快速除去反应生成的水分,使反应物的湿度大大降低,确保能得到细颗粒的铜钼复合粉,其平均粒径小于70nm。     

铜互连线内电流拥挤效应的影响

提出了一种新的测试结构(S结构),通过实验、理论推导和有限元分析,研究了铜与TaN扩散阻挡层界面的电流拥挤效应对电迁移致质量输运特性的影响.实验和有限元分析表明,铜互连线内由于电流拥挤效应的存在,在用户温度下沿特定通道输运的局部原子通量显著增大,而焦耳热所产生的温度梯度对原子通量和通量散度增大的影响则相对有限.     

Cu引线框架氧化对功率器件中Cu/EMC界面的影响

按照实际制作器件的工艺条件和方法,采用不同的Cu引线框架氧化时间,制备了多组无芯片的封装器件,并打磨Cu/EMC界面的样品。然后对样品进行了剪切实验和界面微观结构观察。剪切实验发现,适当的Cu预氧化时间能有效提高Cu/EMC界面强度。Cu/EMC界面的SEM照片显示,150 min的氧化时间使界面产生了大量不同形状的氧化物颗粒,断裂沿Cu氧化层或EMC过渡层发生,导致界面剪切强度离散。考虑到Cu氧化对Cu/EMC界面的影响及工艺成本,氧化时间范围为165℃下8~12 min。     

Isothermal solidification of Cu/Sn diffusion couples to form thin-solder joints

Isothermal solidification of conventional Cu/Sn diffusional couples was performed to form thin (30 μm) joints consisting of Cu-Sn intermetallics. During initial stages of isothermal solidification, both Cu₆Sn₅ and Cu₃Sn phases grow, even though the former is the dominant. After consumption of all available Sn, the Cu₃Sn phase grows reactively at the expense of Cu and Cu₆Sn₅. Finally, we obtain solder joints that consist of only Cu₃Sn. Indentation fracture-toughness measurements show that Cu₃Sn is superior to Cu₆Sn₅. Furthermore, indentations of Cu₃Sn exhibit the presence of shear bands, which are not observed in Cu₆Sn₅, implying that the former is more ductile than the latter. Ductile intermetallic-based joints formed by isothermal solidification are promising candidates to form thin (as thin as 5–10 μm or less) solder joints, as they are thermally and thermodynamically stable compared to conventional solder joints. Excess copper in the interconnect provides ductility to the interconnect.     

AA6061铝基材上激光熔覆Cu／Cr合金层的研究

在易氧化的纯AI表面制备Cu/Ar合金熔覆层,因二者的熔点温度差别大且容易结合过渡区产生脆性裂纹而有一定难度。本文通过扫描电镜（SEM）分析研究了激光工艺参数对Cu/Ar熔覆层过渡区裂纹倾向的影响。实验结果表明,以1．06μm波长的Nd:YAG激光器的聚焦光束为热源,通过选择合适的激光工艺参数,可获得理想的Cu/Ar合金熔覆层,这对于改进铝材表面的物理、化学性能并进一步开发其作为电接触材料具有应用价值。     

不同WC含量下WC/Cu复合材料弹性模量实验研究

为了研究数字图像相关方法运用于小试样下WC/Cu复合材料弹性模量测定的准确性,采用粉末冶金法制备出了WC含量不同的WC/Cu复合材料,对试件表面用白漆配合碳粉方法进行制斑,并在万能材料试验机上进行拉伸实验,用CCD相机记录其散斑图。对记录的散斑图进行相关运算,并通过畸变校正理论校正位移计算结果,计算出小应变范围内WC/Cu复合材料的应力应变曲线,得到弹性模量;与传统电测方法结果进行对比,数据吻合较好。结果表明,采用数字图像相关方法和小试件制斑方法运用于WC/Cu复合材料弹性模量的测定是较为精确可靠的。     

电子封装用SiC_p／Cu复合材料制备与性能

采用挤压铸造方法制备了体积分数为55％、不同颗粒粒径增强的电子封装用SiCp／Cu复合材料,并分析了颗粒尺寸和热处理状态对材料物理性能和力学性能的影响规律。显微组织观察表明SiC颗粒分布均匀,复合材料组织致密;随着SiC颗粒尺寸的减小,复合材料的平均线膨胀系数和热导率均降低;退火处理可以降低复合材料的热膨胀系数,同时提高材料的热导率。复合材料具有高的弯曲强度和弹性模量,退火处理后材料的弯曲强度降低,但弹性模量变化不大。     

Cu/Ta/SiO_2/Si多层膜纳米压痕与压痕下微观结构的研究

Cu/Ta/SiO2/Si多层膜结构是目前集成电路制造工艺中的常见结构,其硬度与弹性模量通过纳米压入技术测得。为了表征纳米压痕下的形变微观区域,采用聚焦离子束加工出压痕截面,同时进行扫描电子、扫描离子显微观察,发现样品衬底发生开裂,多层膜结构出现分层现象。TEM分析表明分层出现在Ta/SiO2界面,说明这是该结构的一个薄弱环节。