Charging simulations in nanocrystal quantum flash memories

The comprehension of the charging of a floating gate composed of nanocrystals (NCs) in a non-volatile flash memory is a real challenge. A few electrons tunnel from the channel of a metal-oxide-semiconductor transistor into the two-dimensional array of nanocrystals.A realistic three-dimensional model is proposed for electron tunneling into the floating gate. The energy subbands of the channel are explicitly included, together with the doping density. The model is solved thanks to a finite element method.Therefore many simulations can be carried out to better understand the relation between the tunneling times for charging a single NC, or the whole NC floating gate, and the geometrical parameters for example. Moreover a detailed statistical study concerning the dispersion of the relevant parameters can be led, helping the experimentalists to determine the optimal operating conditions of quantum flash memories.     

Silicon nanocrystal non-volatile memory for embedded memory scaling

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.     

Multi-gate non-volatile memories with nanowires as charge storage material

Multi-gate non-volatile memory (NVM) cell is a promising approach in the next generation. In this work, the performance of NVMs using nanocrystals (NCs) and nanowires (NWs) as charge trapping materials were evaluated by three-dimensional simulation. It is found that the NWs located at different positions have different charge injection speeds. And the NW density will strongly affect the charge injection efficiency. The NW at channel center can result in large memory window and acceptable channel controllability. Although the total charges injected into NWs is lower than that injected into NCs under the same programming condition, using NWs as charge trapping material exhibits larger memory window and better channel controllability. It is suggested that the NW is a better choice than NC to be charge storage material from the perspective of memory performance.     

Si and Ge nanocrystals for future memory devices

An attractive alternative for extending the scaling of Flash-type memories is to replace the conventional floating gate (a poly-Si layer) by laterally isolated floating nodes in the form of nanoparticles. This floating-gate concept has led to the emergence of the so-called nanocrystal (NC) memories which have the potential of operating at lower voltages and higher speeds compared to the conventional non-volatile memories (NVMs) without compromising the criterion of non-volatility. NC memories also offer other advantages like a better immunity to the crosstalk effect arising from the floating-gate coupling of closely spaced adjacent cells and an increased design flexibility from which quantum confinement phenomena can be judiciously exploited for enhanced memory functionality. Among the different technological routes explored in the last few years for generating nanocrystals in the gate insulator of MOS devices, two major techniques have been utilized, namely deposition in vacuum and ion beam synthesis. During the last decade, we have extensively explored the ultra-low-energy ion-beam-synthesis (ULE-IBS) technique to produce single planes of Si-NCs in very thin (5–10 nm) insulator layers. This review summarizes more than 10 years of research efforts we and other groups have dedicated to the fabrication of NCs memories using this original technique. By exploiting the flexibility of the ULE-IBS route, Si-NCs single-transistor NVM cells using “classical” gate oxides (SiO₂) have been successfully realized. More recently, advanced dielectric stacks employing high-κ dielectric (HfO₂) as tunnel oxide and SiN as control oxide and host matrix for Si and Ge-NCs, have been fabricated and show promising performance for low-voltage operating-NVM devices. Particular emphasis is placed herein on material science issues such as anomalous and controlled oxidation processes. While much research is still needed for making reliable and competitive NC NVMs, our systematic investigations based on the ULE-IBS option demonstrate that a tight control and understanding of the properties of NCs memory cells can be achieved, provided that deep structural characterization is coupled to electrical studies.     

包含双层半导体和金属纳米晶MOS电容的存储特性

制备了包含双层半导体和金属纳米晶的MOS电容结构,研究了其在非挥发性存储器领域的应用。利用真空电子束蒸发技术,在二氧化硅介质中得到了半导体硅纳米晶和金属镍纳米晶。与包含单层纳米晶的MOS电容相比,这种包含双层异质纳米晶的MOS电容显示出更大的存储能力,且保留性能得到改善。说明顶层的金属纳米晶作为一层额外的电荷俘获层可以通过直接隧穿机制进一步延长保留时间和提高平带电压漂移量。     

Memory characteristics of an MOS capacitor structure with double-layer semiconductor and metal heterogeneous nanocrystals

An MOS (metal oxide semiconductor) capacitor structure with double-layer heterogeneous nanocrystals consisting of semiconductor and metal embedded in a gate oxide for nonvolatile memory applications has been fabricated and characterized. By combining vacuum electron-beam co-evaporated Si nanocrystals and self-assembled Ni nanocrystals in a SiO_2 matrix, an MOS capacitor with double-layer heterogeneous nanocrystals can have larger charge storage capacity and improved retention characteristics compared to one with single-layer nanocrystals. The upper metal nanocrystals as an additional charge trap layer enable the direct tunneling mechanism to enhance the flat voltage shift and prolong the retention time.     

纳米晶浮栅存储器的模拟、制备和电学特性

介绍了在纳米晶浮栅存储器数据保持特性方面的研究工作,重点介绍了纳米晶材料的选择与制备和遂穿介质层工程。研究证明,金属纳米晶浮栅存储器比半导体纳米晶浮栅存储器具有更好的电荷保持特性。并且金属纳米晶制备方法简单,通过电子束蒸发热退火的方法就能够得到质量较好的金属纳米晶,密度约4×1011cm-2,纳米晶尺寸约6～7nm。实验证明,高介电常数隧穿介质能够明显改善浮栅存储器的电荷保持特性,所以在引入金属纳米晶和高介电常数遂穿介质之后,纳米晶浮栅存储器可能成为下一代非挥发性存储器的候选者。     

Performance improvement of flash memory using AlN as charge-trapping Layer

Potential of high-k dielectric films for future scaled charge storage non-volatile memory (NVM) device applications is discussed. To overcome the problems of charge loss encountered in conventional flash memories with silicon-nitride (Si₃N₄) films and polysilicon-oxide-nitride-oxide-silicon (SONOS) and nonuniformity issues in nanocrystal memories (NC), such as Si, Ge and metal, it is shown that the use of high-k dielectrics allows more aggressive scaling of the tunnel dielectric, smaller operating voltage, better endurance, and faster program/erase speeds. Charge-trapping characteristics of high-k AlN films with SiO₂ as a blocking oxide in p-Si/SiO₂/AlN/SiO₂/poly-silicon (SOHOS) memory structures have been investigated in detail. The experimental results of program/erase characteristics obtained as the functions of gate bias voltage and pulse width are presented.     

Implementation of Six Bit ADC and DAC Using Quantum Dot Gate Non-Volatile Memory

This paper presents the implementation of six-bit analog to digital converters (ADCs) and digital-to-analog converters (DACs) using quantum dot gate non-volatile memory (QDNVM). The charge accumulation in the gate region varies the threshold voltage of QDNVM which can be used as a reference voltage source in a comparator circuit. A simplified comparator circuit can be implemented using the quantum dot gate non-volatile memory (QDNVM). In this work, we discuss the use of QDNVM based comparators in designing 6-bit Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs).     

Organic small-molecule heterointerface for use in transistor-type non-volatile memory

A chargeable layer is an essential element for charge transfer and trapping in a transistor-based non-volatile memory device. Here we demonstrate that a heterointerface layer comprising of two different small molecules can show electrical memory characteristics. The organic heterointerface layer was fabricated with a pentacene and tris(8-hydroxyquinoline) aluminum (Alq3) layers by sequential vapor deposition without breaking the vacuum state. Pentacene was adopted as the active layer on the top, and Alq3 was used as the bottom layer for charge trapping. The bottom-gate top-contact transistor with an organic heterointerface layer showed distinct non-volatile memory behaviors and showed high air stability and reliability. We investigated the energy structure of the pentacene/Alq3 heterointerface layer to reveal the operation mechanism of the non-volatile memory and suggested that the writing/erasing gate bias-dependent energy barrier originating from the difference between the energy levels of the pentacene and Alq3 layers controls the charge transfer at the heterointerface layer. Our approach suggests a simple way to fabricate heterointerface layers for organic non-volatile memory applications with high air stability and reliability.     

Reliability issues of offset drain transistors after different modes of static electrical stress

The reliability issues of Offset Drain Transistors (ODT's) after different modes of static electrical stress (high voltage uniform gate stress, high voltage drain stress and hot carrier stress) are presented. Besides, the evolution of the macroscopic electrical parameters of these devices after high voltage uniform gate stress, has been attributed quantitatively to the evolution of the bulk gate oxide trapping characteristics and the variation of the Si/SiO₂ interface state charge. Furthermore, qualification of these devices for application in non-volatile memory arrays as bit select transistor has been conducted.     

Nonvolatile memory with a metal nanocrystal/nitride heterogeneous floating-gate

Heterogeneous floating-gates consisting of metal nanocrystals and silicon nitride (Si/sub 3/N/sub 4/) for nonvolatile memory applications have been fabricated and characterized. By combining the self-assembled Au nanocrystals and plasma-enhanced chemical vapor deposition (PECVD) nitride layer, the heterogeneous-stack devices can achieve enhanced retention, endurance, and low-voltage program/erase characteristics over single-layer nanocrystals or nitride floating-gate memories. The metal nanocrystals at the lower stack enable the direct tunneling mechanism during program/erase to achieve low-voltage operation and good endurance, while the nitride layer at the upper stack works as an additional charge trap layer to enlarge the memory window and significantly improve the retention time. The write/erase time of the heterogeneous stack is almost the same as that of the single-layer metal nanocrystals. In addition, we could further enhance the memory window by stacking more nanocrystal/nitride heterogeneous layers, as long as the effective oxide thickness from the control gate is still within reasonable ranges to control the short channel effects.     

UV assisted non-volatile memory behaviour using Copper (II) phthalocyanine based organic field-effect transistors

In this report, we have demonstrated the optical non-volatile memory characteristics using CuPc OFET. The memory operation was comprehensively demonstrated with different programming conditions. It was found that the programming of CuPc OFET with an electric pulse at the gate terminal under UV-light photo-illumination compared to other programming conditions, could substantially increase the memory window due to massive charge trapping in the polymer electret layer, which causes shift in the device transfer characteristics from low-conduction state (“OFF state”, or logic 0) to high conduction state (“ON state”, or logic 1) at V_GS = 0V. From device operation at −50V, a memory window of greater than 45V could be achieved by applying a programming voltage of +70 V at the gate terminal under UV-light photo-illumination. Moreover, it was completely erased by applying −100 V at the gate terminal in dark.     

Electrical characteristics of nano-crystal Si particles for nano-floating gate memory

In these days, the researches of non-volatile memory device using nano-crystal(NC)-Si are actively progressing to replace flash memory devices. Many kinds of non-volatile memory devices such as phase-change(P)-RAM, resistance(Re)-RAM, polymer(Po)-RAM, and nano-floating gate memory(NFGM) are being studied. In this work, we study NFGM device in which information is memorized by storing electrons in silicon nanocrystal. The NFGM device has shown great promise for ultra-dense high-endurance memory device for low-power applications [S. Tiwari, et al., Appl. Phys. Lett. 68 (1996) 1377], and it is able to fabricate 1T-type device. Thus, the NFGM is considered to replace existing flash memory device. Non-volatile memory device has been fabricated by using NC-Si particles. The NC-Si particles have broad size range of 1-5 nm and an average size of 2.7 nm, which are sufficiently small to indicate the quantum effect for silicon. The memory window has been analyzed by C-V characteristic of NC-Si particles. V_d-I_d and V_g-I_d characteristics of the fabricated device have also been measured.     

Flexible and transparent nanocrystal floating gate memory devices using silk protein

The charge storage behavior of a floating gate memory device using carbon nanotube-CdS nanostructures embedded in Bombyx mori silk protein matrix has been demonstrated. The capacitance – voltage characteristics in ITO/CNT–CdS-silk composite/Al device exhibits a clockwise hysteresis behavior due to the injection and storage of holes in the quantized valence band energy levels of CdS nanocrystals. The enhanced charge injection resulting in increase in memory window is observed at higher sweeping voltages. Nearly frequency independent hysteresis width over a wide range of 100 kHz–2.0 MHz, indicates its origin due to the charge storage in nanocrystals. The memory behavior of carbon nanotube–CdS nanostructures/silk nanocomposite devices has also been demonstrated on polyethylene terephthalate substrates, which may provide the way for flexible, transparent and printable electronic devices.     

N-type polymeric organic flash memory device: Effect of reduced graphene oxide floating gate

In this paper, n type nonvolatile memory devices were fabricated by implanting a bilayer (rGO sheets/Au NP) floating gates, using n-type polymer semiconductor, poly {[N, N′ bis (2octyldodecyl) - naphthalene-1, 4, 5, 8 - bis (dicarboximide)-2,6-diyl] – alt - 5,5′ - (2, 2′ bithiophene)} [P(NDI2OD-T2)n]. In the developed organic field effect transistor memory devices, electrons are trapped/detrapped in rGO sheet/Au NP's nano-floating gates by controlling the charge carrier density in the active layer through back gate bias control. The devices showed interesting non-volatile memory properties with a large memory window of ∼34 V, a programming-reading-erasing cycling endurance of 103 times and most importantly, an improved retention time characteristics estimated by extrapolation (longer than the technological requirement of commercial memory devices (>10 years)). This approach provides a great potential for fabricating high-performances organic nano-floating gate memory devices and opens up a new way for the development of next-generation non-volatile memory devices.     

Electrically-alterable memory using a dual electron injector structure

A novel type of electrically-alterable memory which uses the phenomenon of enhanced electron injection into SiO2from Si-rich SiO2to charge or discharge a floating polycrystalline Si storage layer in a metal-oxide-semiconductor field-effect-transistor is described. This non-volatile memory differs from others using floating polycrystalline Si in the charging or discharging process. This improvement is accomplished by using a chemically-vapor-deposited stack of Si-rich-SiO2-SiO2-Si-rich-SiO2between the floating polycrystalline Si layer and the control gate electrode. This device is capable of being written or erased in 5 msec at voltages of ≤ 16 V and in 2 µsec at voltages ≤ 23 V with excellent charge retention.     

A three charge-states model for silicon nanocrystals nonvolatile memories

In the field of nonvolatile memories, substantial improvement of reliability is obtained by replacing the continuous polysilicon floating gate by a planar distribution of silicon nanocrystals, each acting as a storage node. The test devices in the present paper are MOS capacitors containing a two-dimensional layer of nanocrystals located 2.5 nm away from the oxide/substrate interface, inside the SiO/sub 2/. This work presents various measurements of the charge current versus either bias voltage or time. On the other side, the charge and discharge dynamics of the nanocrystals had already been described by De Salvo using a model borrowed from the conventional floating-gate memory. We show this approach to be not completely suitable to explain the experimental observations. Thus, we describe and apply a so-called granular model, based on a mono-electronic principle limited by Coulomb blockade, in which electrons interact with the nanocrystals one by one. Omitting the reality of such a one-by-one principle may involve important mistakes in the interpretation of phenomena.     

Overcoming the “retention vs. voltage” trade-off in nonvolatile organic memory: Ag nanoparticles covered with dipolar self-assembled monolayers as robust charge storage nodes

Organic non-volatile memory devices with significantly enhanced retention are explored with C₆₀ thin-film transistors containing silver nanoparticles (Ag-NPs) within gate dielectrics as charge storage nodes. Dipolar self-assembled monolayers covering Ag-NPs effectively prevent stored charges from being lost by providing an additional energy threshold for back-tunneling process. This enables long retention even with ultrathin tunneling dielectric layers, providing a simple means to realize long retention without causing an excessive increase in operation voltage.     

有机非挥发存储器件:浮栅结构有机薄膜晶体管

提出了一种浮栅结构的新型有机薄膜晶体管(FG-OTFT)器件,并阐述了这种器件的工作机理.该器件通过控制浮 置栅上的电荷来控制 FG-OTFT 器件的阈值电压的大小,而器件不同的阈值电压便可用来存储“0”和“1”两个状态,故这种器 件可以被用作有机非挥发存储器.我们通过计算机数值模拟的方法对这种器件进行了研究.研究表明...