Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

The effect of light irradiation on electrons and holes trapping in nonvolotile memory capacitors employing sub 10 nm SiO2-HfO2 stacks and Au nanocrystals

We demonstrate the possibility to control charge trapping in the memory stacks comprised of metal nanocrystals (NCs) sandwiched between SiO₂ and high-k dielectric films by light irradiation. Non-equilibrium depletion effects in the state of the art charge trapping memories are reported for the first time. The studied nonvolatile memory devices employ Au NCs, thermal SiO₂ tunnel layer, atomic layer deposited HfO₂ blocking layer and Au/Pt metal gate. The memory windows are 3 V and 10.5 in the dark and under illumination for ±10 V programming voltages. Reliability limitations of the studied structure, in particular leakage currents and effects in high electric fields have been investigated in detail and are discussed in view of the mentioned device application. Low programming voltages and currents, and high light sensitivity make suggested NVM structures promising for developing digital imagers with ultra-low power consumption.     

Role of tunneling layer in graphene-oxide based organic nonvolatile memory transistors

This paper demonstrates non-volatile memory transistor using solution processable graphene oxide (GO) as charge storage nodes in the configuration, p⁺⁺Si/SiO₂/GO/Tunneling layer/Pentacene/Au. The tunneling layers are polymethylmethacrylate (PMMA) and polyvinylphenol (PVP). GO film could be deposited as single layered flakes with a uniform distribution using spin coating technique. The devices with PMMA as charge tunneling layer exhibited higher mobility and on/off ratio than PVP based devices. The devices show a large positive threshold voltage shift (∼24 V for PMMA and ∼15 V for PVP) from initial value during programming at gate voltage of +80 V kept for 10 s. The transfer curves can be restored approximately to its initial condition by applying an erasing voltage of −30 V for 10 s for both the devices. Since such a large shift is not observed without GO layer, we consider that memory effect was due to electron trapping in GO. Further, retention of the initial memory window was measured to be 63% and 37% after 3000 s for PMMA and PVP based devices, respectively.     

Organic nonvolatile memory transistors based on fullerene and an electron-trapping polymer

We report for the first time organic n-type nonvolatile memory transistors based on a fullerene (C₆₀) semiconductor and an electron-trapping polymer, poly(perfluoroalkenyl vinyl ether) (CYTOP). The transistors with a Si++/SiO₂/CYTOP/C₆₀/Al structure show good n-type transistor performance with a threshold voltage (V_th) of 2.8 V and an electron mobility of 0.4 cm² V⁻¹ s⁻¹. Applying gate voltages of 50 or −45 V for about 0.1 s to the devices induces the reversible shifts in their transfer characteristics, which results in a large memory window (ΔV_th) of 10 V. A memory on/off ratio of 10⁵ at a small reading voltage below 5 V and a retention time greater than 10⁵ s are achieved. The memory effect in the transistor is ascribed to electrons trapped at the CYTOP/SiO₂ interface. Because of the use of high-electron-mobility C₆₀, the switching voltages of our memory transistors become significantly lower than those of conventional memory transistors based on pentacene.     

Morphology control of tunneling dielectric towards high-performance organic field-effect transistor nonvolatile memory

We report high-performance organic field-effect transistor nonvolatile memory based on nano-floating-gate, which shows a large memory window of about 70 V, high ON/OFF ratio of reading current over 10⁵ after 1 week storage, high field-effect mobility of 0.6 cm²/V s, and good programming/erasing/reading endurance. The devices incorporate Au nanoparticles and polystyrene layer on top to form the nano-floating-gate, and we demonstrate that the morphology control of the tunneling dielectric is critically significant to improve the memory performance. The optimized tunneling dielectric morphology is favorable to the efficient charge tunneling, reliable charge storage and high-quality organic film growth.     

Nonvolatile memory characteristics of metallic nanodots as charge-storage nodes

The charge and discharge properties of NiSi nanodots in the gate oxide of MOS and MOSFET devices were investigated in order to utilize as the charge-storage nodes in a nonvolatile floating-gate memory. NiSi nanodots were formed by sputtering Ni and successive exposing to SiH₄ gas. The memory characteristics of MOS and MOSFET devices which contain the NiSi nanodots in the gate oxide were obtained through the capacitance-voltage measurements and the transient threshold voltage shift measurements. The window of threshold voltage shift was achieved to be 2.5 V when the gate bias voltages of ±20 V were applied for 1 s and 500 ms, respectively. The retention time of MOSFET memory-cell was estimated to be about 10 years.     

Memory characteristics of MOSFET with silicon nanoclusters formed using a pulse-type gas-feeding technique in the LPCVD system

The digital gas-feeding method was used in this study, with Si₂H₆ as the source gas, in a low-pressure chemical-vapor deposition system, to grow Si nanoclusters with high densities and uniform sizes. The densities of the Si nanoclusters rose to 7 × 10¹¹ cm⁻², and their sizes slightly changed at about 7 nm based on the frequency of gas-pulse feeding in the digital process. MOSFETs containing Si nanoclusters as a floating gate in the gate stack were fabricated, and the various nonvolatile-memory characteristics of MOSFET were investigated. The total threshold voltage shift of 3.7 V was achieved, and the program/erase times were found to be 5 μs/50 ms when the program/erase voltages were +18/−20 V, respectively. The charge-storage memory window was extrapolated over 1 year to be 1.5 V in the retention measurements of the fabricated Si nanocluster floating-gate memory device.     

Low power resistive switching memory using Cu metallic filament in Ge0.2Se0.8 solid-electrolyte

Bipolar resistive switching memory device using Cu metallic filament in Au/Cu/Ge_0.2Se_0.8/W memory device structure has been investigated. This resistive memory device has the suitable threshold voltage of V_th > 0.18 V, good resistance ratio (R_High/R_Low) of 2.6 × 10³, good endurance of >10⁴ cycles with a programming current of 0.3 mA/0.8 mA, and 5 h of retention time at low compliance current of 10 nA. The low resistance state (R_Low) of the memory device decreases with increasing the compliance current from 1 nA to 500 μA for different device sizes from 0.2 μm to 4 μm. The memory device can work at very low compliance current of 1 nA, which can be applicable for extremely low power-consuming memory devices.     

BE-SONOS flash memory along with metal gate and high-k dielectrics in tunnel barrier and its impact on charge retention dynamics

We investigate the effect of a high-k dielectric in the tunnel layer to improve the erase speed-retention trade-off. Here, the proposed stack in the tunnel layer is AlLaO₃/HfAlO/SiO₂. These proposed materials possess low valence band offset with high permittivity to improve both the erase speed and retention time in barrier engineered silicon-oxide-nitride-oxide-silicon(BE-SONOS). In the proposed structure HfAlO and AlLaO₃ replace Si₃N₄ and the top SiO₂ layer in a conventional oxide/nitride/oxide(ONO) tunnel stack. Due to the lower conduction band offset(CBO) and high permittivity of the proposed material in the tunnel layer, it offers better program/erase(P/E) speed and retention time. In this work the gate length is also scaled down from 220 to 55 nm to observe the effect of high-k materials while scaling, for the same equivalent oxide thickness(EOT). We found that the scaling down of the gate length has a negligible impact on the memory window of the devices. Hence, various investigated tunnel oxide stacks possess a good memory window with a charge retained up to 87.4%(at room temperature) after a period of ten years. We also examine the use of a metal gate instead of a polysilicon gate, which shows improved P/E speed and retention time.     

Characteristics of metal-ferroelectric-insulator-semiconductor structure using Sr0.8Bi2.2Ta2O9 and Sr0.8Bi2.2Ta2O9-BaZrO3 for ferroelectric gates

Characteristics of BaZrO₃ (BZO) modified Sr_0.8Bi_2.2Ta₂O₉ (SBT) thin films fabricated by sol-gel method on HfO₂ coated Si substrates have been investigated in a metal-ferroelectric-insulator-semiconductor (MFIS) structure for potential use in a ferroelectric field effect transistor (FeFET) type memory. MFIS structures consisting of pure SBT and doped with 5 and 7 mol% BZO exhibited memory windows of 0.81, 0.82 and 0.95 V with gate voltage sweeps between −5 and +5 V, respectively. Leakage current density levels of 10⁻⁸ A/cm² for BZO doped SBT gate materials were observed and attributed to the metallic Bi on the surface as well as intrinsic defects and a porous film microstructure. The higher than expected leakage current is attributed to electron trapping/de-trapping, which reduces the data retention time and memory window. Further process improvements are expected to enhance the electronic properties of doped SBT for FeFET.     

Electronic properties of GST for non-volatile memory

Impacts of annealing temperature and film thickness to the resistivity of Ge₂Sb₂Te₅(GST) have been studied. The resistivity of GST drops when the annealing temperature reaches 180 °C, rises above 360 °C and the thicker film crystallized more easily. Electronic device of phase change memory also has been fabricated with metal sidewall technology using 5 μm lithographic technology. The device was successfully programmed by 100 ns of 5 V pulse for SET and 10 ns of 10 V pulse for RESET. More than 100 times on/off ratio has been reached.     

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10¹⁹ cm⁻³ doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10¹¹ cm⁻² and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy)_xO_y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10⁻⁷ A/cm². We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.     

Lowering programmed voltage of organic memory transistors based on polymer gate electrets through heterojunction fabrication

The authors report on low operation voltage memory cells based on heterojunction ambipolar organic transistors with polymer gate electret (PGE). The introduction of the N,N′-dioctyl perylene diimide/pentacene heterojunction into the memory OFETs with PGE successfully lowered the memory cells’ reading, writing and erasing programmed voltages (reading voltage of 2 V, writing and erasing programmed voltages of 10 V). Meanwhile, the memory devices showed reproducible and durable memory behavior in more than 500 cycles’ testing. The built-in electric field-effect at heterojunction surface should efficiently reduce operation voltage of the memory devices.     

Effects of incorporation of copper sulfide nanocrystals on the performance of P3HT: PCBM based inverted solar cells

It has been reported that performance of bulk heterojunction organic solar cells can be improved by incorporation of an additive like metal and semiconducting nanoparticles in the active layer. Here in, we have synthesized Cu₂S nanocrystals (NCs) by chemical route and studied its dispersion in poly (3-hexylthiophene) [6, 6]-phenyl C61-butyric acid methyl ester (P3HT: PCBM) matrix. Variation in the performance parameters with change in the concentration of Cu₂S NCs into the P3HT: PCBM matrix has also been studied and it was found that the inverted geometry device with concentration of 20 wt% of Cu₂S NCs and having the structure ITO/ZnO (NPs)/P3HT: PCBM:Cu₂S NCs/MoO₃/Al has shown maximum efficiency of 3.39% which is more than 100% increase in comparison with devices without Cu₂S NCs. Photoluminescence measurements studies unveiled that the incorporation of Cu₂S NCs into a P3HT: PCBM matrix has helped in quenching photoluminescence which suggests more effective exciton dissociation at the interfaces between the P3HT and PCBM domains. The Nyquist plots obtained from impedance spectroscopy at 1 V bias in the dark has suggested the effective lifetime and global mobilities for P3HT: PCBM as 0.267 ms and 1.17 × 10⁻³ cm²/V-S and for P3HT: PCBM:Cu₂S NCs (20 wt%) systems as 0.156 ms and 2.02 × 10⁻³ cm²/V-S respectively. Based on observed photoluminescence quenching, calculated effective lifetime and global mobility, we have tried to explain the possible reason for improvement in the efficiency with the very well dispersion of Cu₂S NCs into the P3HT: PCBM matrix.     

Si-nanoclusters embedded into epitaxial rare earth oxides: Potential candidate for nonvolatile memory applications

Using an unconventional approach, single crystalline Si-nanoclusters (Si-NCs) with uniform size and higher density were embedded into epitaxial rare earth oxide with two-dimensional spatial arrangements at a defined distance from the substrate using solid source molecular beam epitaxy (MBE) technique.The incorporated Si-NCs with average size of 5 nm and density of 2 × 10¹² cm⁻² exhibit charge storage capacity with promising retention (∼10⁷ s) and endurance (10⁵ write/erase cycles) characteristics. The Pt/Gd₂O₃ (Si-NC)/Si (MOS) basic memory cells with embedded Si-nanoclusters display large programming window (∼1.5-2 V) and fast writing speed. With such properties demonstrated, we believe that the Si-NCs embedded in epitaxial Gd₂O₃ could be potential candidate for high density nonvolatile memory devices in the future.     

Understanding the potential and limitations of HfAlO as interpoly dielectric in floating-gate Flash memory

Introduction of high-k dielectrics in Flash memory is seen as a must for the upcoming technology nodes. Hafnium aluminate (HfAlO) has been identified as a possible candidate for implementing the interpoly dielectric in floating gate memory. In this work, we establish a link between the material morphology and its electrical response, allowing to understand memory device behavior and to consequently assess the potential and limitations of HfAlO as IPD in a memory cell.     

Uniform bipolar organic memory using vapor phase polymerized poly (3,4-ethylenedioxythiophene)

Organic memory device has emerged as an excellent candidate for the next generation storage devices due to its high performance and low production cost. In this paper, we report the fabrication and electrical characterization of an organic memory device made of vapor-phase polymerized PEDOT thin films that are highly uniform and free of PSS and free of unreacted reactants. The PEDOT memory device exhibited a typical bipolar resistive switching with a high ON/OFF current ratio of at least 10³, which was maintained for more than 10³ dc sweeping cycles. The device performance was stable for more than 10⁵ s. Moreover, the device containing 64 cells has very high cell to cell uniformity as demonstrated by (1) at least 93% of the cells displaying the ON/OFF current ratio of at least 10³ and (2) the deviation of the set and reset voltages from the average values being less than 0.5 V and 0.4 V, respectively. The maximum current before switching in the reset process was found to increase linearly with increase in the compliance current applied during the set process.     

Self-assembled metallic nanocrystal structures for advanced non-volatile memory applications

Nanocrystal (NC) based non-volatile memories are a leading candidate to replace conventional floating gate memory. Substituting the poly-silicon gate with a layer of discrete nanocrystals or nanodots provides increased immunity to charge loss. Metallic nanocrystals have been found to be advantageous over Si- or Ge-based approaches due to good controllability of the size distribution and the achievable NC densities as well as increased charge storage capacity of metallic nanocrystals. Sufficiently high NC densities have been achieved to demonstrate feasibility for sub-32 nm node non-volatile memory devices.     

Multilevel charge storage in Si nanocrystals arranged in double-dot-layers within SiO2

We investigated charging/discharging characteristics of a MOS structure with two layers of Si-nanocrystals (NCs) embedded in the SiO₂ dielectric. The two-dimensional (2D) arrays of nanocrystals, of sizes 3 and 5 nm in the lower and upper NCs layer, respectively, were fabricated by low pressure chemical vapor deposition (LPCVD) of amorphous Si (a-Si), followed by oxidation/annealing. The tunnel oxide was 3.5 nm thick. Successive charging of the NCs layers by both electrons and holes injected from the substrate was clearly demonstrated by the observed steps in the flatband voltage shift (ΔV_FB) as a function of the applied positive (electrons) or negative (holes) pulses on the gate, thus opening the potential for multiple bit operation of the memory. Discharging of the structure by pulses of opposite sign was consistently obtained. The current-voltage (I-V) curves exhibited two transient peaks at voltages corresponding to the two steps in ΔV_FB vs. V_gate that were attributed to a displacement current from the substrate to the nanocrystal layers. Clear improvement of charge retention in the double-nanocrystal layer structure compared to the single one was obtained, opening the possibility for lowering the gate oxide thickness of the NC memory without compromising device reliability.     

Electrical characteristics of nano-crystal Si particles for nano-floating gate memory

In these days, the researches of non-volatile memory device using nano-crystal(NC)-Si are actively progressing to replace flash memory devices. Many kinds of non-volatile memory devices such as phase-change(P)-RAM, resistance(Re)-RAM, polymer(Po)-RAM, and nano-floating gate memory(NFGM) are being studied. In this work, we study NFGM device in which information is memorized by storing electrons in silicon nanocrystal. The NFGM device has shown great promise for ultra-dense high-endurance memory device for low-power applications [S. Tiwari, et al., Appl. Phys. Lett. 68 (1996) 1377], and it is able to fabricate 1T-type device. Thus, the NFGM is considered to replace existing flash memory device. Non-volatile memory device has been fabricated by using NC-Si particles. The NC-Si particles have broad size range of 1-5 nm and an average size of 2.7 nm, which are sufficiently small to indicate the quantum effect for silicon. The memory window has been analyzed by C-V characteristic of NC-Si particles. V_d-I_d and V_g-I_d characteristics of the fabricated device have also been measured.