Effect of RuO2 electrode on laser-MBE prepared HfO2 gate dielectrics

In this paper, we report our recent study of the effect of RuO₂ as an alternative top electrode for pMOS devices to overcome the serious problems of polysilicon (poly-Si) gate depletion, high gate resistance and dopant penetration in the trend of down to 50 nm devices and beyond. The conductive oxide RuO₂, prepared by RF sputtering, was investigated as the gate electrode on the Laser MBE (LMBE) fabricated HfO₂ for pMOS devices. Structural, dielectric and electric properties were investigated. RuO₂/HfO₂/n-Si capacitors showed negligible flatband voltage shift (<10 mV), very strong breakdown strength (>10 MV cm⁻¹). Compared to the SiO₂ dielectric with the same EOT value, RuO₂/HfO₂/n-Si capacitors exhibited at least 4 orders of leakage current density reduction. The work function value of the RuO₂ top electrode was calculated to be about 5.0 eV by two methods, and the effective fixed oxide charge density was determined to be 3.3 × 10¹² cm⁻². All the results above indicate that RuO₂ is a promising alternative gate electrode for LMBE grown HfO₂ gate dielectrics.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

A comparative study of depth profiling of interface states using charge pumping and low frequency noise measurement in SiO2/HfO2 gate stack nMOSFETs

Charge pumping and low frequency noise measurements for depth profiling have been studied systematically using a set of gate stacks with various combinations of IL and HfO₂ thicknesses. The distribution of generated traps after HCI and PBTI stress was also investigated. The drain-current power spectral density made up all of the traps of IL in 0 < z < T_IL and the traps of HfO₂ in T_IL < z < T_HK. The traps near the Si/SiO₂ interface dominated the 1/f noise at higher frequencies, which is common in SiO₂ dielectrics. For the HfO₂/SiO₂ gate stack, however, the magnitude of the 1/f noise did not significantly change after HCI and PBTI because of more traps in the bulk HfO₂ film than at the bottom of the interface.     

Improved low frequency noise characteristics of sub-micron MOSFETs with TaSiN/TiN gate on ALD HfO2 dielectric

Low frequency noise measurements were performed on n- and p-channel MOSFETs with TaSiN and TiN metal gates, respectively, deposited on ALD HfO₂ gate dielectric. Lower normalized current noise power spectral density is reported for these devices in comparison to poly-Si/HfO₂ devices and that yielded one order lower magnitude for extracted average effective dielectric trap density. In addition, the noise levels in PMOS devices were found to be higher than NMOSFETs and the dielectric trap distribution less dense in the upper mid-gap than the lower mid-gap region. The screened carrier scattering coefficient extracted from the noise measurements was approximately the same for metal and poly-Si high-k stacks but higher than that for the poly-Si SiO₂ system, implying higher Coulomb scattering effects. It is believed that the elimination of dopant penetration seen in poly-Si system and low thermal budgets for metal gate deposition helped lower the noise magnitude and yielded better mobility and effective trap density values.     

Characteristics of metal-ferroelectric-insulator-semiconductor structure using Sr0.8Bi2.2Ta2O9 and Sr0.8Bi2.2Ta2O9-BaZrO3 for ferroelectric gates

Characteristics of BaZrO₃ (BZO) modified Sr_0.8Bi_2.2Ta₂O₉ (SBT) thin films fabricated by sol-gel method on HfO₂ coated Si substrates have been investigated in a metal-ferroelectric-insulator-semiconductor (MFIS) structure for potential use in a ferroelectric field effect transistor (FeFET) type memory. MFIS structures consisting of pure SBT and doped with 5 and 7 mol% BZO exhibited memory windows of 0.81, 0.82 and 0.95 V with gate voltage sweeps between −5 and +5 V, respectively. Leakage current density levels of 10⁻⁸ A/cm² for BZO doped SBT gate materials were observed and attributed to the metallic Bi on the surface as well as intrinsic defects and a porous film microstructure. The higher than expected leakage current is attributed to electron trapping/de-trapping, which reduces the data retention time and memory window. Further process improvements are expected to enhance the electronic properties of doped SBT for FeFET.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Improvement on low-temperature deposited HfO2 film and interfacial layer by high-pressure oxygen treatment

In this study, high-pressure oxygen (O₂ and O₂ + UV light) technologies were employed to effectively improve the properties of low-temperature-deposited metal oxide dielectric films and interfacial layer. In this work, 13 nm HfO₂ thin films were deposited by sputtering method at room temperature. Then, the oxygen treatments with a high-pressure of 1500 psi at 150 °C were performed to replace the conventional high temperature annealing. According to the XPS analyses, integration area of the absorption peaks of O-Hf and O-Hf-Si bonding energies apparently raise and the quantity of oxygen in deposited thin films also increases from XPS measurement. In addition, the leakage current density of standard HfO₂ film after O₂ and O₂ + UV light treatments can be improved from 3.12 × 10⁻⁶ A/cm² to 6.27 × 10⁻⁷ and 1.3 × 10⁻⁸ A/cm² at |Vg| = 3 V. The proposed low-temperature and high pressure O₂ or O₂ + UV light treatment for improving high-k dielectric films is applicable for the future flexible electronics.     

Interface optimization using diindenoperylene for C60 thin film transistors with high electron mobility and stability

C₆₀-based organic thin film transistors (OTFTs) with high electron mobility and high operational stability are achieved with (1 1 1) oriented C₆₀ films grown by using template effects of diindenoperylene (DIP) under layer on the SiO₂ gate insulator. The electron mobility of the C₆₀ transistor is significantly increased from 0.21 cm² V⁻¹ s⁻¹ to 2.92 cm² V⁻¹ s⁻¹ by inserting the template-DIP layer. Moreover much higher operational stability is also observed for the DIP-template C₆₀ OTFTs. A grazing incidence X-ray diffraction and ultrahigh-sensitivity photoelectron spectroscopy measurements indicate that the improved electron mobility and stability arise from the decreased density of trap states in the C₆₀ film due to increased (1 1 1) orientation of C₆₀-grains and their crystallinity on the DIP template.     

Annealing effect on the metal gate effective work function modulation for the Al/TiN/SiO2/p-Si structure

In this work, the thermal annealing effect on the metal gate effective work function (EWF) modulation for the Al/TiN/SiO₂/p-Si(1 0 0) structure was investigated. Compared with the sample of TiN/SiO₂/p-Si(1 0 0) structure, for the sample additionally capped with Al the flat band voltage has a very obvious shift as large as 0.54 V to the negative direction after forming gas annealing. It is also revealed that the thermal budget can effectively influence both the EWF of the gate electrode and the thickness of the gate dielectric layer when a post annealing at 600 °C with different soak times was applied to the samples with Al cap. Material characterization indicates that the diffusion of Al and the formation of Al oxide during annealing should be responsible for all the phenomena. The interface trap density Dit calculated from the high-frequency C-V and the laser-assisted high-frequency C-V curves show that the introduction of Al does not cause reliability problem in the Al/TiN/SiO₂/p-Si structure.     

Constant current stress-induced leakage current in mixed HfO2-Ta2O5 stacks

The electrical characteristics of HfO₂-Ta₂O₅ mixed stacks under constant current stress (CCS) at gate injection with 20 mA/cm² and stressing times of 50 and 200 s have been investigated. A very weak effect of the stress on the global dielectric constant, on fast and slow states in the stack as well as on the dominant conduction mechanism is detected. The most sensitive parameter to the CCS is the leakage current. The stress-induced leakage current (SILC) is voltage and thickness dependent. The pre-existing traps govern the trapping kinetics and are a key parameter to evaluate the stress response. Two processes - positive charge build-up and new bulk traps generation - are suggested to be responsible for SILC: the domination of one of them depends on both the film thickness and the stressing time. The positive charge build-up is localized close to the gate electrode implying gate-induced defects could be precursors for it. It is established that unlike the case of single SiO₂ layer, the bulk traps closer to the gate electrode control SILC in the mixed Ta₂O₅-HfO₂-based capacitors.     

Influence of the metal electrode on the characteristics of thermal Ta2O5 capacitors

The effect of various electrodes (Al, W, TiN) deposited by evaporation (Al) and sputtering (W, TiN) on the electrical characteristics of thermal thin film (15-35 nm) Ta₂O₅ capacitors has been investigated. The absolute level of leakage currents, breakdown fields, mechanism of conductivity, dielectric constant values are discussed in the terms of possible reactions between Ta₂O₅ and electrode material as well as electrode deposition process-induced defects acting as electrically active centers. The dielectric constant values are in the range 12-26 in dependence on both Ta₂O₅ thickness and gate material. The results show that during deposition of TiN and Al a reaction that worsens the properties of Ta₂O₅ occurs while there is not an indication for detectable reduction of Ta₂O₅ when top electrode is W, and the leakage current is 5-7 orders of magnitude lower as compared to Al and TiN-electroded capacitors. The high level of leakage current for TiN and Al gate capacitors are related to the radiation defects generated in Ta₂O₅ during sputtering of TiN, and damaged interface at the electrode due to a reaction between Al and Ta₂O₅, respectively. It is demonstrated that the quality of the top electrode affects the electrical characteristics of the capacitors and the sputtered W is found to be the best. The sputtered W gate provides Ta₂O₅ capacitors with a good quality: the current density <7 × 10⁻¹⁰ A/cm² at 1 V (0.7 MV/cm, 15 nm thick Ta₂O₅). W deposition is not accompanied by an introduction of a detectable damage leading to a change of the properties of the initial as-grown Ta₂O₅ as in the case of TiN electrode. Damage introduced during TiN sputtering is responsible for current deterioration (high leakage current) and poor breakdown characteristics. It is concluded that the sputtered W top electrode is a good candidate as a top electrode of storage capacitors in dynamic random access memories giving a stable contact with Ta₂O₅, but sputtering technique is less suitable (favorable) for deposition of TiN as a metal electrode due to the introduction of radiation defects causing both deterioration of leakage current and poor breakdown characteristics.     

Physical and electrical characterization of polysilicon vs. TiN gate electrodes for HfO2 transistors

The effects of pre-deposition substrate treatments and gate electrode materials on the properties and performance of high-k gate dielectric transistors were investigated. The performance of O₃ vs. HF-last/NH₃ pre-deposition treatments followed by either polysilicon (poly-Si) or TiN gate electrodes was systematically studied in devices consisting of HfO₂ gate dielectric produced by atomic layer deposition (ALD). High-angle annular dark field scanning transmission electron microscopy (HAADF-STEM) using X-ray spectra and Electron Energy Loss Spectra (EELS) were used to produce elemental profiles of nitrogen, oxygen, silicon, titanium, and hafnium to provide interfacial chemical information and to convey their changes in concentration across these high-k transistor gate-stacks of 1.0–1.8 nm equivalent oxide thickness (EOT). For the TiN electrode case, EELS spectra illustrate interfacial elemental overlap on a scale comparable to the HfO₂ microroughness. For the poly-Si electrode, an amorphous reaction region exists at the HfO₂/poly-Si interface. Using fast transient single pulse (SP) electrical measurements, electron trapping was found to be greater with poly-Si electrode devices, as compared to TiN. This may be rationalized as a result of a higher density of trap centers induced by the high-k/poly-Si material interactions and may be related to increased physical thickness of the dielectric film, as illustrated by HAADF-STEM images, and may also derive from the approximately 0.5 nm larger EOT associated with polysilicon electrodes on otherwise identical gate stacks.     

Epitaxial strontium oxide layers on silicon for gate-first and gate-last TiN/HfO2 gate stack scaling

We show that a thin epitaxial strontium oxide (SrO) interfacial layer enables scaling of titanium nitride/hafnium oxide high-permittivity (high-k) gate stacks for field-effect transistors on silicon. In a low-temperature gate-last process, SrO passivates Si against SiO₂ formation and silicidation and equivalent oxide thickness (EOT) of 5 Å is achieved, with competitive leakage current and interface trap density. In a gate-first process, Sr triggers HfO₂-SiO₂ intermixing, forming interfacial high-k silicate containing both Sr and Hf. Combined with oxygen control techniques, we demonstrate an EOT of 6 Å with further scaling potential. In both cases, Sr incorporation results in an effective workfunction that is suitable for n-channel transistors.     

Pentacene thin-film transistors with sol-gel derived amorphous Ba0.6Sr0.4TiO3 gate dielectric

An amorphous Ba_0.6Sr_0.4TiO₃ (BST) film with the thickness of 200 nm was deposited on indium-tin-oxide (ITO)-coated glass substrate through sol-gel route and post-annealing at 500 °C. The dielectric constant of the BST film was determined to be 20.6 at 100 kHz by measuring the Ag/BST/ITO parallel plate capacitor, and no dielectric tunability was observed with the bias voltage varying from −5 to 5 V. The BST film shows a dense and uniform microstructure as well as a smooth surface with the root-mean-square (RMS) roughness of about 1.4 nm. The leakage current density was found to be 3.5 × 10⁻⁸ A/cm² at an applied voltage of −5 V. The transmittance of the BST/ITO/glass structure is more than 70% in the visible region. Pentacene based transistor using the as-prepared BST film as gate insulator exhibits a low threshold voltage of −1.3 V, the saturation field-effect mobility of 0.68 cm²/Vs, and the current on/off ratio of 3.6 × 10⁵. The results indicate that the sol-gel derived BST film is a promising high-k gate dielectric for large-area transparent organic transistor arrays on glass substrate.     

MOS devices with tetragonal ZrO2 as gate dielectric formed by annealing ZrO2/Ge/ZrO2 laminate

A Ge-stabilized tetragonal ZrO₂ (t-ZrO₂) film with permittivity (κ) of 36.2 was formed by depositing a ZrO₂/Ge/ZrO₂ laminate and a subsequent annealing at 600 °C, which is a more reliable approach to control the incorporated amount of Ge in ZrO₂. On Si substrates, with thin SiON as an interfacial layer, the SiON/t-ZrO₂ gate stack with equivalent oxide thickness (EOT) of 1.75 nm shows tiny amount of hysteresis and negligible frequency dispersion in capacitance-voltage (C-V) characteristics. By passivating leaky channels derived from grain boundaries with NH₃ plasma, good leakage current of 4.8 × 10⁻⁸ A/cm² at V_g = V_fb − 1 V is achieved and desirable reliability confirmed by positive bias temperature instability (PBTI) test is also obtained.     

Temperature dependent time-to-breakdown (TBD) of TiN/HfO2 n-channel MOS devices in inversion

Effect of temperature on time-to-breakdown (T_BD) of n⁺-ringed n-channel MOS capacitors with atomic layer deposited TiN/HfO₂ based gate stacks is studied. While interfacial layer (IL) growth condition and thickness varied the high-κ layer thickness and processing was unchanged. These devices were investigated by applying a constant voltage stress (CVS) in inversion (substrate injection) at room and elevated temperatures. For high electric fields (10-15 MV/cm) across IL, it is observed that T_BD is thermally activated irrespective of IL condition. Activation energies (2-3 eV after correction), found from Arrhenius plots of T_BD for different IL conditions, show good matches with those associated with field-driven thermochemical model of breakdown developed for SiO₂.     

Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

Impact of the TiN electrode deposition on the HfO2 band gap for advanced MOSFET gate stacks

The impact of the deposition of a TiN electrode on the high-k oxide HfO₂ has been investigated, focussing on the dielectric band gap. After the gate elaboration, a non-destructive approach combining Spectroscopic Ellipsometry (SE), Reflection Electron Energy Loss Spectroscopy (REELS) and X-ray Photoelectron Spectroscopy (XPS) was developed to probe the buried metal/high-k interface. The overall optical band gap is 5.9 ± 0.1 eV with no change after the metal gate deposition. A local reduction of 1 eV is measured near the TiN layer, due to N diffusion at the interface creating N 2p states at the top of the HfO₂ valence band. Increased disorder and defects are identified in the high-k after gate elaboration by XPS, REELS and SE.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.