Fabrication and electrical characteristics of ultrathin (HfO2)x(SiO2)1−x films by surface sol-gel method and reaction-anneal treatment

Hafnium oxide (HfO₂) films were deposited on Si substrates with a pre-grown oxide layer using hafnium chloride (HfCl₄) source by surface sol-gel process, then ultrathin (HfO₂)_x(SiO₂)_1−x films were fabricated due to the reaction of SiO₂ layer with HfO₂ under the appropriate reaction-anneal treatment. The observation of high-resolution transmission electron microscopy indicates that the ultrathin films show amorphous nature. X-ray photoelectron spectroscopy analyses reveal that surface sol-gel derived ultrathin films are Hf-Si-O alloy instead of HfO₂ and pre-grown SiO₂ layer, and the composition was Hf_0.52Si_0.48O₂ under 500 °C reaction-anneal. The lowest equivalent oxide thickness (EOT) value of 0.9 nm of film annealed at 500 °C has been obtained with small flatband voltage of −0.31 V. The experimental results indicate that a simple and feasible solution route to fabricate (HfO₂)_x(SiO₂)_1−x composite films has been developed by means of combination of surface sol-gel and reaction-anneal treatment.     

Anomalous thermal oxidation of gadolinium thin films deposited on silicon by high pressure sputtering

Thin gadolinium metallic layers were deposited by high-pressure sputtering in pure Ar atmosphere. Subsequently, in situ thermal oxidation was performed at temperatures ranging from 150 to 750 °C. At an oxidation temperature of 500 °C the films show a transition from monoclinic structure to a mixture of monoclinic and cubic. Regrowth of interfacial SiO_x is observed as temperature is increased, up to 1.6 nm for 750 °C. This temperature yields the lowest interface trap density, 4 × 10¹⁰ eV⁻¹ cm⁻², but the effective permittivity of the resulting dielectric is only 7.4. The reason of this low value is found on the oxidation mechanism, which yields a surface with located bumps. These bumps increase the average thickness, thus reducing the capacitance and therefore the calculated permittivity.     

Improvement on low-temperature deposited HfO2 film and interfacial layer by high-pressure oxygen treatment

In this study, high-pressure oxygen (O₂ and O₂ + UV light) technologies were employed to effectively improve the properties of low-temperature-deposited metal oxide dielectric films and interfacial layer. In this work, 13 nm HfO₂ thin films were deposited by sputtering method at room temperature. Then, the oxygen treatments with a high-pressure of 1500 psi at 150 °C were performed to replace the conventional high temperature annealing. According to the XPS analyses, integration area of the absorption peaks of O-Hf and O-Hf-Si bonding energies apparently raise and the quantity of oxygen in deposited thin films also increases from XPS measurement. In addition, the leakage current density of standard HfO₂ film after O₂ and O₂ + UV light treatments can be improved from 3.12 × 10⁻⁶ A/cm² to 6.27 × 10⁻⁷ and 1.3 × 10⁻⁸ A/cm² at |Vg| = 3 V. The proposed low-temperature and high pressure O₂ or O₂ + UV light treatment for improving high-k dielectric films is applicable for the future flexible electronics.     

ALD of LaHfOx nano-laminates for high-κ gate dielectric applications

Electrical properties and thermal stability of LaHfO_x nano-laminate films deposited on Si substrates by atomic layer deposition (ALD) have been investigated for future high-κ gate dielectric applications. A novel La precursor, tris(N,N′-diisopropylformamidinato) lanthanum [La(ⁱPrfAMD)₃], was employed in conjunction with conventional tetrakis-(ethylmethyl)amido Hf (TEMA Hf) and water (H₂O). The capacitance-voltage curves of the metal oxide semiconductor capacitors (MOSCAPs) showed negligible hysteresis and frequency dispersion, indicating minimal deterioration of the interface and bulk properties. A systematic shift in the flat-band voltage (V_fb) was observed with respect to the change in structure of nano-laminate stacks as well as La₂O₃ to HfO₂ content in the films. The EOTs obtained were in the range of ∼1.23-1.5 nm with leakage current densities of ∼1.3 × 10⁻⁸ A/cm² to 1.3 × 10⁻⁵ A/cm² at V_fb − 1 V. In addition, the films with a higher content of La₂O₃ remained amorphous up to 950 °C indicating very good thermal stability, whereas the HfO₂ rich films crystallized at lower temperatures.     

A low gate leakage current and small equivalent oxide thickness MOSFET with Ti/HfO2 high-k gate dielectric

Annealing effects on electrical characteristics and reliability of MOS device with HfO₂ or Ti/HfO₂ high-k dielectric are studied in this work. For the sample with Ti/HfO₂ higher-k dielectric after a post-metallization annealing (PMA) at 600 °C, its equivalent oxide thickness value is 7.6 Å and the leakage density is about 4.5 × 10⁻² A/cm². As the PMA is above 700 °C, the electrical characteristics of MOS device would be severely degraded.     

Failure mechanisms of PVD Ta and ALD TaN barrier layers for Cu contact applications

PVD Ta-based and ALD TaN layers were studied as Cu diffusion barriers on poly-silicon, NiSi and CoSi₂ for Cu contact applications. The effectiveness of nanometer-thick layers, deposited in manufacturing compatible chambers on 200 and 300 mm wafers, is evaluated by detection of Cu-silicidation temperature using high temperature in situ XRD. It is found that Si diffuses into the α-Ta lattice for PVD barriers between 300 and 500 °C, and induces Ta silicidation at 600 °C. The agglomeration of TaSi₂ seems to be responsible for the damage of barrier continuity and cause subsequent Cu-silicidation. The growth of ALD TaN on different surfaces of NiSi was studied by XRF, RBS and XRR. The growth curves show excellent linearity as a function of thickness. TOF-SIMS shows closed layers after 60 ALD cycles. In situ XRD reveals that the failure temperature of 4 nm thick ALD layers is higher than 500 °C. It is found that the failure of 3 and 4 nm ALD TaN layers in Cu/barrier/NiSi stacks is a diffusion controlled process, with an activation energy Q of ∼2.2 eV and a pre-exponential factor D₀ of ∼3.8 × 10⁻³ cm²/s.     

Materials characterization of WNxCy, WNx and WCx films for advanced barriers

A ternary WN_xC_y system was deposited in a thermal ALD (atomic layer deposition) reactor from ASM at 300 °C in a process sequence using tungsten hexafluoride (WF₆), triethyl borane (TEB) and ammonia (NH₃) as precursors. The WC_x layers were deposited by a novel ALD process at a process temperature of 250 °C. The WN_x layers were deposited at 375 °C using bis(tert-butylimido)-bis-(dimethylamido)tungsten (^tBuN)₂(Me₂N)₂W (imido-amido) and NH₃ as precursors. WN_x grows faster on plasma enhanced chemical vapor deposition (PECVD) oxide than WC_x does on chemical oxide. WN_xC_y grows better on PECVD oxide than on thermal oxide, which is opposite of what is seen for WN_x. In the case of the ternary WN_xC_y system, the scalability towards thinner layers and galvanic corrosion behavior are disadvantages for the incorporation of the layer into Cu interconnects. ALD WC_x based barriers have a low resistivity, but galvanic corrosion in a model slurry solution of 15% peroxide (H₂O₂) is a potential problem. Higher resistivity values are determined for the binary WN_x layers. WN_x shows a constant composition and density throughout the layer.     

Influence of rapid thermal annealing temperature on structure and electrical properties of high permittivity HfTiO thin film used in MOSFET

HfTiO thin films were prepared by r.f. magnetron co-sputtering on Si substrate. To improve the electrical properties, HfTiO thin films were post heated by rapid thermal annealing (RTA) at 400 °C, 500 °C, 600 °C and 700 °C in nitrogen. It was found that the film is amorphous below 700 °C and at 700 °C monoclinic phase HfO₂ has occurred. With the increase of the annealing temperature, the film becomes denser and the refractive index increases. By electrical measurements, we found at 500 °C annealed condition, the film has the best electrical property with the largest dielectric constant of 44.0 and the lowest leakage current of 1.81 × 10⁻⁷ A/cm², which mainly corresponds to the improved microstructure of HfTiO thin film. Using the film annealed at 500 °C as the replacement of SiO₂ dielectric layer in MOSFET, combining with TiAlN metal electrode, a 10 μm gate-length MOSFET fabricated by three-step photolithography processes. From the transfer (I_DS–V_G) and output (I_DS–V_DS) characteristics, it shows a good transistor performance with a threshold voltage (V_th) of 1.6 V, a maximum drain current (I_ds) of 9 × 10⁻⁴ A, and a maximum transconductance (G_m) of 2.2 × 10⁻⁵ S.     

Ultrathin insulating silica layers prepared from adsorbed TEOS, H2O and NH3 as a catalyst

Homogeneous ultrathin silica films were deposited without need of any expensive equipment and high-temperature processes (t?200 °C). Repeated adsorption of tetraethoxysilane (TEOS) multimolecular layers and their subsequent reaction with H₂O/NH₃ mixed vapours at atmospheric pressure and room temperature were used. By preparing the Al/SiO₂/N-Si MOS structure conditions were attained for electrical characterisation of the thin oxide layer by capacitance (C-V) and current (I-V) measurements. These measurements confirmed acceptable insulating properties of the oxide, the maximum breakdown field intensity being E_bd=5.4 MV/cm. The total defect charge of the MOS structure was positive, affected by a high trap density at the Si-SiO₂ interface.     

Nitridation of hafnium oxide by reactive sputtering

Hafnium oxide films were RF sputtered from HfO₂ target in Ar/O₂ or Ar/N₂ ambient on silicon substrates. The composition of the deposited films was analyzed by X-ray photoelectron spectroscopy (XPS). For samples sputtered in Ar/N₂, it was observed that nitrogen was incorporated in the bulk of hafnium oxide films in the form of HfON, and SiON layer was formed at the silicon-insulator interface. After annealing the hafnium oxide films at 600-700 °C, MOS structures were fabricated and used for electrical characterization. The effects of nitridation of hafnium oxide on both the capacitance-voltage and current-voltage characteristics of the MOS capacitors were discussed.     

Electrical characteristics and TDDB breakdown mechanism of N2-RTA-treated Hf-based high-κ gate dielectrics

This study investigates the effects of rapid thermal annealing (RTA) in nitrogen ambient on HfO₂ and HfSiO_x gate dielectrics, including their electrical characteristics, film properties, TDDB reliability and breakdown mechanism. The optimal temperature for N₂ RTA treatment is also investigated. The positive oxide trap charges (oxygen vacancies) in HfO₂ and HfSiO_x dielectric films can be reduced by the thermal annealing, but as the annealing temperature increased, many positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy level will be formed in the grain boundaries, degrading the electrical characteristics, and changing the breakdown mechanism. We believe that variation in the number of positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy levels is the main cause of the CV shift and difference in the breakdown behaviors between HfO₂ and HfSiO_x dielectrics. With respect to CV characteristics and TDDB reliability, the optimal temperature for N₂ RTA treatment is in the range 500-600 °C and 800-900 °C, respectively.     

Barrier and seed repair performance of thin RuTa films for Cu interconnects

Thin (<4 nm) Physical Vapor Deposited (PVD) Ru-10 at.% Ta films were evaluated as diffusion barriers and seed enhancement layers for Cu metallization in sub 25 nm trenches. The ratio of Ru/Ta on blanket wafers could be influenced by changing the process conditions. However, a difference in Ru/Ta ratio did not influence the thermal stability of the layers during High Temperature X-ray Diffraction (HT-XRD) measurements as all RuTa films exhibited good thermal properties since no Cu-silicide formation was observed for temperatures below 500 °C. The RuTa films also passed an 85 °C/85% relative humidity (RH) test of one week of storage in order to test the H₂O barrier integrity of the films. Furthermore no difference was found when testing the O₂ barrier integrity during 300 s anneals at various temperatures between 250 °C and 500 °C. Good Cu fill of 20 nm trenches (AR 4:1) patterned in oxide was achieved when combining the RuTa films with PVD Cu seed layers with thicknesses ranging from 7 to 20 nm and Cu plating. When compared to a Ta(N)/Ta barrier, relatively high electrical yields (60-80%) were obtained for structures with CDs <30 nm when combining RuTa films with PVD Cu seed layers as thin as 7 nm (on field), hence evidencing the seed enhancement ability of these layers.     

Composition and electrical characteristics of Al2O3-HfO2-HfTiO nanolaminates on Si

A dielectric constant of 27 was demonstrated in the as deposited state of a 5 nm thick, seven layer nanolaminate stack comprising Al₂O₃, HfO₂ and HfTiO. It reduces to an effective dielectric constant (k_eff) of ∼14 due to a ∼0.8 nm interfacial layer. This results in a quantum mechanical effective oxide thickness (EOT) of ∼1.15 nm. After annealing at 950 °C in an oxygen atmosphere k_eff reduces to ∼10 and EOT increases to 1.91 nm. A small leakage current density of about 8 × 10⁻⁷ and 1 × 10⁻⁴ A/cm², respectively at electric field 2 and 5 MV/cm and a breakdown electric field of about 11.5 MV/cm was achieved after annealing at 950 °C.     

Properties of ALD HfTaxOy high-k layers deposited on chemical silicon oxide

HfTa_xO_y high-k dielectric layers with different compositions were deposited using ALD on 1 nm SiO₂ generated by ozone based cleaning of 200 mm Si(1 0 0) surface. Physical characterization of blanket layers and C-V mapping demonstrates that the ALD layers have excellent uniformity and controllable compositions. The layers with a composition of HfTaO_5.5 remain amorphous after annealing at 900 °C. The C-V measurements of MOS capacitors show no hysteresis, negligible frequency dispersion and interfacial state density smaller than 3 × 10¹¹ (cm⁻² eV⁻¹). k-value of the amorphous layers varies in the range from 20 to 25, depending on layer composition. The flat band voltage does not shift with the increase of EOT, implying that the effect of fixed charge densities in the layers is negligible. The I-V measurements show a leakage reduction comparable to that of the ALD HfO₂ layers.     

Thin titanium oxide films deposited by e-beam evaporation with additional rapid thermal oxidation and annealing for ISFET applications

Titanium oxide (TiO₂) has been extensively applied in the medical area due to its proved biocompatibility with human cells [1]. This work presents the characterization of titanium oxide thin films as a potential dielectric to be applied in ion sensitive field-effect transistors. The films were obtained by rapid thermal oxidation and annealing (at 300, 600, 960 and 1200 °C) of thin titanium films of different thicknesses (5 nm, 10 nm and 20 nm) deposited by e-beam evaporation on silicon wafers. These films were analyzed as-deposited and after annealing in forming gas for 25 min by Ellipsometry, Fourier Transform Infrared Spectroscopy (FTIR), Raman Spectroscopy (RAMAN), Atomic Force Microscopy (AFM), Rutherford Backscattering Spectroscopy (RBS) and Ti-K edge X-ray Absorption Near Edge Structure (XANES). Thin film thickness, roughness, surface grain sizes, refractive indexes and oxygen concentration depend on the oxidation and annealing temperature. Structural characterization showed mainly presence of the crystalline rutile phase, however, other oxides such Ti₂O₃, an interfacial SiO₂ layer between the dielectric and the substrate and the anatase crystalline phase of TiO₂ films were also identified. Electrical characteristics were obtained by means of I-V and C-V measured curves of Al/Si/TiO_x/Al capacitors. These curves showed that the films had high dielectric constants between 12 and 33, interface charge density of about 10¹⁰/cm² and leakage current density between 1 and 10⁻⁴ A/cm². Field-effect transistors were fabricated in order to analyze I_D x V_DS and log I_D × Bias curves. Early voltage value of −1629 V, R_OUT value of 215 MΩ and slope of 100 mV/dec were determined for the 20 nm TiO_x film thermally treated at 960 °C.     

Reliability of multistacked tantalum-based structure as the barrier film in ultralarge-scale integrated metallization

Diffusion barrier properties of Ta films with and without plasma treatments have been investigated in the study. The nitrogen-incorporated Ta films were prepared by NH₃ plasma treatment or reactive sputtering. Barrier properties were evaluated by sheet resistance, X-ray diffraction, transmission electron microscopy, X-ray photoelectron spectroscopy and reverse-biased junction leakage current. An amorphous-like TaN_x layer was formed on Ta barrier film after plasma treatments. The thickness of the amorphous TaN_x layer is about 3 nm and NH₃ plasma-treated Ta films (TaN_x/Ta) possess lower resistivity and smaller grain sizes. The Cu/TaN_x/Ta(10 nm)/Si remained stable after annealing at 750 °C for 1 h. NH₃ plasma-treated Ta films (TaN_x/Ta) possess better thermal stability than Ta and TaN films. It is attributed to the formation of a new amorphous layer on the surface of Ta film after the plasma treatments. For thermal stability of Cu/Ta(-N)/n⁺-p diodes, Cu/Ta/n⁺-p and Cu/TaN/n⁺-p junction diodes resulted in large reverse-bias junction leakage current after annealing at 500 and 525 °C, respectively. On the other hand, TaN_x/Ta diffusion barriers will improve the integrity of Cu/Ta(-N)/n⁺-p junction diodes to 650 °C.     

Schottky barrier SOI-MOSFETs with high-k La(2)O(3)/ZrO(2) gate dielectrics

Schottky barrier SOI-MOSFETs incorporating a La₂O₃/ZrO₂ high-k dielectric stack deposited by atomic layer deposition are investigated. As the La precursor tris(N,N′-diisopropylformamidinato) lanthanum is used. As a mid-gap metal gate electrode TiN capped with W is applied. Processing parameters are optimized to issue a minimal overall thermal budget and an improved device performance. As a result, the overall thermal load was kept as low as 350, 400 or 500 °C. Excellent drive current properties, low interface trap densities of 1.9 × 10¹¹ eV⁻¹ cm⁻², a low subthreshold slope of 70-80 mV/decade, and an I_ON/I_OFF current ratio greater than 2 × 10⁶ are obtained.     

Yttrium silicide formation and its contact properties on Si(1 0 0)

Yttrium silicide formation and its contact properties on Si(1 0 0) have been studied in this paper. By evaporating a yttrium metal layer onto Si(1 0 0) wafer in conventional vacuum condition and rapid thermal annealing, we found that YSi_2-x begins to form at 350 °C, and is stable to 950 °C. Atomic force microscopy characterization shows the pinholes formation in the formed YSi_2-x film. By current-voltage measurement, the Schottky barrier height (SBH) of YSi_2-x diode on p-type Si(1 0 0) was shown to be between 0.63 and 0.69 eV for annealing temperature from 500 to 900 °C. By low temperature current-voltage measurement, the SBH of YSi_2-x diode on n-type Si(1 0 0) was directly measured and shown to be 0.46, 0.37, 0.32 eV for annealing temperature of 500, 600, and 900 °C, respectively, and possibly even lower for annealing at 700 or 800 °C.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.     

Properties of low-k SiCOH films prepared by plasma-enhanced chemical vapor deposition using trimethylsilane

The properties of low-k SiCOH film deposited by plasma-enhanced chemical vapor deposition using trimethylsilane are reported here. The deposition process was performed at different temperatures from 200 to 400 °C. The influence of deposition temperature on the films were characterized using Fourier transform infrared spectroscopy (FTIR) to understand its impact on the studied properties. The films were annealed at ∼450 °C in an inert ambient after deposition in all the cases. The deposition rate decreases with increase in deposition temperature. The refractive index of the films increases as a function of deposition temperature. From FTIR spectra, OH-related bonds were not detected in films even when deposited at 200 °C. The Si-CH₃ bonds were detected in all the films and decreased monotonically from 200 to 400 °C. All deposition conditions studied resulted in films with dielectric constant less than 3, the lowest being ∼2.7 when deposited at 200 °C. All films exhibited good thermal stability.