Mechanism of electromigration failure in submicron Cu interconnects

This paper reports on two different electromigration-failure mechanisms competing in Cu interconnects. Accelerated electromigration tests are conducted on identical single-level, 0.25-μm Cu interconnects with SiN or SiCN passivation. The results indicate that the failure mechanism can vary with the interface condition of the capping layer. The first failure mechanism, seen primarily in SiN-capped samples, is characterized by extensive interface damage, believed to be a result of failure led by interface electromigration. In this failure mode, damage initiates at the capping interface but gradually spreads along all interfaces of the Cu to form an isolated strand. The competing failure mechanism, found in SiCN-capped samples, is characterized by the formation and growth of a localized void without extensive interface damage. The absence of interface damage, in addition to the higher activation energy for failure, suggests that the failure occurs at a more localized inhomogeneity than the interface, such as grain boundaries. While the exact mechanism of how the capping layer suppresses one mechanism and promotes the other is unknown, this study reveals that the passivation-interface material and condition have a decisive role in determining the failure mechanism in Cu interconnects.     

Effect of stresses on the evolution of annealing textures in Cu and Al interconnects

A new model is advanced to account for the evolution of annealing textures in copper and aluminum interconnects based on strain and surface energies. The interconnects, whether they are conventionally or damascene-process fabricated, are subjected to stresses during room temperature or elevated temperature annealing, which, in turn, gives rise to strain energies. The strain energy of a deposit is influenced by its texture and geometry. The annealing texture of an interconnect line is determined such that its elastic strain and surface energies are minimal. The measured textures in damascene-processed copper interconnects and a published result of conventionally processed Al-1%Cu interconnects are discussed based on minimization of their strain and surface energies.     

Study of electron-scattering mechanism in nanoscale Cu interconnects

This paper presents a study of electron scattering in damascene-processed Cu interconnects. To understand the leading electron-scattering mechanism responsible for the size effect, Cu interconnects with varying physical widths, 80–750 nm, were made, and their resistivity characterized as a function of temperature, ranging from liquid He temperature (4.2 K) to 500 K. The resulting data suggest that surface scattering, contrary to expectations, was not the primary cause of the size effect observed in this investigation. Surface scattering was found to weaken with decreasing line width. Further analysis leads to the conclusion that a substantial fraction of the size effect originates from impurity content scaling inversely with width in these samples.     

Electromigration-induced failure in operando characterization of 3D interconnects: microstructure influence

An accurate knowledge of the phenomenon is required to develop a predictive modeling of the electromigration failure. Thus, a hitherto unseen SEM in operando observation method is devised. The test structure with “high density” through silicon vias (TSV) is tested at 623 K with an injected current density of 1 MA/cm². Regular shots of micrographs inform about the voids nucleation, forced in copper lines above the TSV, and about the scenario of their evolution. A clear relation is established between voids evolution and the one of the electrical resistance. The lack of impact of test conditions on the failure mechanism is demonstrated. Finally, the impact of microstructure on the depletion mechanism is discussed. Grain boundaries are preferential voids nucleation sites and influence the voids evolution. A probable effect of grain size and crystallographic orientation is revealed.     

交流电诱发铜互联体的热疲劳失效行为及微观分析

本文报道了铜互联体布线在交流电作用下产生的一种新的热疲劳失效行为,通过透射电子显微镜对热疲劳损伤部位的研究,并与纯机械疲劳载荷作用下的铜薄膜损伤行为进行比较,分析了铜互联体热疲劳损伤失效机理。     

铜互连线静水应力的有限元模拟

本文根据工业上使用的铜大马士革互连线尺寸建立了三维有限元模型,模拟计算了铜大马士革互连线中对应力诱导形成空洞很关键的静水应力分布,对比分析了不同低k介质、阻挡层材料和互连线深宽比对静水应力的影响。研究结果表明,静水应力受k介质、阻挡层材料和互连线深宽比影响很大,静水应力在铜大马士革互连线中分布不均匀且最大应力出现在互连线表面。     

Finite element simulation of hydrostatic stress in copper interconnects

This work focuses on numerical modeling of hydrostatic stress,which is critical to the formation of stress-induced voiding(SIV) in copper damascene interconnects.Using three-dimensional finite element analysis, the distribution of hydrostatic stress is examined in copper interconnects and models are based on the samples, which are fabricated in industry.In addition,hydrostatic stress is studied through the influences of different low-k dielectrics,barrier layers and line widths of copper lines,and the results indicate that hydrostatic stress is strongly dependent on these factors.Hydrostatic stress is highly non-uniform throughout the copper structure and the highest tensile hydrostatic stress exists on the top interface of all the copper lines.     

Effect of copper seed aging on electroplating-induced defects in copper interconnects

Voids in copper thin films, observed after electroplating, have been linked to seed aging that occurs when a wafer is exposed, over time, to clean-room ambient. Oxidation of the copper seed surface prevents wetting during subsequent copper electroplating, leading to voids. Several surface treatments were employed to counteract the seed aging effect, including reduction of the copper oxide film by hydrogen, reverse plating of the copper surface, and rinsing the wafer surface with electrolyte. Each treatment was applied to wafers increasingly aged from 2 to 14 days, just prior to electroplating. Results showed a significant decrease in postelectroplating defects with all three treatments. The reduction of copper oxide by hydrogen exhibited the most marked results. An increase in surface wetting is shown by a decrease in contact angle measurements and an increase in film reflectivity for treated versus untreated copper wafers. This study shows that, although the copper surface exhibits strong aging effects over a short period of time, using proper surface treatments can eliminate such effects and voids.     

Physical investigation of the impact of electrolessly deposited self-aligned caps on insulation of copper interconnects

With the miniaturization of ULSI circuits and the associated increase of current density up to several MA/cm², copper interconnects are facing electromigration issues at the top interface with the dielectric capping layer SiC(N). A promising solution is to insert selectively on top of copper lines a CoWP metallic self-aligned encapsulation layer, deposited using a wet electroless process. We study the impact of this process on electrical line insulation as a function of cap thickness at the 65 nm technology node and we investigate the physical origin of leakage currents. Below a critical thickness, only a slight leakage current increase of less than one decade is observed, remaining within the specification for self-aligned capping layer processes. Above this critical thickness, large leakage currents are generated due to the combined effect of lateral growth and the presence of parasitic redeposited nodules. We show that a simple phenomenological model allows to reproduce the experimental data, to assess quantitatively the contribution of parasitic defects, and to predict that the self-aligned barrier technology should be extendible up to the 32 nm node, provided that a thin cap layer of less than 8 nm is used.     

Analysis of electromigration induced early failures in Cu interconnects for 45 nm node

Bi-directional current stressing was used for monitoring electromigration (EM) lifetime evolution in 45 nm node interconnects. Experimental results show that an initial bimodal distribution of lifetimes can be modified into a more robust mono-modal distribution. Since the bi-directional tests provide successive void nucleation and void healing phases, the Cu microstructure is thought to evolve once the formed void is filled thanks to EM induced matter displacement. FEM modeling is used to compare the predicted location of void nucleation for given microstructures at the cathode end: a multigrain structure is compared to a perfect bamboo microstructure. Experimental and modeling results let us assume that small grains (<linewidth or via diameter) at the cathode end present a risk of EM induced early fails. Indeed at this location void nucleates and grows nearby the via opening it shortly. On the contrary, the bamboo microstructure is thought to provide more robust lifetime because voids nucleate a few hundred nanometers in the line and grow down reaching the bottom diffusion barrier of the line. This latter case provides larger void size before circuit opening.     

Textural and microstructural transformation of Cu damascene interconnects after annealing

Influence of annealing on the textural and microstructural transformation of Cu interconnects having various line widths is investigated. Two types of annealing steps have been considered here: room temperature over 6 months and 200°C for 10 min. The texture was determined by x-ray diffraction (XRD) of various cross-sectional profiles after electropolishing, and the surface, microstructure, and grain boundary character distribution (GBCD) of Cu interconnects were characterized using electron backscattered diffraction (EBSD) techniques. In order to analyze a relationship between the stress distribution and textural evolution in the samples, microstresses were calculated with decreasing line widths at 200°C using finite element modeling (FEM). In this investigation, it was found that the inhomogeneity of stress distribution in Cu interconnects is an important factor, which is necessary for understanding textural transformation after annealing. A new interpretation of textural evolution in damascene interconnects lines after annealing is suggested, based on the state of stress and the growth mechanisms of Cu electrodeposits.     

Reliability and early failure in Cu/oxide dual-damascene interconnects

Recent results on up-direction electromigration (EM) studies on Cu dual-damascene (DD) interconnects are presented. The issue of the DD process and its potential effect on EM reliability is described with special focus on the peculiarities of the DD interconnect architecture in comparison to the previous subtractively etched Al-based interconnect technology. Experiments performed on multilink, DD interconnects that highlight EM reliability issues, such as early failure, and the Blech effect are summarized.     

Correlation of electromigration lifetime distribution to failure mode in dual Damascene Cu/SiLK interconnects

The electromigration cumulative percent lifetime probability of dual Damascene Cu/SiLK interconnects was fitted using three, individual lognormal functions where the functional populations were grouped by void growth location determined from focused ion beam failure analysis of all 54 of the stressed structures. The early, first mode failures were characterized by small voids in the bottom of the vias. The intermediate mode failures had voids in the line and via bottom while the late mode failures had voids that formed in the line only. The three, individual lognormal functions provided good fits of the data. Failure mode population separation using comprehensive failure analysis suggested that only the first mode failures should be used in the prediction of the chip design current.     

Thermomechanical response and stress analysis of copper interconnects

This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability issues for modern copper/low-k dielectric interconnect systems are discussed.     

大马士革镶嵌结构对Cu膜微结构及应力的影响

通过TEM、SEM、XRD和EBSD,观察了Cu互连线和平坦Cu膜的微观结构。采用薄膜应力测试分布仪和二维面探测器XRD,测量了平坦Cu膜和Cu互连线的应力,计算了Cu薄膜热应力的理论值。凹槽侧壁成为互连线新的形核区域,并且在平行于侧壁的方向形成较弱的(111)织构。与平坦膜相比,互连线晶粒尺寸明显变小(、111)织构较弱,且存在大量Σ3和Σ9晶界。平坦膜和互连线分别表现出压应力和张应力。降温过程产生的热应力为互连线的主要应力。     

Integration of optical interconnects and optoelectronic elements on wafer-scale

The UV-reaction molding technology enabling for the fabrication of microoptical elements with rectangular, triangular or circular cross-sections (waveguides, prisms, lenses) in optical polymers is described. Multimode waveguide optical interconnects, coupling prisms and holding structures for fibers can be fabricated in one step. A three-dimensional monomode waveguide interconnection module is presented. Stability tests of the microoptical elements are reported.     

Cu grain growth in interconnects trenches - Experimental characterization of the overburden effect

With the reduction of dimensions in interconnect copper lines, metal resistivity is seen to increase. This phenomenon is due to electron scattering on both sidewalls and grain boundaries. To reduce the grain boundary contribution and then resistivity, it becomes important to control microstructure. This paper focuses on the grain growth mechanism in a Damascene architecture. In this architecture, trenches are filled with copper. It is shown that the remaining copper on the top surface - the overburden - plays a key role in the final microstructure in the lines. Electrical results and observations are presented and discussed in terms of overburden grains extension inside the trenches. A method is proposed to quantify this grain extension.     

等电子杂质Sb对InP中缺陷的影响

用光致发光和正电子湮没技术研究了掺Sb InP单晶的“本征缺陷”。发现元素Sb的掺入导致磷空位(V_p)或者是V_p与杂质络合物的光致发光峰消失。用正电子湮没技术的测量也表明掺Sb的InP晶体中单空位浓度有所降低,两种方法测量的结果对应得很好。我们认为InP中掺Sb能有效地降低晶体中的本征缺陷。     

Cu互连线显微结构和应力的AFM及SNAM分析

在ULSI中采用Cu互连线代替Al以增加电子器件的传输速度和提高器件的可靠性，Cu的激活能约为1．2eV，而Al的激活能约为0．7eV,Cu互连线寿命约为Al的3－5倍。Cu大马士革互连线的制备工艺为：在硅衬底上热氧化生成的SiO2上开出凹槽，在凹槽中先后沉积阻挡层Ta和晶种层Cu，然后由电镀的Cu层将凹槽填满，最后采用化学机械抛光将凹槽外多余的Cu研磨掉，Cu互连线的尺寸为：200um长，0．5μm厚，宽度分别为0．35，0．5，1至3μm不等，部分样品分别在200℃，300℃和450℃下经过30min退火。利用原子力显微镜（AFM）和扫描近场声学显微镜（SNAM），同时获得形貌像和声像，分别了Cu大马士革凹槽构造引起的机械应力和沉积引起的热应力对Cu互连线显微结构及可靠性的影响，SNAM是在Topometrix公司AFM基础上建造的实验装置，实验采用的机械振动频率在600Hz-100kHz之间。分析测试结果如下：1．AFM和SNAM可以实现对微米和亚微米特征尺寸的Cu互连线的局域应力分布和显微结构的原位分析。2．采用AFM，TEM、XRD观察和测试了Cu互连线的晶体结构，分析了大马士革凹槽工艺 对Cu晶粒尺寸及取向的影响。平坦的沉积态Cu膜的晶粒尺寸约为100nm；而由大马士革工艺制备的凹槽中的Cu互连线的晶粒尺寸约为70－80nm，凹槽结构抑制了晶粒生长，平坦的沉积态Cu膜有较强的（111）织构；而凹槽中的Cu互连线的（111）织构减弱，（200）和其它的晶体取向分量增强。3．SNAM声阻尼信号对材料局域应力的变化敏感，SNAM声图衬底可显示出局域应力的分布，在沉积态的Cu互连线声图中，金属和SiO2介电层的界面处像衬度强，表明该处为应力较高的区域，而在退火后的Cu互连线的声图中，金属和SiO2介电层的界面处像衬度弱，表明退火后该处应力减小，我们对Cu膜进行了宏观应力的测试，退火后应力值从沉积态的661MPa减少至359Mpa，这与SNAM声成像的结果相符合。     

Spontaneous, non-aqueous electrochemical deposition of copper and palladium on Al and Al(Cu) thin films

Copper and palladium seed layers have been successfully deposited from organic solutions onto patterned and unpatterned pure aluminum and Al(0.5%Cu) thin films using an immersion displacement process. The reaction occurs at ambient temperature and pressure by a spontaneous electrochemical mechanism. Copper and palladium deposition using the organic solution was studied as a function of reaction time and Cu or Pd concentration in the solution. It was found that both time and the intial ionic metal concentration significantly influence deposit morphology, particle size and shape, and adherence. Nucleation of Cu or Pd sub-micron particles on both Al and Al(Cu) surfaces occurred in less than one minute while nucleation density and particle size increased with longer deposition times. Increasing the copper or palladium concentration in the organic solution resulted in an increase in the final particle size of the seed crystals. However, an increase in deposition time and metal concentration in the organic solution caused more extensive dissolution and pitting of the aluminum thin films. The Cu and Pd deposits were effectively used as catalytic sites for subsequent electroless or electrolytic copper deposition using conventional aqueous processes.