Integration of low dimensional crystalline Si into functional epitaxial oxides

In this work we show that by efficiently exploiting the growth kinetics during molecular beam epitaxy (MBE) one could create Si nanostructures of different dimensions. Examples are Si quantum dots (QD) or quantum wells (QW), which are buried into an epitaxial rare-earth oxide, e.g. Gd₂O₃. Electrical measurements carried out on Pt/Gd₂O₃/Si MOS capacitors comprised with Si-QD demonstrate that such well embedded Si-QD with average size of 5 nm and density of 2×10¹² cm⁻² exhibit very good charge storage capacity with suitable retention (∼10⁵ s) and endurance (∼10⁵ write/erase cycles) characteristics. The Pt/Gd₂O₃/Si (metal-oxide-semiconductor (MOS)) basic memory cells with embedded Si-QD display large programming window (∼1.5-2 V) and fast writing speed and hence could be a potential candidate for future non-volatile memory application. The optical absorption of such Si-QD embedded into epitaxial Gd₂O₃ was found to exhibit a spectral threshold maximum up to 2.9±0.1 eV depending on their sizes, inferring a significant influence of quantum confinement on the QD/oxide interface band diagram.Ultra-thin single-crystalline Si-QW with epitaxial insulator (Gd₂O₃) as the barrier layers were grown by a novel approach based on cooperative vapor phase MBE on Si wafer with sharp interfaces between well and barriers. The current-voltage characteristics obtained for such structure exhibits negative differential resistance at lower temperature, making them a good candidate for resonant tunneling devices.     

Charge-trapping characteristics of BaTiO3 with and without nitridation for nonvolatile memory applications

The charge-trapping characteristics of BaTiO₃ with and without nitrogen incorporation were investigated based on Al/Al₂O₃/BaTiO₃/SiO₂/Si (MONOS) capacitors. The physical properties of the high-k films were analyzed by transmission electron microscopy and X-ray photoelectron spectroscopy. Compared with the MONOS capacitor with BaTiO₃ as charge-trapping layer, the one with nitrided BaTiO₃ showed higher program speed even at lower operating voltage (4.3 V at +8 V for 100 μs), better endurance property and smaller charge loss (charge loss of 10.6% after 10⁴ s at 85 °C), due to the nitrided BaTiO₃ film exhibiting higher charge-trapping efficiency caused by nitrogen incorporation and suppressed leakage induced by nitrogen passivation.     

通信波段稀土离子掺杂固态量子存储进展

量子互联网是实现多方量子通信、分布式量子计算等量子信息技术的重要基础,量子存储器作为实现互联网的重要部件,对量子信息技术的发展、应用具有举足轻重的作用。如今遍布全球的光纤网络已经是信息传输的有力载体,通信波段的量子存储器因容易嵌入到当前的光纤网络中而备受重视。聚焦于稀土离子掺杂固态体系的通信波段光量子存储,首先介绍稀土离子掺杂固态量子存储的基本原理,包括稀土掺杂材料特性以及存储协议等,然后介绍目前的研究现状,最后简要分析其未来的发展趋势,并对量子互联网的构建做出展望。     

Formation of stacked ruthenium nanocrystals embedded in SiO2 for nonvolatile memory applications

n metal oxide semiconductor (MOS)capacitors fabricated by the former method, which are much better than 4.6 Ⅴ and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

面向非挥发存储器应用的叠层Ru纳米晶材料的制备与特性

Two methods are proposed to fabricate stacked ruthenium （Ru） nanocrystals （NCs）： rapid thermal annealing （RTA） for the whole gate stacks, and RTA before each SiO2 layer deposition. The size and aerial density of Ru NCs are 2-4 nm and 3 × 10^12 cm^-2 for the former method, compared to 3-7 nm and 2 ×10^12 cm^-2 for the latter. Because of the higher surface trap density and more uniform electron tunneling path between upper and lower Ru NCs, a 5.2 V memory window and 1 V after a period of 10 years are observed in metal oxide semiconductor （MOS） capacitors fabricated by the former method, which are much better than 4.6 V and no window remaining after one year observed in the latter. The former method is compatible with conventional CMOS technology.     

Synthesis of the PZT films deposited on pt-coated (100) Si substrates for nonvolatile memory applications

Ferroelectric lead-zirconate-titanate (PZT) thin films were deposited by the pulsed laser deposition technique on Pt-coated (100) Si substrates. This study was focused on the investigation of the PZT film growth on (100) Si substrate at varying deposition parameters and electrical characterization of the films including hysteresis loop and fatigue properties by RT66A Standardized Ferroelectric Test System. PZT deposited at higher temperature (575°C in 450 mTorr O₂ partial pressure) showed the best crystalline structure. The remnant polarization and the retained polarization of the ferroelectric capacitors were 13 μC/cm² and 20 μC/cm², respectively. The crystallographic properties of the films were determined using the x-ray diffractometer method. The cross-sectional transmission electron microscope results showed very smooth interfaces among different layers of films.     

Characterization of PI:PCBM organic nonvolatile resistive memory devices under thermal stress

In this study, we fabricated nonvolatile organic memory devices using a mixture of polyimide (PI) and 6-phenyl-C61 butyric acid methyl ester (PCBM) (denoted as PI:PCBM) as an active memory material with Al/PI:PCBM/Al structure. Upon increasing the temperature from room temperature to 470 K, we demonstrated the good nonvolatile memory properties of our devices in terms of the distribution of ON and OFF state currents, the threshold voltage from OFF state to ON state transition, the retention, and the endurance. Our organic memory devices exhibited an excellent ON/OFF ratio (I_ON/I_OFF > 10³) through more than 200 ON/OFF switching cycles and maintained ON/OFF states for longer than 10⁴ s without showing any serious degradation under measurement temperatures up to 470 K. We also confirmed the structural robustness under thermal stress through transmission electron microscopy cross-sectional images of the active layer after a retention test at 470 K for 10⁴ s. This study demonstrates that the operation of PI:PCBM organic memory devices could be controlled at high temperatures and that the structure of our memory devices was maintained during thermal stress. These results may enable the use of nonvolatile organic memory devices in high temperature environments.     

Multilevel characteristics and operating mechanisms of nonvolatile memory devices based on a floating gate of graphene oxide sheets sandwiched between two polystyrene layers

Nonvolatile organic memory devices were fabricated utilizing a graphene oxide (GO) layer embedded between two polystyrene (PS) layers. Scanning electron microscope images of GO sheets sandwiched between two PS layers showed that the GO sheets were clearly embedded in the PS layers. Capacitance–voltage (C–V) curves of the Al/PS/GO/PS/n-type Si devices clearly showed hysteresis behaviors with multilevel characteristics. The window margin of the nonvolatile memory devices increased from 1 to 7 V with increasing applied sweep voltages from 6 to 32 V. The cycling retention of the ON/OFF switching for the devices was measured by applying voltages between +15 and −15 V. While the capacitance of the memory devices at an ON state have retained as 230 pF up to 10⁴ cycles, that at an OFF state maintained as 16 pF during three times of repeated measurements. The extrapolation of the retention data for the devices maintained up to 10⁶ cycles. The operating mechanisms of the nonvolatile organic memory devices with a floating gate were described by the C–V results and the energy band diagrams.     

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

The self-assembly of metal nanocrystals including Au, Ag, and Pt on ultrathin oxide for nonvolatile memory applications are investigated. The self-assembly of nanocrystals consists of metal evaporation and selective rapid-thermal annealing (RTA). By controlling process parameters, such as the thickness of the deposited film, the post-deposition annealing temperatures, and the substrate doping concentration, metal nanocrystals with density of 2–4 × 10¹¹ cm⁻², diameter less than 8.1 nm, and diameter deviation less than 1.7 nm can be obtained. Observation by scanning-transmission electron microscopy (STEM) and convergent-beam electron diffraction (CBED) shows that nanocrystals embedded in the oxide are nearly spherical and crystalline. Metal contamination of the Si/SiO₂ interface is negligible, as monitored by STEM, energy dispersive x-ray spectroscopy (EDX), and capacitance-voltage (C-V) measurements. The electrical characteristics of metal, nanocrystal nonvolatile memories also show advantages over semiconductor counterparts. Large memory windows shown by metal nanocrystal devices in C-V measurements demonstrate that the work functions of metal nanocrystals are related to the charge-storage capacity and retention time because of the deeper potential well in comparison with Si nanocrystals.     

Resistive switching characteristics of Sm2O3 thin films for nonvolatile memory applications

This study investigates a sputtered Sm₂O₃ thin film to apply into a resistive random access memory device. The proposed device exhibits a stable resistance ratio of about 2.5 orders after 10⁴ cycling bias pulses and no degradation for retention characteristics monitored after an endurance test at 85 °C. The conduction mechanisms for low and high resistance states are dominated by ohmic behavior and trap-controlled space-charge limited current, respectively. The resistance switching is ascribed to the formation/rupture of conductive filaments.     

Optoelectronic properties of transition metal and rare earth doped epitaxial layers on InP for magneto-optics

Rare earth-and transition metal-doped thin films of InP, In_0.53Ga_0.47As, and In_0.71Ga_0.29As_0.58P_0.42 were grown by liquid phase epitaxy and evaluated for use in integrated electro-optical and magneto-optical applications, such as waveguides and Faraday rotators. The films were lattice matched to (100) InP substrates, and the transition metal (Mn) and rare earth (Gd, Eu, and Er) doping concentra-tions were between 2.6 × 10¹⁸ and 1.5 × 10²⁰ cm^-3. The chemical profiles were generally found to be homogeneous by SIMS, although in more highly doped films the rare earths were observed to segregate toward the interfaces. The undoped films were n-type, and the net carrier concentrations in the rare earth-doped (Gd, Eu, Er) films were decreased by an order of magnitude. The Mn-doped films were p-type. Optically, the rare earth dopants were observed to raise the refractive index of the layers at 632.8 nm, and subsequent waveguiding in doped InP layers was observed at 1.3 μm. Although the Faraday rotations of our materials were much less than that of well known oxides, such as yttrium iron garnet, they were sufficient for device applications, and our materials can be much more easily integrated with InP OEIC devices. For example, a 1 cm waveguide would provide the large rotation (45°) required in isolator applica-tions.     

Double-gate 1T-DRAM cell using nonvolatile memory function for improved performance

We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-gate voltage (V_cg) and nonvolatile memory (NVM) function. The additional NVM function is achieved by Fowler-Nordheim (FN) tunneling electron injection into the nitride storage node. The injected electrons induce a permanent hole accumulation layer in silicon body which improves the sensing margin and retention time characteristics. To demonstrate the effect of stored electrons in the nitride layer, experimental data are provided using 0.6 μm devices fabricated on SOI wafers.     

High-k polymer dielectrics with different cross-linked networks for nonvolatile transistor memory device

Nonvolatile OFET memory devices using different pPFPA/bPEI cross-linked polymers as the dielectric layer are fabricated. The influence of bPEI content on the electrical property and memory performance of devices are systematically investigated. The results demonstrate that the introduction of bPEI into pPFPA can significantly enhance the capacitance and dielectric constant of the pPFPA/bPEI cross-linked polymer dielectrics, but it also causes a slight increase in the leakage current density. Besides, the excess bPEI induces more morphology defects of the semiconductor film, leading to an apparent decrement in charge mobility. Transistors with the 119:250 pPFPA/bPEI dielectric layer exhibit the highest on/off current ratio (~10⁷ at V_g = − 20V) and a relatively low hole mobility of 0.38 cm² V⁻¹s⁻¹. Moreover, the corresponding memory devices show good reliability in information record with a data retention time over 10⁵ s, indicating that an appropriate amount of bPEI is crucial for improving the stability of the memory devices.     

Lanthanide rare earth oxide thin film as an alternative gate oxide

An ultrathin gate oxide is needed for future nanoscale technology due to the density of integrated circuits will increase exponentially every two to three years as predicted by Moore's Law. Some problems were occurred in conventional silicon dioxide gate oxide during applications such as high leakage current density, low reliability issues, and undesirable power dissipation. Lanthanide rare earth oxides was attracted as one of potential candidates to replace conventional silicon dioxide due to their superior properties. Each rare earth oxides in lanthanide group was reviewed and discussed in terms of physical, chemical, and electrical properties and also its common deposition methods. Sm₂O₃ is one of the promising candidate materials among rare earth oxides because of some outstanding properties such as high κ (7–22), high breakdown electric field (5–7 MV cm^-1), relatively large bandgap (4.33 eV), low leakage current, large conduction offset with Si, high thermal stability, small frequency dispersion, low trapping rate, and low hygroscopic characteristic. The literatures of Sm₂O₃ was paid particular attention in the last section. The previous deposition methods of the Sm₂O₃ as gate oxide were reviewed and compared.     

Rare earth-based high-k materials for non-volatile memory applications

A study of a La-based high-k oxide to be employed as active dielectric in future scaled memory devices is presented. The focus will be held on La_xZr_1−xO_2−δ (x = 0.25) compound. In order to allow the integration of this material, its chemical interaction with an Al₂O₃ cap layer has been studied. Moreover, the electrical characteristics of these materials have been evaluated integrating them in capacitor structures. The rare earth-based ternary oxide is demonstrated to be a promising candidate for future non-volatile memory devices based on charge trapping structure.     

Characterization of various alloying metal oxide nanoparticles embedded in HfOxNy as charge trapping nodes in nonvolatile memory devices

This work compares Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO alloying metal oxide nanoparticles (AMONs) that were individually embedded in HfO_xN_y high-k dielectric as charge trapping nodes. They were formed by chemical vapor deposition using Co/Mo, Co/Fe and Fe/Mo acetate, respectively, calcined and reduced in Ar/NH₃ ambient. The effects of various pre-treatments on Co_xMo_yO, Co_xFe_yO and Fe_xMo_yO AMONs preparation were investigated. The results indicate that the larger charge trap density, larger memory window and better programming characteristics of Co_xMo_yO AMONs are attributable to their higher surface density and smaller diameter. The average collected charge in each Co_xMo_yO AMON is the smallest among three AMONs, revealing that a local leakage path is associated with the least charge loss. The main mechanism that governs the programming characteristics involves the trapping of holes.     

Stackable nonvolatile memory with ultra thin polysilicon film and low-leakage (Ti, Dy)xOy for low processing temperature and low operating voltages

We report the fabrication process as well as material and electrical characterization of ultra thin body (UTB) thin film transistors (TFTs) for stackable nonvolatile memories by using in situ phosphorous doped low-temperature polysilicon followed by the chemical mechanical polishing (CMP) process. The resulting polysilicon film is about 13 nm thick with approximately 10¹⁹ cm⁻³ doping. Root mean square surface roughness below 1 nm is achieved. Metal nanocrystals and high-k dielectric are selected for storage nodes and tunneling barriers to achieve low operating voltages. The number density and average diameter of nanocrystals embedded in the gate stack are 7.5 × 10¹¹ cm⁻² and 5.8 nm, respectively. Furthermore, scanning transmission electron microscopy (STEM), convergent beam electron diffraction (CBED) and electron energy loss spectroscopy (EELS) are performed for material characterization. The dielectric constant of the (Ti, Dy)_xO_y film is 35, and the off-state leakage current at −1 V bias and 2.8 nm equivalent oxide thickness is 5 × 10⁻⁷ A/cm². We obtain a memory window of about 0.95 V with ±6 V program/erase voltages. Our results show that UTB TFT is a promising candidate for the three-dimensional integration in high-density nonvolatile memory applications.     

一种适用于低压高速嵌入式应用的2T P沟道纳米晶存储器件

本文基于嵌入式应用的低压、高速要求,提出了一种基于2T结构的P沟道纳米晶存储新型结构。该器件采用带带隧穿激发热电子注入(BTBTIHE)的编程方式,可以同时实现高速、低功耗编程。同时采用2T结构以简化外围高压和读出电路。该器件具有良好的存储特性,包括高编程速度（5us编程脉冲下获得1.1V窗口）和优异的数据保持特性（在10年的保持时间电荷损失仅为20%）。该器件在嵌入式非挥发存储领域具有很强的应用潜力。     

PEM:a lightweight program memory encryption mechanism for embedded processor

Application of embedded systems is faced with multiple threats against security.To solve this problem,this article proposes a new program memory encryption mechanism(PEM) to enhance the security of embedded processor.The new mechanism encrypts all the programs via a secure cache structure.It not only caches the instructions read from the off-chip memory,but also stores the pad values used to encrypt the plaintext.It effectively accelerates encryption and reduces the performance overhead.Besides the encrypti...     

Cost-effective integration of an FN-programmed embedded flash memory into a 0.25 μm SiGe:C RF-BiCMOS technology

 This paper presents a process technology for cost-effective integration of low-power flash memories into a 0.25 μm, high performance SiGe:C RF-BiCMOS process. Only four additional lithographic steps are used on top of the baseline BiCMOS process, leading to in total 23 mask levels for the BiCMOS/embedded flash process. Uniform-channel Fowler-Nordheim programmable and erasable stacked-gate cells, suitable for medium density (∼Mbit) memories, are demonstrated. Peripheral high-voltage transistors, with >10 V breakdown voltage, are integrated without additional mask steps on top of the flash cell integration. The flash memory integration is modular and has negligible impact on the original CMOS and HBT device parameters.