Effect of Gate Electrode Work‐Function on Source Charge Injection in Electrolyte‐Gated Organic Field‐Effect Transistors

Systematic investigation of the contact resistance in electrolyte‐gated organic field‐effect transistors (OFETs) demonstrates a dependence of source charge injection versus gate electrode work function. This analysis reveals contact‐limitations at the source metal‐semiconductor interface and shows that the contact resistance increases as low work function metals are used as the gate electrode. These findings are attributed to the establishment of a built‐in potential that is high enough to prevent the Fermi‐level pinning at the metal‐organic interface. This results in an unfavorable energetic alignment of the source electrode with the valence band of the organic semiconductor. Since the operating voltage in the electrolyte‐gated devices is on the same order as the variation of the work functions, it is possible to tune the contact resistance over more than one order of magnitude by varying the gate metal.     

Scalability of strained-Si nMOSFETs down to 25 nm gate length

Strained-Si nMOSFETs with a standard polysilicon gate process were fabricated down to 25 nm gate length with well-behaved characteristics and small difference in short channel effects. The performance enhancement degrades linearly as the gate length becomes shorter, due to not only the parasitic resistance but also heavy halo implant. Thus the key integration issues are how to manage threshold difference and As diffusion without excess doping. With comparable doping and well controlled parasitic resistance, up to 45% improvement in drive current is predicted for sub-50 nm gate length strained-Si nMOSFETs on the Si/sub 0.8/Ge/sub 0.2/ substrate. In this work approximately 45% enhancement is in fact demonstrated for 35 nm gate length devices, through advanced channel engineering and implementation of metal gates.     

Jet vapor deposition nitride processing and application to advanced CMOS devices for reduction of gate leakage current and boron penetration

The increase in gate leakage current and boron penetration are major problems for scaled gate dielectrics in advanced device technology. We have demonstrated, for the first time, reduction in gate leakage current and strong resistance to boron penetration when jet vapor deposition (JVD) nitride is used as a gate dielectric in an advanced CMOS process. JVD nitride provides a robust interface in addition to well behaved bulk properties, MOSFET characteristics and ring oscillator performance. Process optimization is discussed. Manufacturing issues remain to be addressed.     

金属栅/高k基FinFET研究进展

对比传统的平面型晶体管,总结了三维立体结构FinFET器件的结构特性。结合MOS器件栅介质材料研究进展,分别从纯硅基、多晶硅/高k基以及金属栅/高k基三个阶段综述了Fin-FET器件的发展历程,分析了各阶段FinFET器件的材料特性及其在等比缩小时所面临的关键问题,并着重从延迟时间、可靠性和功耗三方面分析了金属栅/高k基FinFET应用于22 nm器件的性能优势。基于短沟道效应以及界面态对器件性能的影响,探讨了FinFET器件尺寸等比缩小可能产生的负面效应及其解决办法。分析了FinFET器件下一步可能的发展方向,主要为高迁移率沟道材料、立体型栅结构以及基于新原理的电子器件。     

Investigation of NiSi and TiSi as CMOS gate materials

NiSi is a promising new candidate for CMOS gate metal material because its workfunction can be adjusted by the implantation of dopants into the silicon before silicidation. In this report, NiSi and TiSi are studied, and the work functions of each are found to be adjustable over a wider range than previously published. This range covers the work function values required to achieve correct threshold voltages (V/sub t/) for both deep-scaled bulk CMOS and fully depleted, silicon-on-insulator MOSFETs. The influence of these silicides on the gate oxide and interface quality is also examined thoroughly via measurements of capacitance, minority carrier mobility, and gate-leakage current. While no degradation of the interface is observed with NiSi gates, TiSi gates generate interface traps and significantly degrade transistor device performance. With all the merits of a metal gate and no apparent degradation of interface quality, NiSi can be integrated with minor modification into a standard CMOS process and is a promising gate metal material for future CMOS technology generations.     

GaN-based HEMTs tested under high temperature storage test

In this work, the impact of 1000 h thermal storage test at 325 °C on the performance of gallium nitride high electron mobility transistors grown on Si substrates (GaN-on-Si HEMTs) is investigated. The extensive DC- and pulse-characterization performed before, during and after the stress did not reveal degradation on the channel conduction properties as well as formation of additional trapping states. The failure investigation has shown that only the gate and drain leakage currents were strongly affected by the high temperature storage test. The physical failure analysis revealed a Au inter-diffusion phenomenon with Ni at the gate level, resulting in a worsening of the gate–AlGaN interface. It is speculated that this phenomenon is at the origin of the gate and drain leakage current increasing.     

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

High-quality schottky and ohmic contacts in planar 4H-SiC metal semiconductor field-effect transistors and device performance

We have fabricated planar 4H-SiC, metal-semiconductor field-effect transistors (MESFETs) with high-quality metal/SiC contacts. To eliminate potential damage to the gate region caused by etching and simplify the device fabrication process, gate Schottky contacts were formed without any recess gate etching, and an ideality factor of 1.03 was obtained for these gate contacts. The interface state density between the contact metal and SiC was 5.7×10¹² cm⁻²eV⁻¹, which was found from the relationship between the barrier height and the metal work function. These results indicate that the interface was well controlled. Thus, a transconductance of 30 mS/mm was achieved with a 3-μm gate length as the performance figure of these MESFETs with high-quality metal/SiC contacts. Also, a low ohmic contact resistance of 1.2×10⁻⁶ Θcm² was obtained for the source and drain ohmic contacts by using ion implantation.     

Thermal instability of effective work function in metal/high-/spl kappa/ stack and its material dependence

Thermal instability of effective work function and its material dependence on metal/high-/spl kappa/ gate stacks is investigated. It is found that thermal instability of the effective work function of metal electrode on a gate dielectric is strongly dependent on the gate electrode and dielectric material. Thermal instability of a metal gate is related to the presence of silicon at the interface, and the Fermi-level pinning position is dependent on the location of silicon at the interface. The silicon-metal or metal-silicon bond formation by thermal anneal at the metal/dielectric interface induces the donor-like or acceptor-like interface states, causing a change of effective work function.     

Work Function Tuning Via Interface Dipole by Ultrathin Reaction Layers Using AlTa and AlTaN Alloys

This letter presents a route for tuning the metal gate effective work function via interface dipoles formed using AlTa and AlTaN alloys. It was found that the AlTa alloy has a higher effective work function (4.45 eV) compared to either Al ($sim$4.1 eV) or Ta (4.2 eV) gates on$hboxSiO_2$at 400$^circhboxC$. This increase in effective work function was attributed to interface dipoles formed at the gate electrode and dielectric interface. The origin of this dipole is attributed to a reaction between the AlTa alloy and the dielectric layer. Similar AlTa effective work function tuning was also observed on high-$k$dielectrics. However, since the AlTa alloy is not thermally stable on$hboxSiO_2$, nitrogen was added to stabilize the electrode. The addition of N stabilizes the equivalent oxide thickness while still allowing for work function tuning under high temperatures. AlTaN alloys were deposited by reactive sputtering and resulted in an effective work function of$sim$5.1 eV after a 1000$^circhboxC$anneal, making them suitable for PMOS gate applications.     

Impact of gate stack process on conduction and reliability of 0.18 μm PMOSFET

Aim of this work is the investigation of the impact of gate stack process on conduction and reliability of NMOSFET and PMOSFET in 0.18 μm dual-gate technology. Different poly-Si gate depositions and annealing oxidations have been compared, showing a strong impact on conduction characteristics only in PMOSFET in inversion mode. The differences have been ascribed to the contribution of electron tunneling through interface states at the poly-Si/SiO₂ interface, whose density depends on the poly-Si grain dimension. STEM cross-sections have indeed shown completely different grain size depending on the gate stack technology. A significantly different reliability performance is found in correspondence.     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

The material and electrical properties of HfO2 high-k gate dielectric are reported.In the first part,the band alignment of HfO2 and (HfO2)x(Al2O3)1-x to (100)Si substrate and their thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO2)x(Al2O3)1-x,the valence band offset,and the conduction band offset between (HfO2)x(Al2O3)1-x and the Si substrate as functions of x are obtained based on the XPS results.Our XPS results also demonstrate that both the thermal stability and the resistance to oxygen diffusion of HfO2 are improved by adding Al to form Hf aluminates.In the second part,a thermally stable and high quality HfN/HfO2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage,and work function (close to Si mid-gap) of HfN/HfO2 gate stack are demonstrated even after 1000℃ post-metal annealing(PMA),which is attributed to the superior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/HfO2 interface.Therefore,even without surface nitridation prior to HfO2 deposition,the EOT of HfN/HfO2 gate stack has been successfully scaled down to less than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.The last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO2 gate dielectric.The excellent thermal stability of the HfN/HfO2 gate stack enables its use in high temperature CMOS processes.The replacement of HfN with other metal gate materials with work functions adequate for n- and p-MOS is facilitated by a high etch selectivity of HfN with respect to HfO2,without any degradation to the EOT,gate leakage,or TDDB characteristics of HfO2.     

Mobility measurement and degradation mechanisms of MOSFETs made with ultrathin high-k dielectrics

Accurate measurements and degradation mechanisms of the channel mobility for MOSFETs with HfO/sub 2/ as the gate dielectric have been systematically studied in this paper. The error in mobility extraction caused by a high density of interface traps for a MOSFET with high-k gate dielectric has been analyzed, and a new method to correct this error has been proposed. Other sources of error in mobility extraction, including channel resistance, gate leakage current, and contact resistance for a MOSFET with ultrathin high-k dielectric have also been investigated and reported in this paper. Based on the accurately measured channel mobility, we have analyzed the degradation mechanisms of channel mobility for a MOSFET with HfO/sub 2/ as the gate dielectric. The mobility degradation due to Coulomb scattering arising from interface trapped charges, and that due to remote soft optical phonon scattering are discussed.     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

Introduction High- k gate dielectrics have been extensivelystudied as alternates to conventional gate oxide( Si O2 ) due to the aggressive downscaling of Si O2thickness in CMOS devices,and hence the exces-sive gate leakage.Hf O2 has emerged as one...     

Impact of boron penetration at P+-poly/gate oxideinterface on deep-submicron device reliability for dual-gate CMOStechnologies

In this paper, we investigate the onset of boron penetration at the P⁺-poly/gate oxide interface. It is found that conventional detection methods such as shifts in flatband voltage or threshold voltage (V_t) and charge-to-breakdown (Q_BD) performance in accumulation mode failed to reveal boron species near this interface. On the contrary, under constant current stressing with inversion mode bias conditions, significantly lower Q_BD and large V_t shift have been observed due to boron penetration near the P⁺-poly/gate oxide interface. These results suggest that onset of boron penetration at the P⁺ -poly/gate oxide interface does not alter fresh device characteristics, but it induces severe reliability degradation for the gate oxide. Tradeoffs of boron penetration and poly depletion are also studied in this work with different combinations of polysilicon thickness, BF₂ implant energy and dose, and the post-implant RTA temperature     

Sub-100 nm Γ-gate MOSFETs with self-aligned drain extensionformed by solid phase diffusion

High performance 60 nm Γ-gate n-MOSFETs have been fabricated. The very fine poly-Si gates were made using deposition and etchback of poly-Si to form a sidewall along the conductive poly-Si/PSG dummy stack. Due to the relatively wide dummy stack, the low gate resistance r_g is independent of the actual gate length; this is especially essential for rf circuits as high gate resistance could severely degrade high frequency performance. The diffusion source, PSG layer underneath the poly-Si, allowed the formation of an ultra-shallow self-aligned drain extension by solid phase diffusion. Together with a steep retrograde channel using indium, good subthreshold characteristics as well as high current drive were obtained     

一种200V/100A VDMOS器件开发

分析了功率MOSFET最大额定电流与导通电阻的关系,讨论了平面型中压大电流VDMOS器件设计中导通电阻、面积和开关损耗的折衷考虑,提出了圆弧形沟道布局以增大沟道宽度,以及栅氧下部分非沟道区域采用局域氧化技术以减小栅电容的方法,并据此设计了一种元胞结构。详细论述了器件制造过程中的关键工艺环节,包括栅氧化、光刻套准、多晶硅刻蚀、P阱推进等。流水所得VDMOS实测结果表明,该器件反向击穿特性良好,栅氧耐压达到本征击穿,阈值电压2.8V,导通电阻仅25mΩ,器件综合性能良好。     

三维圆柱形电荷俘获存储器件的继续微缩对其性能的影响

本文详细地研究了关键尺寸的继续微缩对三维圆柱形无结型电荷俘获存储器器件性能的影响。通过Sentaurus三维器件仿真器,我们对器件性能的主要评价指标进行了系统地研究,包括编程擦除速度和高温下的纵向电荷损失及横向电荷扩散。沟道半径的继续微缩有利于操作速度的提升,但使得纵向电荷损失, 尤其是通过阻挡层的纵向电荷损失,变得越来越严重。栅极长度的继续微缩在降低操作速度的同时将导致俘获电荷有更为严重的横向扩散。栅间长度的继续微缩对于邻近器件之间的相互干扰有决定性作用,对于特定的工作温度及条件其值需谨慎优化。此外,栅堆栈的形状也是影响电荷横向扩散特性的重要因素。研究结果为高密度及高可靠性三维集成优化提供了指导作用。     

Study on the degradation induced by donor interface state in deep-sub-micron grooved-gate P-channel MOSFET’s

The degradation of electrical performance induced by interface states is one main reason for failure occurs in deep-sub-micron MOS devices. Especially for grooved-gate MOS devices, there are a large amount of interface states and flaw formed during the etching of concave. Based on the hydrodynamics energy transport model, using MEDICI simulator, the degradation induced by donor interface states is analyzed for deep-sub-micron grooved-gate PMOSFET’s with different channel doping densities and compared with that of corresponding conventional planar PMOSFET’s. The results also compared with that of degradation induced by acceptor interface states. The simulation results indicate that the degradation induced by same interface state density in grooved-gate PMOSFET’s is larger than that in planar PMOSFET’s, and in both structure devices, the impact of electron donor interface states on device performance is far larger than that of hole donor interface state. This work gives an useful insight of mechanism of hot-carrier degradation for grooved gate MOS devices and lays a solid foundation for grooved gate devices used in deep-sub-micron region VLSI practically.     

4H-SiC隐埋沟道MOSFET迁移率的研究

研究了几种因素对4H-SiC隐埋沟道MOSFET沟道迁移率的影响.提出了一个简单的模型用来定量分析串联电阻对迁移率的影响.串联电阻不仅会使迁移率降低,还会使峰值场效应迁移率所对应的栅压减小.峰值场效应迁移率和串联电阻的关系可用一个二次多项式来准确描述.详细分析了均匀分布和不均匀分布的界面态对场效应迁移率的影响.对于指数分布的界面态,低栅压下界面态的影响基本上可以忽略不计,随着栅压的增加,界面态的影响越来越显著.