A multiconductor transmission line methodology for global on-chip interconnect modeling and analysis

This paper describes a methodology for global on-chip interconnect modeling and analysis using frequency-dependent multiconductor transmission lines. The methodology allows designers to contain the complexity of series impedance computation by transforming the generic inductance and resistance extraction problem into one of per-unit-length parameter extraction. This methodology has been embodied in a CAD tool that is now in production use by interconnect designers and complementary metal oxide semiconductor (CMOS) process technologists.     

A unified RLC model for high-speed on-chip interconnects

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model.     

Well-behaved global on-chip interconnect

Global interconnects have been identified as a serious limitation to chip scaling, due to their latency and power consumption. We demonstrate a scheme to overcome these limitations, based on the utilization of upper-level metals, combined with structured communication architecture. Microwave style transmission lines in upper-level metals allow close-to-velocity-of-light delays if properly dimensioned. As an example, we demonstrate a 480-/spl mu/m-wide and 20-mm-long bus with a capacity of 320 Gb/s in a nearly standard 0.18-/spl mu/m process. The process differs from a standard process only through a somewhat thicker outer metal layer. We further illustrate how "self pre-emphasis" at the launch of a data pulse can be used to double the maximum available data rate over a wire. The proposed techniques are scalable, given that higher level metals are properly dimensioned in future processes.     

Thermal effect analysis of silicon microring optical switch for on-chip interconnect

The silicon microring resonator plays an important role in large-scale, high-integrability modern switching matrixes and optical networks, as silicon photonics enables ring resonators of an unprecedented compact size. But as the nature of resonators is their sensitivity to temperature, their performances are vulnerable to being affected by thermal effect. In this paper, we analyze the dominant thermal effects to the application of silicon microring optical switch. On the one hand we theoretically analyze and experimentally measure the thermal crosstalk among adjacent microring optical switches with different distances, and give possible solutions to minimize the affect of thermal crosstalk. On the other hand we analyze and measure the thermooptic dynamic response of microring switch; the experiment shows for the thermal-tuning that the rising edge is around 2μs, and the falling edge is around 35μs. We give the explanation of the asymmetric rise-time and fall-time.     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

CDMA bus-based on-chip interconnect infrastructure

As technology scales toward deep submicron, the integration of complete system-on-chip (SoC) designs consisting of large number of Intellectual Property (IP) blocks (cores) on the same silicon die is becoming technically feasible. Until recently, the design-space exploration for SoCs has been mainly focused on the computational aspects of the problem. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from computation-based to communication-based designs becomes mandatory. As a result, the communication architecture plays a major role in the area, performance and energy consumption of the overall systems [Pasricha S, Dutt N. On-chip communication architectures: system on chip interconnect. Amsterdam: Elsevier Inc.; 2008, Kim J, Verbauwhede I, Chang MCF. Design of an interconnect architecture and signaling technology for parallelism in communication. IEEE Trans VLSI Syst 2007;15(8):881-94].This article presents a structure of a wrapper as a component of Code Division Multiple Access, CDMA, based shared bus architecture in a SoC. Two types of wrappers can be identified, master and slave. A master wrapper is located between the arbiter and CDMA coded physical interconnect, while a slave connects the CDMA coded bus with memory/peripheral module. In the proposal, only bus lines that carry address and data signals are CDMA coded. We implemented a pair of master-slave wrapper described in VHDL and confirmed its functionality using testbenches. Also we synthesized wrappers using a Xilinx Spartan and Virtex devices to determine resource requirements in respect to a number of equivalent gates, communication bandwidth, latency and power consumption. Specifically we involved a Design_Quality, DQ, metric for wrapper performance evaluation. A pair of master-slave wrapper seems to occupy appropriate space, in average 2000 equivalent gates, considering CPU cost of about 30,000 gates, what is less than 8% of hardware overhead per CPU. We also present experimental results which show that benefits of involving CDMA coding relates both to decreasing a number of bus lines and accomplishing simultaneous multiple master-slave connections at relatively low-power consumption and high communication bandwidth. Convenient range indices R_W and R_R to determine data transfer rate for Write and Read operations in multiprocessor bus systems that use TDMA and CDMA data transfer techniques. The obtained results show that increased data transfer latencies involved by CDMA data transfer are compensated by simultaneous master-slave transfers.     

Shielding effect of on-chip interconnect inductance

Interconnect inductance introduces a shielding effect which decreases the effective capacitance seen by the driver of a circuit, reducing the gate delay. A model of the effective capacitance of an RLC load driven by a CMOS inverter is presented. The interconnect inductance decreases the gate delay and increases the time required for the signal to propagate across an interconnect, reducing the overall delay to drive an RLC load. Ignoring the line inductance overestimates the circuit delay, inefficiently oversizing the circuit driver. Considering line inductance in the design process saves gate area, reducing dynamic power dissipation. Average reductions in power of 17% and area of 29% are achieved for example circuits. An accurate model for a CMOS inverter and an RLC load is used to characterize the propagation delay. The accuracy of the delay model is within an average error of less than 9% as compared to SPICE.     

Optimum voltage swing on on-chip and off-chip interconnect

Reduced voltage swings are often used for saving power on interconnects. In this paper, we demonstrate the existence of an optimum voltage swing for minimum power consumption, for on-chip and off-chip interconnects. Actual values of optimum swings and corresponding power savings for high performance interconnects are estimated     

Predictions of CMOS compatible on-chip optical interconnect

Interconnect has become a primary bottleneck in the integrated circuit design process. As CMOS technology is scaled, the design requirements of delay, power, bandwidth, and noise due to the on-chip interconnects have become more stringent. New design challenges are continuously emerging, such as delay uncertainty induced by process and environmental variations. It has become increasingly difficult for conventional copper interconnect to satisfy these design requirements. On-chip optical interconnect has been considered as a potential substitute for electrical interconnect. In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-the-art optical technologies. Electrical and optical interconnects are compared for various design criteria based on these predictions. The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one-tenth of the chip edge length at the 22 nm technology node.     

Sensitivity analysis of multiconductor transmission lines andoptimization for high-speed interconnect circuit design

Sensitivity analysis of multiconductor transmission lines is derived from a new, all-purpose multi-conductor transmission line model in both frequency domain and time domain. Computer implementation of this new model as well as the sensitivity analysis has been completed. It enables efficient, accurate simulations of interconnect circuit responses as well as sensitivity analysis with respect to both electrical and physical transmission line parameters. By applying sensitivity analysis to high-speed interconnect circuit design, design variables are optimized to achieve simultaneous minimization of crosstalk, delays and reflections at desired nodes in the circuit without violating any indispensable design rules. Numerical examples are presented to demonstrate the validity of the proposed sensitivity analysis and illustrate its application to the optimization of high-speed interconnect circuit design     

Lifetime RC time delay of on-chip copper interconnect

Increasing resistance and RC time delay induced by an oxidation in a copper line during its lifetime may limit copper-based metallization for technologies with critical dimension. Based on the mechanisms of resistance, constriction resistance and material diffusion, two dynamic models to access lifetime behavior of resistance and RC time delay were developed and discussed. These models also provide a means to gain insight into the correlation between the resistance and RC time delay of copper interconnect and such key variables as feature dimension, operating condition, and oxidation     

一种新的集成电路互连线串扰模型和估计公式

建立了一个考虑分布电阻,分布电容的互连线混П模型,在这个模型的基础上,分析了终端在最坏条件下的串扰响应,并推导了三阶S域系数的精确表达式,最终,获得了一个新的互连线串扰响应的估计公式,通过与SPICE模拟的结果相比较,该文的模拟结果非常接近实际电路的串扰响应,与相关文献所发表的结果相比较,该模型更符合实际情况,结果也更精确。     

Process variation robust current-mode on-chip interconnect signaling scheme

We propose a novel bias circuit, which can help a promising current-mode signaling （CMS） scheme （CMS-bias） enhance the robustness against process variation but consume less energy than the original bias circuit in this scheme. Monte Carlo and process corner analysis are carried out using HSPICE in the Global Foundry 0.18 μm process. Monte Carlo analysis shows that the CMS-bias with proposed bias circuit （CMS-proposed） and the CMS-bias with original circuit （CMS-original） have the same robustness against the variation, but the former offer a 9% reduction in power consumption. The process corner analysis shows that the average power and delay of the CMS-proposed don＇t change much in different process corners, especially in FS and SF corner. In addition, parameter sensitivity analysis shows that the process variation in long wires has little influence on the delay of the CMS scheme, but the variation in the effective length of MOSFETs influences the performance of the CMS scheme very much.     

New methodology for combined Simulation of delta-I noise interaction with interconnect noise for wide, on-chip data-buses using lossy transmission-line power-blocks

A new technique is described for reducing computational complexity and improving accuracy of combined power distribution and interconnect noise prediction for wide, on-chip data-buses. The methodology uses lossy transmission-line power-blocks with frequency-dependent properties needed for the multigigahertz clock frequencies. The interaction between delta-I noise, common-mode noise, and crosstalk and their effect on timing is illustrated with simulations using representative driver and receiver circuits and on-chip interconnections.     

Accurate on-chip interconnect evaluation: a time-domain technique

This paper describes an on-chip sampling and measurement technique for accurate (<15 ps) evaluation of interconnect delays and coupled noise. We have used this nonintrusive time-domain technique to extract in situ driver/receiver waveforms, propagation delays, and coupled noise in 120 interconnect structures. The effects studied include multiple AC returns through active devices, gridded planes on adjacent layers, via impedances, variable driver impedances, and noise in bus structures. The results provide a comprehensive evaluation of interconnect delays and noise in a 1.8 V, 0.25 μm process     

Advanced experimental and computational tools for robust evaluation of on-chip interconnect reliability

Two technologies are introduced that, together, provide a platform for robust evaluation of interconnect reliability. One is the DISMAP technology, which provides plots of the displacement and strain fields of cross-sectioned interconnect structures under various loading conditions. Measurements provided by DISMAP reveal how multilevel-interconnect structures interact structurally, for example what type of strain fields exist during thermal cycling. A complimentary technology, known as probabilistic analysis, is also described and applied using the NESSUS software. Probabilistic analysis combines statistical uncertainty with physics-based models to predict the probability of failure and also to reveal the relative importance of the various uncertainties associated with interconnect manufacturing. By comparing the predictions of physical models to DISMAP measurements, the validity of those models are evaluated.     

CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects

This paper provides a comparative study of the low-voltage signaling methodologies in terms of delay, energy dissipation, and energy delay product (energy×delay), and sensitivity technology process variations, and noise. We also present the design of two symmetric low-swing driver-receiver pairs for driving signals on the global interconnect lines. The key advantage of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. The proposed signaling schemes were implemented on 1.0 V CMOS technology, for signal transmission along a wire-length of 10 mm. When compared with other counterpart symmetric and asymmetric low-swing signaling schemes, the proposed schemes perform better in terms of delay, energy dissipation and energy×delay.     

Statistical signal integrity analysis and diagnosis methodology for high-speed systems

This paper discusses an efficient statistical analysis methodology for system-level signal integrity analysis. In the proposed method, statistical variations of the design and operational parameters are mapped to system performance through simulations based on orthogonal Taguchi arrays. Using the sensitivity functions derived from these simulations, statistical distributions of the performance measures are computed. The sensitivity functions and probability distributions of the design parameters are utilized as a diagnosis tool to estimate the design parameters of a system for a given measured performance. The statistical methodology is applied for design space exploration to improve system performance. For demonstrating the concept, a source synchronous memory bus and a peripheral input-output (I/O) bus have been analyzed under design and operational variations.     

Permalloy loaded transmission lines for high-speed interconnect applications

The mutual inductance and self-inductance of global interconnects are important but difficult to extract and model in deep submicrometer very large scale integration (VLSI) designs. The absence of effective mutual magnetic field shielding limits the maximum unbuffered interconnect line length. In this paper, we propose and demonstrate that permalloy-loaded transmission lines can be used for high-speed interconnect applications to overcome these limitations. Permalloy films were incorporated into planar transmission lines using a CMOS-compatible process. The line characteristics show that eddy-current effects are the limiting factors for the high-frequency permalloy applications when ferromagnetic resonance are restrained through geometry design. Patterning permalloy films effectively extends their application to above 20 GHz. The line characteristic impedances are about /spl sim/90 /spl Omega/. Under 50 mA dc current biases, the line parameters did not change much. Moreover, the patterned permalloy reduces the magnetic field coupling between two adjacent transmission lines by about 10 dB in our design. The demonstrated operation frequency range, current carrying capability and magnetic field shielding properties indicate that the permalloy loaded lines are suitable for high-speed interconnect applications in CMOS technologies.     

An on-chip, interconnect capacitance characterization method withsub-femto-farad resolution

A simple, accurate method of measuring interconnect capacitances is presented. The test structure has excellent resolution, needs only DC measurements, and is compact enough for scribe-line implementation. These qualities make it suitable for measurement-based, interconnect capacitance characterization in a comparable fashion to current characterization efforts for MOSFET devices. The entire characterization scheme is demonstrated for a production 0.5 μm, three-level metal technology. The method not only provides an accurate assessment of actual capacitance variation but provides valuable feedback on the variability of physical parameters such as interlevel dielectric (ILD) thickness and drawn width reductions for process control as well