Simulation of ZnO diodes for application in non-volatile crossbar memories

As passive crossbar memories contain no amplifying/signal restoring components, their scalability, reliability and speed depends exclusively on the quality of diodes, fuse/antifuse elements and interconnections that constitute them. This paper presents a computational study of ZnO-based Schottky diodes which are thought to be a good candidate for the junction of a crossbar memory, mainly due to their limited thermal budget which guarantees the compatibility with Silicon technology. The simulation shows that the diode characteristics are indeed suitable for their use as junctions. A circuit level simulation demonstrates that optimized ZnO devices would allow the realization of many-megabit memory arrays.     

Interaction of Ir and IrO2 thin films with polysilicon,W and WSIx

Abstract

Ir and IrO₂ thin films have been identified as potential electrode materials for ferroelectric capacitors. These electrodes have shown excellent electrical characteristics. The integration of ferroelectric capacitors into memory cell requires the bottom electrode material to be placed directly over a contact plug. This paper studies the interaction of Ir and IrO₂ with commonly used plug materials such as polysilicon, tungsten (W), and tungsten silicide (WSi_x) after a post-deposition annealing at 800°C. Film properties such as composition, resistivity, crystallinity, adhesion, and micro-structure have been examined before and after anneal. The results show that W is a possible plug material for Ir electrode; while polysilicon and WSi_x are potential candidates if IrO₂ electrodes are used.     

The Effects of Integration Processes on Properties of One Transistor MFMPOS Memory Devices

Integration processing of one-transistor memory devices deals with the following issues: film quality of ferroelectric materials, integration process induced damages such as etching and forming gas annealing damage of ferroelectric materials, the alignment for devices. In order to make high quality one-transistor memory devices, integration processes including nitride gate replacement, oxide trench etching structures, selective deposition, etc. have been investigated for fabrication of one transistor MFMPOS (M: Metal, F: Ferroelectrics, M: Metal, P: polysilicon, O: oxide, S: silicon) memory devices. The integration processes for one transistor memory device have also been optimized to reduce process-induced damages. Based on the experimental results, MOCVD selective deposition can make higher quality patterned ferroelectric thin films, damascene structure with CMP processes can reduce the etching damages. Therefore, the high quality one transistor MFMPOS memory devices have been made.     

Optimized electrical properties of (Bi 1/2 K 1/2 )TiO 3 - bi(Mn 2/3 Sb 1/3 )O 3 lead-free ceramics in mixing phase region

A new lead-free (1-x)(Bi1/2K1/2)TiO3-xBi(Mn2/3Sb1/3)O3 (BKT-BMS) piezoelectric ceramics were prepared by conventional solid-state route. The experiments show that the addition of BMS induces the occurrence of a mixed tetragonal and pseudocubic phases, and the fraction of tetragonal to pseudocubic phases closes to 50:50 around the composition x = 0.015, at where the dielectric, ferroelectric and piezoelectric properties is optimized. It is highlighted that the Td for the composition x = 0.015 keeps at an adequately-high level around 205 °C. All these competitive properties of the composition x = 0.015 demonstrate the potential application for lead-free piezoelectric ceramics over a broad temperature range.     

LiNi1/3Co1/3Mn1/3O2的蔗糖改性研究

首次采用一种固相自引发基团置换反应法制备了蔗糖改性的LiNi1/3Co1/3Mn1/3O2材料.采用X射线衍射(XRD)、场发射扫描电镜(SEM)技术对产物的结构和形貌进行了表征,同时对其电化学性能进行了检测.结果表明,在前驱体中加入少量的蔗糖可以有效改善LiNi1/3Co1/3Mn1/3O2材料的微观结构和电化学性能.在3～4.3 V的充放电电压区间内.添加质量分数3%蔗糖所制备的LiNi1/3Co1/3Mn1/3O2材料显示出最高的初始放电比容量0.1 C达到183 mAh/g.     

新型锂离子电池正极材料LiMnBO3的制备及其性能

以Li2CO3,MnO2和H3BO3为原料,在烧结温度大于800℃时得到了具有六方结构的单相LiMnBO3.充放电测试结果表明:加入高比表面积的碳黑和机械球磨使其比容量和循环性能得到很大改善,但充放电电流的大小会影响其循环性和比容量.800℃烧结温度下得到的LiMnBO3在电流密度为10 mA/g和20 mA/g时得到的首次放电比容量分别为82.5 mAh/g和81.8 mAh/g,循环25周后容量的保持率分别为74.7%和66.9%.850℃下得到的LiMnBO3在10 mA/g的电流密度下首次放电比容量为62.9 mAh/g,第九个循环后比容量仅为29.7 mAh/g.扫描电子显微镜(SEM)测试结果显示,烧结温度为850℃时所得产物的粒径明显增大,这是造成其容量衰减严重的主要原因.     

Write/erase cycling endurance of memory cells with SiO/sub 2//HfO/sub 2/ tunnel dielectric

The write/erase cycling endurance of low voltage floating-gate memory cells programmed and erased by tunneling through a SiO/sub 2//HfO/sub 2/ dual layer tunnel dielectric stack is investigated. The use of fixed single pulse program and erase conditions leads to fast shifting (after /spl sim/1000 cycles) of the threshold voltage window, so that only a limited number of write/erase cycles can be achieved. Increasing the write and erase duration quickly leads to an excessive erase time so that a different erase method has to be used. Improvement of the erase behavior and cycling endurance has been obtained by a combination of two methods. Inclusion of soft write pulses between the erase pulses reduces the amount of charge trapped in the tunnel dielectric and therefore limits the increase in erase time. Also, the erase voltage can progressively be raised in order to further limit the erase time, leading to an endurance of 10 000 cycles on the considered cells. When combining the SiO/sub 2//HfO/sub 2/ stack with channel hot electron injection so that tunneling is only required in one direction, 100 000 write/erase cycles are demonstrated with minimal change of the memory window.     

The equivalent circuits for polaronic relaxation: Taking the LaNi3/4Mo1/4O3 as a model sample

We herein discuss the equivalent circuits for polaronic relaxation based on the results of the low-temperature dielectric properties of LaNi_3/4Mo_1/4O₃. The ceramic samples were prepared via solid-state reaction route. The dielectric properties were investigated in the temperature range from 103 K to 330 K and the frequency range from 20 Hz to 10 MHz. Our results showed that the Debye-like relaxation found in the sample was related to be a polaronic relaxation caused by localized carriers. At low enough temperatures below 103 K, the carriers were strictly confined and the equivalent circuit for impedance spectra was an ideal capacitor. At the temperatures around room temperature, the carriers can hop between spatially fluctuating lattice potentials, the circuit of R???CPE (R?=?resistance, CPE?=?constant phase element) was found to be the better model to describe the impedance data.     

多晶硅还原炉的电器设备

目前,国际上多晶硅的生产,工艺大多采用改良西门子法,其关键设备为还原炉：本文介绍了国内常用的12对多晶硅棒还原炉之国产主要电器设备,并根据多晶硅生产的流程和工艺,说明选择这些电器设备参数的原则和依据,着重介绍了生产电子级多晶硅用的高压启动方式,以及可控硅调功器“拼波”的原理.     

Study of fluctuations in advanced MOSFETs using a 3D finite element parallel simulator

Two important new sources of fluctuations in nanoscaled MOSFETs are the polysilicon gates and the introduction of high-κ gate dielectrics. Using a 3D parallel drift-diffusion device simulator, we study the influence of the polycrystal grains in polysilicon and in the high-κ dielectric on the device threshold for MOSFETs with gate lengths of 80 and 25 nm. We model the surface potential pinning at the grain boundaries in polysilicon through the inclusion of an interfacial charge between the grains. The grains in the high-κ gate dielectric are distinguished by different dielectric constants. We have found that the largest impact of the polysilicon grain boundary in the 80 nm gate length MOSFET occurs when it is positioned perpendicular to the current flow. At low drain voltage the maximum impact occurs when the grain boundary is close to the middle of the gate. At high drain voltage the impact is stronger when the boundary is moved toward the source end of the channel. Similar behaviour is observed in the 25 nm gate length MOSFET.     

温度对光伏电池转换特性影响的理论及实验研究

根据光伏电池的转换特性,详细分析温度对光伏电池开路电压、短路电流、填充因子及转换效率的影响。并设计测试平台,对多晶硅光伏电池实际输出转换效率的温度特性进行了实验研究。结果表明,硅光伏电池输出开路电压随温度升高的减少率约为-2.3mV/K,理想填充因子随温度升高的减少率约为-4.5×10-4/K,短路电流随温度增加而增大,其随温度升高的增加率约为1.21mA/K。总体而言,光伏电池转换效率随温度增加而减少。同时,实验结果也证明多晶硅光伏电池实际输出效率随其温度升高的减少约为-0.22%/K,实验结果与理论分析基本一致。研究结果为光伏系统的优化设计提供了理论及实验基础。     

Comparative study on the spectroscopic properties of Nd:GdVO/sub 4/ and Nd:YVO/sub 4/ with hybrid process

We have proposed a hybrid procedure for determining spectroscopic parameters for uniaxial solid-state laser crystals. Using our procedure, the spectroscopic properties of Nd:GdVO/sub 4/ were evaluated and compared to those of Nd:YVO/sub 4/. As a result, the peaks of absorption and stimulated emission cross sections of Nd:GdVO/sub 4/ in /spl pi/-polarization were determined to be 2.6 and 10.3/spl times/10/sup -19/ cm/sup 2/, respectively, and were smaller than those of Nd:YVO/sub 4/. On the other hand, the fluorescence lifetime of 1 at% Nd:GdVO/sub 4/ was evaluated to be 83.4 /spl mu/s, and was similar to 84.1 /spl mu/s of 1 at% Nd:YVO/sub 4/. Therefore, the product of stimulated emission cross section and fluorescence lifetime (/spl sigma//sub em//spl tau//sub f/ product) of Nd:GdVO/sub 4/ was smaller than that of Nd:YVO/sub 4/ under 1 at% of Nd/sup 3+/ doping concentration. The radiative lifetime of spontaneous emission of Nd:GdVO/sub 4/ was 168 /spl mu/s and was 1.9 times longer than that of Nd:YVO/sub 4/. Because of the low value of radiative quantum efficiency of Nd:GdVO/sub 4/ (50%), careful cavity design is required for creating a well performing solid-state laser with Nd:GdVO/sub 4/, based on the larger /spl sigma//sub em//spl tau//sub f/ product rather than the /spl sigma//sub em//spl tau//sub f/ product of Nd:YAG.     

不同方法合成LiVPO4F/C的电化学性能研究

以葡萄糖、NH4H2PO4、V2O5和LiF为原料,分别通过液相法和固相法合成了锂离子电池正极材料LiVPO4F/C复合材料,并通过X-射线衍射(XRD)、扫描电镜(SEM)及电化学测试技术对复合材料的结构、形貌及电化学性能进行了表征。结果表明,两种方法所合成复合材料均由三斜结构的LiVPO4F与碳组成;液相法所合成的材料首次放电比容量分别为133.7(0.2 C)、124.9 mAh/g(0.5 C)和118.7 mAh/g(1 C),明显高于相同测试条件下固相法所合成材料的首次放电比容量[131.2(0.2 C)、121.4 mAh/g(0.5 C)和104.9 mAh/g(1 C)],并且液相法合成的复合材料循环性能优于固相法合成的复合材料;液相法合成的LiVPO4F/C复合材料具有良好的循环性能和倍率性能,其2 C和5 C的放电比容量分别高达114 mAh/g和98 mAh/g,循环50次后,容量损失率均小于1%。     

Characterization of Au/Pb(Zr0.96Ti0.04)O3/Al2O3/Si antiferroelectric field-effect transistors for memory application

Polarization-voltage (P-V) hysteresis loops and polarization retention were studied for Au/Pb(Zr_0.96Ti_0.04)O₃/Al₂O₃/Pt antiferroelectric capacitors with different Al₂O₃ layer thicknesses. The high-field ferroelectric phase after poling can be pertained to zero external field with the choice of an appropriate Al₂O₃ layer thickness. At the same time, a strong depolarization field across the Al₂O₃ layer is generated with the direction opposite to the field across the Pb(Zr_0.96Ti_0.04)O₃ layer. The depolarization-field direction can be reversed with the domain switching of the high-field ferroelectric phase, possessing the potential application of antiferroelectric memories. A large memory window of 10 V was observed for Au/Pb(Zr_0.96Ti_0.04)O₃ (50 nm)/Al₂O₃ (6.3 nm)/n-Si (100) field-effect transistors, as confirmed from the capacitance sweeping under voltages between ?19 and +19 V. The high/low capacitance ratio is over 8:1, and the ratio remains stable with time over 4 h after programming voltage of ±19 V at 80°C, in suggestion of the excellent retention of the memory.     

Reliability of pFET EEPROM with 70-/spl Aring/ tunnel oxide manufactured in generic logic CMOS Processes

We investigate the reliability of pFET-based EEPROMs with 70-/spl Aring/ tunneling oxides fabricated in standard foundry 0.35-/spl mu/m, 0.25-/spl mu/m, and 0.18-/spl mu/m logic CMOS processes. The floating-gate memory cell uses Fowler-Nordheim tunneling erase and impact-ionization generated hot-electron injection for programming. We show that charge leakage is dominated by the leakage through interlayer dielectrics. We propose a retention model and show the data retention lifetime exceeds 10 years. These results demonstrate the feasibility of producing nonvolatile memory using standard logic processes that have a 70-/spl Aring/ oxide.     

Electrical characteristics of Pt-SBT-Polysilicon (MFIP) capacitors with yttrium oxide as the buffer layer

Abstract

MFIS structures with Strontium Bismuth Tantalate (SBT) as the ferroelectric thin film and yttrium oxide as the buffer layer have been fabricated on polysilicon layer as well single crystal silicon. Yttrium oxide film was deposited by electron beam evaporation and SBT was deposited by spin on MOD technique. Preliminary analysis of capacitance vs voltage (C-V) curve shows hysteresis and the direction of hysteresis corresponds to ferroelectric polarization. For an applied DC bias of ± 5 V, the C-V curve shows a memory window of ± 2 V.     

DESIGN OF A MULTI-LEVEL/ANALOG FERROELECTRIC MEMORY DEVICE

ABSTRACT

Increasing the memory density and utilizing the novel characteristics of ferroelectric devices is important in making ferroelectric memory devices more desirable to the consumer. This paper describes a design that allows multiple levels to be stored in a ferroelectric based memory cell. It can be used to store multiple bits or analog values in a high speed nonvolatile memory. The design utilizes the hysteresis characteristic of ferroelectric transistors to store an analog value in the memory cell. The design also compensates for the decay of the polarization of the ferroelectric material over time. This is done by utilizing a pair of ferroelectric transistors to store the data. One transistor is used a reference to determine the amount of decay that has occurred since the pair was programmed. The second transistor stores the analog value as a polarization value between zero and saturated. The design allows digital data to be stored as multiple bits in each memory cell. The number of bits per cell that can be stored will vary with the decay rate of the ferroelectric transistors and the repeatability of polarization between transistors. It is predicted that each memory cell may be able to store 8 bits or more. The design is based on data taken from actual ferroelectric transistors. Although the circuit has not been fabricated, a prototype circuit is now under construction. The design of this circuit is different than multi-level FLASH or silicon transistor circuits. The differences between these types of circuits are described in this paper. This memory design will be useful because it allows higher memory density, compensates for the environmental and ferroelectric aging processes, allows analog values to be directly stored in memory, compensates for the thermal and radiation environments associated with space operations, and relies only on existing technologies.     

Mg2+不同取代位对LiFePO4/C性能的影响

以蔗糖为碳源,用高温固相法制备了Li0.98Mg0.02FePO4/C、LiFe0.98Mg,0.02PO4,/C和不确定掺杂位的样品LiFePO/C+Mg2+的正极材料.用XRD,SEM、恒流充放电测试、循环伏安和交流阻抗谱方法,研究了样品的结构、形貌及电化学性能.研究发现,样品均为单一规则的橄榄石型的LiFeP0,...     

A manual/automatic synchronization circuit for a 37.5 MVAsteam-turbine-driven generator

The critical parameters in synchronizing a synchronous generator to an electrical system are delta phase angle, delta frequency, and delta voltage magnitude. A manual/automatic synchronization circuit has been designed for a 37.5 MVA generator with protection for all three critical synchronizing parameters. The manual/automatic synchronizing circuit uses triple redundant protective levels for both the manual and automatic circuits. The first and second protective levels are shared by both circuits. These protective levels are a solid-state automatic synchronizing relay in tandem with a solid-state synchronisation check relay. An operator/synchroscope provides the third protective level for the manual circuit, while a microprocessor-based governor provides the third protective level for the automatic circuit. The philosophy, design, and operation of this manual/automatic synchronization circuit are reviewed     

All-optical synchronization and mode locking of solid-state lasers with nonlinear semiconductor Fabry-Perot mirrors

The dynamics of laser oscillators can be directly accessed by modulating the intracavity losses. The authors present a new approach of optically driven loss modulation by means of a nonlinear semiconductor mirror based on a Fabry-Pe/spl acute/rot structure [Fabry-Pe/spl acute/rot modulator (FPM)]. The modulation depth of this device can be several percent and the response time is dominated by the recombination time of the generated free carriers inside the semiconductor, which can be reduced by ion implantation. This paper reviews the design of the FPMs and their optical characterization via spectrally resolved two-color pump-probe spectroscopy. Applications of the FPM are the synchronization of the pulse trains of independent mode-locked laser oscillators. The authors demonstrate the synchronization of a ps-Nd:YVO/sub 4/ laser to a fs-Ti:sapphire laser in a master-slave configuration and show experiments on the carrier-envelope phase relationship between the two synchronized pulse trains. Finally, they show that it is possible to actively mode lock a solid-state laser by an optically driven FPM. The resulting pulsewidths of the actively mode-locked Nd:YVO/sub 4/ laser are as short as 6 ps, which is comparable to passively generated pulses.