Analysis of capacitance and transconductance frequency dispersions in MESFETs for surface characterization

A theoretical model is developed for capacitance and transconductance frequency dispersion in MESFETs at low drain bias and is compared with experimental data obtained on commercial and special devices. It is shown that the results are consistent with a model in which the surface states have a density N_SS in the range of 10¹³ cm⁻² eV⁻¹ and are distributed over a depth of approximately 100 Å below the surface. It is found that a small N_SS contributes to an increase of the g_m dispersion and that the dispersion is minimized in recessed gate structures. Finally it is emphasized that g_m frequency measurements are very convenient for surface characterization and mostly for the evaluation of the spatial distribution of the interface traps when other techniques are inoperative.     

The effect of an interfacial layer on minority carrier injection in forward-biased silicon Schottky diodes

It is shown that the degree of minority carrier injection in Au-Si junctions can be substantially increased by the inclusion of a thin interfacial layer between the metal and the semiconductor. When a forward voltage is applied to the junction, a part of this voltage is developed across the interfacial layer. This favours the reduction of the barrier height to minority carriers, which tunnel from the metal into the semiconductor. The minority carrier injection current increases at the expense of the majority carrier current.For a given oxide thickness, γ(= J_minority/J_tot) increases with forward bias, approaching a saturation value for a few volts applied to the junction. For a given voltage, γ also shows a variation with interfacial layer thickness, δ, and the present results indicate that an oxide thickness can be chosen to optimise γ. In the case of a gold-silicon junction with an insulating layer of thermally-grown oxide, as δ is increased to 40 Å, the saturation value of γ increased from $\text{10}{}^{\mathrm{?4}}\text{for δ = 10}\text{A}\text{?}$ through a maximum of 2 × 10^?1 for δ ? 30 Å. For oxides prepared by r.f. sputtering, the maximum value of γ is 10^?1 and occurs for δ ? 80 Å.These results are of considerable importance in the improvement of injection luminescence in metal-semiconductor diodes.     

Interface state density in Au-nGaAs Schottky diodes

A method for determining the surface state density in Schottky diodes taking into account both I–V and C–V data while considering the presence of a deep donor level is presented. The model assumes that the barrier height is controlled by the energy distribution of surface states in equilibrium with the metal and the applied potential and does not include, explicitly, an interfacial layer. The model was applied to extract interface state densities of Au-nGaAs guarded Schottky diodes fabricated from bulk and VPE (100) GaAs with carrier conentrations between 3 × 10¹⁵ and 8 × 10¹⁶ cm^?3. These diodes exhibited ideality (n) factors of approximately 1.02 and room temperature saturation current densities ～10^?8 A/cm². This model is in substantial agreement with forward bias measurements over the 77–360°K temperature range investigated, in that a temperature-independent energy distribution of interface states was obtained. In reverse bias the interface state model is most valid with the higher carrier concentration material and at high temperature and low bias voltage. Typical interface state densities from 0.07 eV above the zero bias Fermi level to 0.01 eV below the Fermi level were 2 × 10¹³ cm^?2 eV^?1. The validity of the model under reverse bias is restricted by a non-thermionic reverse current, thought to be enhance field emission from traps.     

Recombination beneath ohmic contacts and adjacent oxide covered regions

By modelling a contact as a Schottky barrier space-charge region it is possible to calculate the effective surface-recombination velocity which it displays. Such a model is of use in analysing the behaviour of thin emitter regions, and of contacts, or oxide covered regions in the extrinsic base of I²L vertical transistors.It is shown necessary to take account of both the doping and electric field dependence of the carrier mobility as well as the exact form of the potential at the boundary between the space-charge region and the substrate.The values of surface recombination velocity predicted by the model are in fair agreement with available data, and a tentative model for recombination beneath an oxide is proposed.     

Effects of high field stresses on threshold voltage of CMOS transistors

In this paper, the threshold voltage instabilities of CMOS transistors under gate bias stress at high gate oxide electric fields have been investigated. It is shown that in presence of the negative gate bias stress threshold voltage of n-channel MOSTs decreases, while threshold voltage of p-channel MOSTs increases. These results are explained by positive fixed oxide charge increase due to hole tunneling from the silicon valence band into oxide hole traps. On the other hand, it is shown that in the presence of the positive gate bias stress threshold voltage of n-channel MOSTs decreases at the beginning as well, but after a certain time period starts to increase, while threshold voltage of p-channel MOSTs continuously increases. The initial threshold voltage behaviour is explained by positive fixed oxide charge increase as well; however, in this case it is caused by the electron tunneling from oxide electron traps into oxide conduction band. The later threshold voltage increase of n-channel MOSTs is explained by surface state charge increase due to tunnel current flowing through the oxide.     

Evaluation of different oxidation methods for silicon for scanning capacitance microscopy

Different oxides, namely, native, thermal, and wet-chemical (H₂SO₄+H₂O₂ based) oxides on Si are evaluated in the context of scanning capacitance microscopy (SCM). The samples investigated consisted of uniformly doped Si substrates and p-type epitaxial doping-staircase structures with concentrations ranging from 5×10¹⁴ to 2×10¹⁹ cm⁻³. The bias for which the SCM signal (dC/dV) is maximised for the lowest doped region was used for comparing the different oxidation methods. It is shown that for a better evaluation of the surface oxide properties, it is essential to obtain dC/dV curves for a sufficiently large doping range. Best results in terms of low values of flat-band voltages (1 V), uniformity, and consistency across a large doping range were obtained for the wet-chemical oxide. For the native oxide case, the difference in the dC/dV peak bias values obtained at regions doped to 5×10¹⁴ to 10¹⁷ cm⁻³ was anomalously large and suggests appreciable distortion of the dC/dV curves. For the same oxidation procedure the full-width at half-maximum of the dC/dV curve obtained on the cleaved surface is typically 2 times larger than that on the planar (1 0 0) surface. It is most likely that interface states are responsible for the observed distortion.     

Low operational voltage and high performance organic field effect memory transistor with solution processed graphene oxide charge storage media

Low voltage organic field effect memory transistors are demonstrated by adapting a hybrid gate dielectric and a solution processed graphene oxide charge trap layer. The hybrid gate dielectric is composed of aluminum oxide (AlO_x) and [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) plays an important role of both preventing leakage current from gate electrode and providing an appropriate surface energy to allow for uniform spin-casting of graphene oxide (GO). The hybrid gate dielectric has a breakdown voltage greater than 6 V and capacitance of 0.47 μF/cm². Graphene oxide charge trap layer is spin-cast on top of the hybrid dielectric and has a resulting thickness of approximately 9 nm. The final device structure is Au/Pentacene/PMMA/GO/PhO-19-PA/AlO_x/Al. The memory transistors clearly showed a large hysteresis with a memory window of around 2 V under an applied gate bias from 4 V to −5 V. The stored charge within the graphene oxide charge trap layer was measured to be 2.9 × 10¹² cm⁻². The low voltage memory transistor operated well under constant applied gate voltage and time with varying programming times (pulse duration) and voltage pulses (pulse amplitude). In addition, the drain current (I_ds) after programming and erasing remained in their pristine state after 10⁴ s and are expected to be retained for more than one year.     

Measurements on depletion-mode field effect transistors and buried channel MOS capacitors for the characterization of bulk transfer charge-coupled devices

The properties of bulk transfer charge-coupled devices (BCCD's) may be characterized from measurements obtained using MOS capacitors and field effect transistors. Models are presented for the MOS capacitor and field effect transistor for the case where a shallow doped layer of polarity opposite to that of the substrate is incorporated between the oxide and the substrate. These models explain the observed frequency dependence of the capacitance-voltage (C-V) characteristics of these devices.Techniques are presented for determining the impurity profile of the buried layer from the low frequency C-V measurements made on MOS transistors. The majority carrier mobilities in the buried layer and at the surface are measured for the BCCD's and compared to the surface minority carrier mobility measured for the surface channel CCD's. Generation lifetimes at the surface, in the buried layer and in the underlying substrate are determined from capacitance-time (pulse bias C-t) measurements and leakage current measurements of the MOS capacitors and transistors. Methods are demonstrated whereby the depth from the oxide interface of the potential minimum (depth of the buried channel) and its potential can be determined as a function of the various applied biases.     

High-low junctions for solar cell applications

A new theoretical model to calculate the effective surface recombination velocity (S_eff) of a high-low junction with an arbitrary impurity distribution is presented. The model is applied to erfc-diffused pp⁺ junctions using experimental data of bandgap narrowing, lifetime and mobility. Bandgap narrowing is shown to degrade the minority carrier reflecting properties of the high-low junction. Computer results are applied for the design of BSF solar cells and to study other solar cells structures based on high-low junctions.     

A finite-element model and characterization of the p-i-n magnetodiode at microwave frequencies

A finite element, resistive network analog model is presented and applied to p-i-n magnetodiodes at a microwave frequencies. The network analog model is outlined and verified with microwave measurements on a mesa-style p-i-n diode. The microwave measurements, coupled with data obtained by the model, are shown to provide a measure of the ambipolar mobility in the i-region of the semiconductor device. The magnetosensitivity of the magnetodiode as a function of geometry is also discussed.     

InP Schottky contacts with increased barrier height

We present an analysis of Schottky barriers in n-InP made by incorporating a thin native oxide. An oxidation technique using nitric acid under illumination produces an oxide layer with uniform composition distribution within the layer. The growth rate is interpreted as being partially limited by diffusion presumably of oxygen through oxide. The Au Schottky barrier formed on a 40–80 Å thick oxide layer exhibits little degradation of the ideality factor n (1.04 < n < 1.10) and an increase of the barrier height by greater than 0.3 eV, resulting in at least a 10^?4 times smaller reverse leakage current density, compared with conventional Au-InP barriers. The barrier height increase is analysed by a generalised model, and is found to be produced by the existence of fixed negative charges in the oxide layer. From the present analysis, a surface state density of 6.0 × 10¹² cm^?2 eV^?1 and an equivalent surface density of negative charges of 2.8 × 10¹² cm^?2 are determined independently. The origins of these, particularly of the surface states, are considered in relation to the P vacancies at the oxide-InP interface.     

Characteristics of metal/tunnel-oxide/n/p+ silicon switching devices—II: Two-dimensional effects in oxide-isolated structures

Effects of oxide isolation on the two-terminal D.C. characteristics of metal/tunnel-oxide/n/p⁺ silicon switching devices have been studied.Recent experimental results have shown that the switching characteristics are strongly dependent on area, and area-to-perimeter ratio of the device. To carry out a systematic investigation of this phenomenon, the devices in this study were isolated using V-grooves of various areas. For a given tunnel-oxide thickness and area, it was found that the magnitude of the switching voltage and holding current of the device increased with isolation area, whereas the switching current remained essentially constant. Furthermore, it is shown that the switching current is almost completely determined by the characteristics of the tunnel-oxide; in particular, the minority carrier concentration at the SiSiO₂ interface. Physical arguments are presented which adequately explain the observed trends. It is also experimentally shown that both switching current and holding current decrease as the tunnel-oxide thickness is increased.A simple two-dimensional model for the oxide-isolated MISS device is derived which effectively explains the above area-related phenomena. In agreement with experimental results, the model predicts that for a given tunnel-oxide thickness and area, an increase in switching voltage magnitude and holding current will result as the isolated p⁺-n junction area is increased. Calculations based on this model are shown to be in good agreement with experimental data.     

Characteristics of Cr-SiO2-nSi tunnel diodes

The admittance of Cr-SiO₂-nSi tunnel diodes was measured at 195 and 295 K, from which the surface potential ψ_s(V_a) and the energy distribution of the surface states N_ss which communicate with the silicon were determined. By employing these data, the I(V_a) characteristics measured at 77, 195 and 295 K are interpreted as tunneling current consisting of two components. The first is a net electron tunnel current from the Si-conduction band through the oxide into the metal which dominates at room temperature for forward bias V_a greater than 0.4 V. Introducing a simple model of a trapezoidal SiO₂ barrier allows us to calculate the band to band current, resulting in typical values of the barrier height η_o = 0.24 eV and barrier width $\text{d}{}_{\mathrm{o}}\text{= 24}\text{A}\text{?}$. The second component is a net recombination current of electrons from the Si-conduction band into surface states which then tunnel through the oxide into the metal; this component dominates for reverse bias and for small forward bias, especially at low temperatures. It is a current via surface states N_sm which are at the Si-SiO₂ interface but rapidly communicate with the metal, and it is therefore recombination controlled. Together, these components explain the measured bias and temperature dependence of the d.c. current.     

The effect of low-field injection of charge carriers on the electrical properties of the metal-oxide-semiconductor structures

The method of high-frequency capacitance-voltage characteristics was used to study the effect of low-field injection of charge carriers on the electrical properties of metal-SiO₂-Si structures with n- and p-type substrates. It is shown that in all cases of injection (irrespective of the polarity of the voltage at the gate), an effective positive charge is generated in the oxide; after completion of the injection, this charge relaxes with characteristic times that depend on the bias voltage applied to the gate and the type of the metal-oxide-semiconductor structure. In the structures with p-Si substrates, in the case of a positive voltage applied to the gate, a capacitance minimum appeared in the inversion portion of the capacitance-voltage characteristics in the course of injection; this effect became more pronounced as the gate voltage was increased. After the injection, the capacitance gradually approached the initial value (before injection).     

A new model for the thermal oxidation kinetics of silicon

A model is presented which reasons that the thermal oxidation of silicon is surface reaction limited, and that the reaction rate is controlled by the viscous flow of newly forming oxide to accommodate the volume expansion that occurs when silicon oxidizes. The SiO₂ must form at silicon lattice sites and therefore epitaxially. This thermody-namically unstable epitaxial structure reconfigures and this reconfiguration results in an increase of the average viscosity of the oxide. The continual increase of average oxide viscosity accounts for the continual decrease in oxidation rate with time. A mathemat-ical analysis based on this model is used to derive the simple power law x = at^b relating oxide thickness, x, to oxidation time, t which has been shown previously to model phe-nomenologically all of the extant dry oxidation data.¹ The physical significances of the coefficient a and exponent b are obtained by the interpretation of the x vs t data in the literature in terms of this mathematical analysis.     

The effect of current suppression in the pn−n+ diode of integrated injection logic

The j-V characteristics of the pn^?n⁺ diode are derived by combining the different current components in the n^? region of the diode for various bias voltages. For infinitly fast recombination, the expression for the current density as a function of bias reduces to that of a conventional one-dimensional theory. For finite recombination, however, the expression deviates significantly from the usual expression. In fact, contrary to what would be expected from the conventional theory, the current increases as the width of the neutral n^? region increases for a constant bias. Finally the results of the analysis of the pn^?n + diode are applied to an analysis of the current gain in the integrated injection logic (I²L) device. A qualitative discussion of the current gain for the lateral pnp transistor and for that of the vertical npn transistor is given.     

Study of the potential distribution in a forward-biased silicon diode using electrostatic force microscopy

Electrostatic force microscopy was used to study the potential distribution in a forward-biased epitaxial-diffused n ⁺-n-p-p ⁺ silicon diode. Distributions of potential and capacitance were determined across the cleaved surface, which intersected the layers in the diode structure. Variations in the surface potential and capacitance were preliminarily measured with a submicrometer spatial resolution and were used to determine the position and width of the n-p junction; the distribution of applied forward bias in the diode was also assessed. It is shown that an additional potential barrier for injected charge carriers may exist in the vicinity of the n ⁺-n junction in the diode under consideration. For an injection-current density exceeding 100 mA/cm², the voltage drop across this barrier becomes comparable with the voltage variations across the operating n-p junction.     

Finite metal-sheet-resistance in contact resistivity measurements: Application to Si/TiN contacts

The standard transmission line model cannot be applied to evaluate the contact resistivity of thin TiN layers on highly doped p⁺ and n⁺ substrates because the finite sheet resistance of the TiN must be accounted for. We present two ways to include this effect using existing analytical models. The results are shown to agree with measurements where the effect of the finite sheet resistance of TiN is eliminated with a metallic overlayer. With the help of these evaluation techniques, it is shown that the contact resistivity of TiN changes in opposite ways for p⁺ and n⁺Si after vacuum annealing at 600°C for 15 min. This result is consistent with an increase of the barrier height φ_Bn of the contact by ?0.1 V to near midgap value.     

A discrete element small-signal equivalent circuit for forward-biased p+n diodes containing deep levels

A discrete element small-signal equivalent circuit model for p-n diodes containing deep defect levels is developed, by extending an existing model for undamaged devices. With the aid of a simple analytical expression which accurately describes the forward bias d.c. current, the enhanced small-signal conductance due to carrier recombination in the depletion region is included in the model. The influence of trapped charge on the space charge capacitance is incorporated using a simplified version of the analysis of Beguwala and Crowell. The predictions of the model are verified by experimental data from silicon p⁺n diodes, in which deep levels have been induced by electron irradiation. It is shown that the deep level activation energies may be estimated from the forward bias capacitance-voltage characteristics, yielding values which agree well with those obtained by established techniques.