Steady-state characteristics of two terminal inversion-controlled switches

The important fabrication procedures and the direct current-voltage characteristics of metal/conducting “insulator”/semiconductor junction diodes are described. These devices generally have two impedance states. The high impedance state is associated with a steady-state deep depletion of the semi-conductor surface which permits the device to absorb a high voltage. The low-impedance state is associated with a partial inversion of the semiconductor surface which greatly increases the electric field across the insulator, even though only a low voltage exists across the device. The generality of this phenomenon is emphasized by citing results from a wide variety of combinations of insulator materials and semiconductor structures. Uniformity of conductor through the insulator and ruggedness of the device are discussed in detail. The device's I–V characteristics can either be independent or quite sensitive to ambient temperature. The temperature sensitivity is explained by the effects of temperature on those mechanisms which control the formation of inversion layers.     

金属-铁电体-GaN结构研究

以铁电体Pb(Zr0.53Ti0.47)O3取代传统绝缘栅氧化物制备了GaN基金属-绝缘层-半导体(MIS)结构.由于铁电体具有较强的极化电场和高介电常数,GaN基金属-铁电体-半导体(MFS)结构的电容-电压特性与其他GaN基MIS结构相比较得到了显著的提高.GaN基MFS结构中GaN激活层达到反型时的偏压小于5V,这和硅基电子器件和集成电路的工作电压一致,而且结果表明GaN层的载流子浓度比其背景载流子浓度减小了一个数量级.因此,GaN基MFS结构对于GaN基场效应晶体管的实际应用具有重要的意义.     

Investigation on UV photodetector behavior of RF-sputtered ZnO by impedance spectroscopy

Ag/ZnO/Ag thin films representing metal/semiconductor/metal ultraviolet (UV) photodetectors were successfully prepared by RF magnetron sputtering. A UV light emitting diode was used as an illuminating source at 365 nm. The current-voltage characteristics of the device under UV illumination showed an enhancement in the forward current. Device modeling was carried out using impedance spectroscopy. The resistance of the device decreased as the light was switched from dark to UV. Moreover, the device showed further decrease in resistance at a bias voltage of up to 2 V.     

Study and modeling of the transport mechanism in a Schottky diode on the basis of a GaAs semiinsulator

The current through a metal-semiconductor junction is mainly due to the majority carriers. Three distinctly different mechanisms exist in a Schottky diode: diffusion of the semiconductor carriers in metal, thermionic emission-diffusion (TED) of carriers through a Schottky gate, and a mechanical quantum that pierces a tunnel through the gate. The system was solved by using a coupled Poisson-Boltzmann algorithm. Schottky BH is defined as the difference in energy between the Fermi level and the metal band carrier majority of the metal-semiconductor junction to the semiconductor contacts. The insulating layer converts the MS device in an MIS device and has a strong influence on its current-voltage (I-V) and the parameters of a Schottky barrier from 3.7 to 15 eV. There are several possible reasons for the error that causes a deviation of the ideal behaviour of Schottky diodes with and without an interfacial insulator layer. These include the particular distribution of interface states, the series resistance, bias voltage and temperature. The GaAs and its large concentration values of trap centers will participate in an increase in the process of thermionic electrons and holes, which will in turn act on the I-V characteristic of the diode, and an overflow maximum value [NT = 3 × 10²⁰] is obtained. The I-V characteristics of Schottky diodes are in the hypothesis of a parabolic summit.     

A silicon double switching inversion-controlled switch formultiple-valued logic applications

A device with the structure of metal/thin insulator/crystalline silicon (n⁺-p)/thin insulator/metal (MISSIM) has been demonstrated to possess a double switching characteristics, which is expected to generate multiple stable states easier than the conventional resonant tunneling devices with multiple negative resistance for multiple-valued logic applications. Based on current-voltage measurements with or without light irradiation, and under the negative gate-biased condition, the operation mechanism of the MISSIM structure is proposed and illustrated in detail     

Minority carrier MIS tunnel diodes and their application to electron- and photo-voltaic energy conversion—I. Theory

If the insulating layer in a metal-insulator-semiconductor (MIS) diode is very thin ($\text{<60}\text{A}\text{?}$ for AlSiO₂Si), measureable tunnel current can flow between the metal and the semiconductor. If the insulating layer is even thinner ($\text{<30}\text{A}\text{?}$), tunnel currents are so large that they can significantly disturb the semiconductor from thermal equilibrium. Under such conditions, MIS diodes exhibit properties determined by which of the following tunneling processes is dominant; tunneling between the metal and the majority carrier energy band in the semiconductor, between the metal and the minority carrier energy band, or between the metal abd surface state levels. In the present paper, minority carrier MIS tunnel diodes are analysed using a very general formulation of the tunneling processes through the insulator, transport properties in the semiconductor, and surface state effects. Starting from solutions for diodes with relatively thick insulating layers where the semiconductor is essentially in thermal equilibrium, solutions are obtained for progressively thinner insulating layers until non-equilibrium effects in the semiconductor are observed. It is shown that such minority carrier MIS tunnel diodes with very thin insulating layers possess properties similar to p-n junction diodes including exponential current-voltage characteristics which approach the “ideal diode” law of p-n junction theory. The theory adequately describes the observed properties of experimental devices reported in a companion paper. The diodes have application as injecting contacts, as photodiodes or elements of photodiode arrays, and as energy conversion devices employing the electron- or photo-voltaic effects.     

Cryogenic processed metal-semiconductor-metal (MSM) photodetectorson MBE grown ZnSe

Molecular beam epitaxy grown 0.5-μm and 2.0-μm thick undoped ZnSe on semi-insulating (100) GaAs substrates were prepared for metal-semiconductor-metal (MSM) photodetector devices. The MSM photodetectors consisted of interdigitated metal fingers with 2, 3, and 4 μm width/spacing on a wafer. A multilayer resist process was employed using polyimide and SiO₂ thin films before the pattern generation to aid in a special low temperature (LT) lift-off process. Dark current-voltage (I-V), DC photo I-V, high frequency I-V, spectral response, and frequency response techniques were employed for testing the device performance. The cryogenic processed metallization provided an improved interface between metal and semiconductor interface. The breakdown voltage in these devices is dependent on the electrode width/spacing and not on film thickness. Dark current remained at around 1 pA for a bias of ±10 V. The devices exhibited a high spectral responsivity of 0.6 (A/W) at a wavelength of 460 nm at 5 V applied bias. A maximum spectral responsivity of 1 (A/W) at an applied bias of 5 V was obtained in these devices indicating an internal gain mechanism. This internal gain mechanism is attributed to hole accumulation in ZnSe epilayers     

Electronic Contact Deposition onto Organic Molecular Monolayers: Can We Detect Metal Penetration?

Using a semiconductor as the substrate to a molecular organic layer, penetration of metal contacts can be clearly identified by the study of electronic charge transport through the layer. A series of monolayers of saturated hydrocarbon molecules with varying lengths is assembled on Si or GaAs and the junctions resulting after further electronic contact is made by liquid Hg, indirect metal evaporation, and a “ready‐made” metal pad are measured. In contrast to tunneling characteristics, which are ambiguous regarding contact penetration, the semiconductor surface barrier is very sensitive to any direct contact with a metal. With the organic monolayer intact, a metal–insulator–semiconductor (MIS) structure results. If metal penetrated the monolayer, the junction behaves as a metal–semiconductor (MS) structure. By comparing a molecule‐free interface (MS junction) with a molecularly modified one (presumably MIS), possible metal penetration is identified. The major indicators are the semiconductor electronic transport barrier height, extracted from the junction transport characteristics, and the photovoltage. The approach does not require a series of different monolayers and data analysis is quite straightforward, helping to identify non‐invasive ways to make electronic contact to soft matter.     

Analytical investigation of surface potential and related properties of metal/insulator/III–V semiconductor capacitors

An analytical study of the effect of an applied gate bias on the potential and electron density in the semiconductor of metal/insulator/III–V semiconductor (III–V MIS) capacitors is carried out. For this, Poisson's equation is rewritten to a form amenable to analytical study. Si₃N₄ is used as an insulator layer for the MIS capacitors. In order to highlight the advantages of III–V MIS capacitors over metal-SiO₂---Si (MOS) capacitors, the ideal case free from interface traps is considered and theoretical results are obtained also for MOS capacitors. The calculated results strongly demonstrate the superiority of InGaAs MIS and GaAs MIS capacitors to Si MOS capacitors and pinpoint the situation in which the interface states are present.     

New types of metal-insulator-semiconductor switch

Theoretical considerations and experimental results of Metal-Insulator-Semiconductor-Switches (MISS) have been reported in the literature[1–5]. A new model has been recently proposed[6] which explains the current-voltage characteristics by the coupled action of two active devices. In this paper experimental studies are reported on MISS devices with (a) semi-insulating tin oxide and (b) polysilicon layers. The tin-oxide layer has favorable optical properties. In polysilicon samples multiple impedance states have been found. Pulse measurements show, there are three phases associated with the turn-on transient behaviour. The device has higher light sensitivity, higher speed and better I.C. compatibility, than the conventional pnpn diode switch.     

Optimization of II–VI based heterojunctions

The performance of heterojunction devices can be optimized by proper choice of characteristics of the two semiconductors forming the junction and by proper design. One very important element in design is the termination of the active volume of the device with surfaces of low, preferably zero surface recombination velocity. This paper discusses the rules governing the choice of ratios of energy gaps, electron affinities, doping levels, minority carrier lifetimes, lattice constants, etc. for the semiconductors comprising the pair. It also discusses the use of heterostructures to produce the low surface recombination velocity surfaces bounding the active volume of the device. The paper reviews principles of materials science which govern the choice of semiconductors for both the active regions of the device and the heterostructure “encapsulants”. The few attempts to realize electronic structures having the properties required by optimization theory will be described.     

覆有BST膜的半导体功率器件结终端研究

通过一系列的工艺步骤,在半导体功率器件含有场限环(FLR)的结终端上覆盖了一层300 nm厚、介电常数高的钛酸锶钡( BST)膜.对该新型结终端和无BST膜的传统FLR结终端的结构与性能进行了研究比较.结果表明,在覆盖BST膜后,FRL结终端的结构击穿电压提高了50％.这证明BST膜能够提高器件的击穿电压.     

Active devices under CMOS I/O pads

Active devices, including electrostatic discharge protection devices and ring-oscillator circuits, under CMOS I/O pads are investigated in a 130 nm full eight-level copper metal complementary metal-oxide-semiconductor process, using fluorinated silicate glass (FSG) low-k inter-metal dielectric. The high current I-V curve measured in the second breakdown trigger point (V/sub t2/, I/sub t2/) of ESD protection devices under various metal level stack structures, shows that i) I/sub t2/ depends very weakly on the number of metal levels used, as expected given specific junction power dissipation criteria; and ii) V/sub t2/ increases with the number of metal level stacks of I/O pads because of increased dynamic impedance due to the presence of more metal levels, as clarified by a simple RC model. Moreover, no noticeable degradation in the speed of the ring-oscillator circuit, as measured for a variety of test structures subjected to bonding mechanical stress, thermal stress by temperature cycling and DC electrical stress by transmission line pulse, as well as AC electrical stress by capacitive-coupling experiments. Accordingly, active devices under CMOS I/O pads are independent of bonding pad metal level structures.     

Determination of energetic distribution of interface states betweengate metal and semiconductor in sub-micron devices from current-voltagecharacteristics

Density and energetic distributions of interface states between metal-semiconductor rectifying contacts in sub-micron GaAs MESFET and AlGaAs/InGaAs pseudomorphic high electron mobility transistors (HEMT's) have been studied. Electrical properties of the interface states between gate metal and semiconductor in sub-micron devices depend on growth technique, associated processing parameters and surface states on III-V semiconductors. Correlation between nonideal current-voltage (I-V) characteristics and interface states has been established through the bias dependence of ideality factor. Ideality factor determined from I-V characteristics of MESFET and HEMT increases with bias and then decreases after reaching a maximum. A theoretical model based on nonequilibrium approach has been used to determine the density of interface states and their energetic distribution from ideality factor. Essentially, Fermi level shifts with applied bias and Schottky barrier height changes due to trapping and detrapping of electrons by the interface states, and from these changes, density of interface states and their energetic distributions have been determined     

Trapping and reliability issues in GaN-based MIS HEMTs with partially recessed gate

This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al₂O₃. Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator.The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability.     

Semiconductor thickness and back-gate voltage effects on the gate tunnel current in the MOS/SOI system with an ultrathin oxide

The effects of the semiconductor layer thickness and the back-gate voltage on the current-voltage (I-V) characteristics of the MOS/SOI tunnel diode with an aluminum gate and n-type semiconductor layers are theoretically investigated. If the semiconductor thickness is reduced or the back-gate voltage is more negative, the total thermal generation current decreases and the gate-oxide thickness critical for transition from the quasiequilibrium strong inversion state to the nonequilibrium state increases. If the MOS/SOI tunnel diode is in the transition range between the nonequilibrium and quasiequilibrium states, a positive increase of the back-gate voltage V/sub BG/ results in a strong increase of the majority carrier tunnel current. This back-gate effect may be exploited in more functional devices based on the MOS/SOI tunnel diode.     

Practical quantitative scanning microwave impedance microscopy

Scanning microwave impedance microscopy (sMIM) is an emerging technique that has the potential to displace conventional scanning capacitance microscopy (SCM), and other electrical scanning probe microscopy (SPM) techniques, for the profiling of dopants in semiconductor samples with sub-micron spatial resolution. In this work, we consider the practical application of sMIM for quantitative measurement of the dopant concentration profile in production semiconductor devices. We calibrate the sMIM using a doped calibration sample prior to performing the measurements on an “unknown” production device. We utilize nanoscale C-V curves to establish a calibration curve for both n- and p-type carriers in a single reference and apply the calibration curve to an “unknown” device presenting the measurements in units of doping concentration. The calibrated results are compared to SRP measurements on the same area of the device.     

Numerical analysis of heterostructure semiconductor devices

A numerical method for analyzing heterostructure semiconductor devices is described. The macroscopic semiconductor equations for materials with position-dependent dielectric constant, bandgap, and densities-of-states are first cast into a form identical to that commonly used to model heavily doped semiconductors. Fermi-Dirac statistics are also included within this simple, Boltzmann-like formulation. Because of the similarity in formulation to that employed for heavily doped semiconductors, well-developed numerical techniques can be directly applied to heterostructure simulation. A simple one-dimensional, finite difference solution is presented. The accuracy of the numerical method is assessed by comparing numerical results with special-case, analytical solutions. Finally, we apply numerical simulation to two heterostructure devices: the heterostructure bipolar transistor (HBT) and the modulation doped field-effect transistor. The influence of a conduction band spike on the current-voltage characteristics of the HBT emitter-base junction is studied, and the variation with gate bias of the two-dimensional electron gas in a field-effect device is also investigated.     

Current-voltage characteristics of silicon metallic-silicide interfaces

The general quantum and electronic theory of the metal-semiconductor contacts, proposed in previous works, is applied to silicon-metallic silicide interfaces in order to calculate their current-voltage characteristics. The analysis takes into account the actual potential profile due both to the semiconductor depletion layer and to the electric dipole created, around the metal-semiconductor interface (MSI), by the quantum mechanical tunneling of the metal free electrons into the semiconductor and by the metal conduction band bending. The current across the MSI, ascribed to the thermionic assisted tunneling, is calculated by taking into account the anisotropy of the effective masses, the many valley-structure of the semiconductor energy bands and the quantum mechanical reflection and tunneling through the energy barrier by means of the generalized transmission probability of Kemble. The results shown by the analysis, which excludes explicity the image-force lowering of the energy barrier height, are the reduction of the height and width of the barrier itself and (hence) the increase of its “transparency” to the thermionic current produced by the increase of the reverse bias voltage and/or of the semiconductor impurity concentration. The effects of such properties of the energy barrier on the current-voltage characteristics of the MSI are the absence of a true reverse saturation current, an ideality factor n greater than 1 and a value of the energy barrier height, deduced from the forward current-voltage characteristics, lower than that true and than that obtained from the measured of the junction capacitance vs the bias voltage. The analysis, applied to interfaces between n-type silicon and the metallic silicides RhSi, ZrSi₂, PtSi and Pd₂Si, yields numerical values which agree well with the experimental ones obtained by several authors on the same contacts which, when it is necessary to eliminate field-enhancement at the electrode periphery and leakage currents, incorporate a guard ring. Effectively such a guard ring and the absence of intervening layers of oxide and of other contaminants in the silicon-metal silicide contacts allow one to acquire experimental data more easy to interpret quantitatively than those relative to other contact types.     

High‐Sensitivity p–n Junction Photodiodes Based on PbS Nanocrystal Quantum Dots

Chemically synthesized nanocrystal quantum dots (NQDs) are promising materials for applications in solution‐processable optoelectronic devices such as light emitting diodes, photodetectors, and solar cells. Here, we fabricate and study two types of p‐n junction photodiodes in which the photoactive p‐layer is made from PbS NQDs while the transparent n‐layer is fabricated from wide bandgap oxides (ZnO or TiO₂). By using a p–n junction architecture we are able to significantly reduce the dark current compared to earlier Schottky junction devices without reducing external quantum efficiency (EQE), which reaches values of up to ～80%. The use of this device architecture also allows us to significantly reduce noise and obtain high detectivity (>10¹² cm Hz^1/2 W^?1) extending to the near infrared past 1 μm. We observe that the spectral shape of the photoresponse exhibits a significant dependence on applied bias, and specifically, the EQE sharply increases around 500–600 nm at reverse biases greater than 1 V. We attribute this behavior to a “turn‐on” of an additional contribution to the photocurrent due to electrons excited to the conduction band from the occupied mid‐gap states.