Theoretical analysis of kink effect in C-V characteristics ofIndium-implanted NMOS capacitors

Experimental observation of an anomalous “kink” effect in C-V characteristics of Indium-doped NMOS capacitors is reported and explained, for the first time, via the impact of incomplete ionization of Indium. A new analytical formulation of the total semiconductor capacitance is developed, that takes incomplete ionization phenomenon into account. Thanks to this new C_SC(φ_s) relation, we have demonstrated that the carrier freeze-out is responsible for this kink near V_FB in C-V curves, and also for an intrinsic lowering in the threshold voltage. This kink has been shown to be very sensitive to Indium dose and temperature. It is also demonstrated that the deformation of the C-V characteristics due to Indium incomplete ionization may be (and probably has often been) miss-interpreted as appearance of high fixed charge densities in parameter extraction from C-V fitting. Our analysis is in full agreement with experimental results     

Modeling of SOI-MOS capacitors C-V behavior: partially- andfully-depleted cases

A model is presented for the C-V characteristics of partially-depleted (PD) and fully-depleted (FD) SOI-MOS capacitors. The proposed model is flexible, allowing introduction of all types of nonidealities typical to MOS type structures. New formulae for the low- and high-frequency capacitances of these structures are derived. Due to the various charges stored in these structures, unusual and more complex C-V curves are obtained. C-V curves where interface-state densities have been individually introduced (one at a time) at all three SiO₂-Si interfaces of the SOI-MOS-C are also demonstrated. The model has been validated by fitting the predicted HF C-V curves for SOI-MOS-C and its inherent structure, the SIS capacitor, to the experimental data. The extracted electrophysical parameters of the studied structures, for both PD and FD cases, are very close, if not the same as the values determined during their fabrication     

Numerical solution of Poisson's equation with application to C-V analysis of III-V heterojunction capacitors

The numerical solution to Poisson's equation under quasi-equilibrium conditions, using a formulation that includes carrier degeneracy, multiple conduction band minima, nonparabolicity of the Γ valley, and dopant deianization, is discussed. Moment theorems are shown to provide stringent tests for the accuracy of numerically simulated capacitance versus voltage characteristics. The numerical model is also used to quantify errors in a widely used technique for extracting band discontinuities byC-Vanalysis.     

On nonequilibrium C-V characteristics of MOS inversion region

The nonequilibrium C-V characteristics of the inverted MOS surface under several linear voltage ramp rates are investigated. The apparent emission rates of recombination-generation centers determined from these measurements strongly depend on the ramp rate and increase monotonically with the space charge width. This apparent increase is attributed to the neglected interband impact generation of electron-hole pairs in the high field region of the surface space charge layer. The effects of surface state density and high temperature annealing on these emission rates are also presented.     

Microwave characteristics of liquid-crystal tunable capacitors

This letter investigates the microwave characteristics of the liquid crystal tunable capacitors for the first time. With the dielectric anisotropy properties, the liquid crystal capacitors present very different characteristics compared to the semiconductor or MEMS tunable capacitors. A quality factor of 310 with a control voltage of 5 V was achieved at 4 GHz. A tuning range of 25.3% for the control voltages from 0 to 5 V was obtained at 5 GHz. The results demonstrate the potential applications of liquid crystals as dielectric materials for capacitors with high quality factors and wide tuning ranges at high frequencies, particularly suitable for the future flexible electronics with transparent substrates.     

Simple formulas for analysis of C-V characteristics of MIS capacitor

Paper presents few simple formulas which permit for a quick determination of the parameters of MIS capacitor on the grounds of the high-frequency C-V characteristics of MOS capacitor. These formulas allow for a simple and quick interpretation of the experimental data and can be used in the design of VLSI circuits as well as to the automatization of measurement on a technological line. The error of the proposed formulas was analyzed in the range U_F = 9–16.     

Interface-state characteristics of GaN/GaAs MIS capacitors

Detailed results of the capacitance voltage, conductance voltage and transient capacitance analysis on GaN/GaAs MIS capacitor are presented. It has been found that the low frequency capacitance rises for deep-depletion biases for both n- and p-type GaAs. Transient capacitance analysis has resulted in bulk life time of a few nanosec which is expected for direct band gap semiconductors like GaAs. The interface state density distribution as obtained from the conductance technique showed a rise in the interface state density around 0.30 eV below E_c and 0.55 eV above E_ν of GaAs. The minimum interface state density is around 8 × 10¹⁰/cm² eV.     

Analog characteristics of metal-insulator-metal capacitors usingPECVD nitride dielectrics

The frequency dependence of PECVD nitride and LPCVD oxide metal-insulator-metal (MIM) capacitors is investigated with special attention for precision analog applications. At measurement frequencies of 1.0 MHz, nitride MIM capacitors show capacitance linearity close to that of oxide MIM capacitors, indicating potential for precision analog circuit applications. Due to dispersion effects, however, nitride MIM capacitors show significant degradation in capacitor linearity as the frequency is reduced, which leads to accuracy limitations for precision analog circuits. Oxide MIM capacitors are essentially independent of frequency     

C-V characteristics of ion implanted depletion IGFETs and buried channel CCDs

Capacitance voltage measurements of ion implanted devices for several circuit connections are presented and interpreted in terms of a simple constant profile approximation. Based on this model the device capacitance is described quantitatively in terms of the series combination of a p?n junction capacitance and a conventional MOS capacitance. It is shown that shallow and deep implants reveal characteristically distinctive C-V curves which provide an immediate rough estimate of the implant depth. Analysis of the model yields directly, important parameters for first order design purposes. It is also shown that the measurements provide a simple diagnostic technique to examine the physics of the implanted structure. The use of the simplified model is justified by the agreement between experimental and calculated values.     

Nonequilibrium segregation of phosphorus in the system silicon dioxide-silicon

A model of diffusion-segregation impurity redistribution in the system SiO₂-Si during the thermal oxidation of silicon is developed, taking into account the nonequilibrium character of the segregation process at the moving phase boundary. The temperature dependence of the mass transfer of phosphorus and its mass-transfer coefficient at the SiO₂-Si interface are determined by the numerical analysis of experimental data. Fiz. Tekh. Poluprovodn. 32, 19–23 (January 1998)     

Modeling of high-frequency characteristics for epoxy-sealed micro vacuum capacitors

The high-frequency loss tangent of micro vacuum dielectric capacitors (VDCs) is modeled based on the experimental results using equivalent circuit approach. We found that the dielectric loss of the capacitor at high frequency mainly arises from the dielectric loss of the periphery sealant for the capacitors. Meanwhile, the resonant frequency of the VDCs also depends on that of the sealant. However, within the constraint of sealant material, the characteristics of the VDC can still be optimized by properly choosing the geometric factors. Smaller value of the width of boundary sealant layer to the capacitor side length ratio will result in a smaller value of loss tangent.     

Electrical characteristics of oxide-nitride-oxide films formed ontunnel-structured stacked capacitors

Current conduction mechanism of oxide-nitride-oxide films formed on tunnel-structured stacked capacitor (TSSC) was studied. At positive and negative bias, the Poole-Frenkel (P-F) conduction of holes in the nitride (SiN_x) film dominates the total leakage current. From the P-F plot, the relative dielectric constant of the SiN_x was calculated. The electric field inside the structure was also calculated by assuming the model that characterizes the electrode shape inside the tunnel. From the results, the reason why the reliability of the TSSC is not lowered in comparison with the conventional stacked capacitor is discussed     

Retention and endurance characteristics of HCl-annealed and unannealed MNOS capacitors

MNOS capacitors (metal-nitrite-oxide-semiconductor) have been used to study the effects of memory oxide growth and post-oxidation annealing conditions on retention and endurance of MNOS devices. Results of this study indicate that write/erase cycling causes a decrease in memory window size after 10⁵ cycles, a shift of the memory window center toward more positive values of threshold voltage, and an increase in surface state density for cycling above 10⁶ cycles. The retention data presented indicates that the memory window decay rate for ±25 V writing pulses is only a function of the initial window size. The collapse of the memory window to zero volts is predicted to occur after 10¹⁶ sec for native oxide devices and after 10¹⁸ sec for thermal oxide devices. HCl annealing of the memory oxide does not have a significant effect on either endurance or retention.     

多层瓷介电容器绝缘特性RC的研究

采用N-沟道MOS场效应晶体管搭建电路,测得了多层瓷介电容器通过本身绝缘电阻放电的时间常数τ,对比了Ni和Pd/Ag内电极多层瓷介电容器的绝缘特性RC(绝缘电阻乘以电容量)指标,分析了Ni内电极绝缘特性较差的原因和潜在风险。结果表明:RC反映了介质材料的本身属性,代表电容器通过本身绝缘电阻放电的时间常数τ;Ni内电极的RC考核指标相对于Pd/Ag内电极从1 000 s降至100 s;Ni内电极多层瓷介电容器在高可靠长寿命电路使用时应提高其绝缘特性RC的考核指标。     

Slow state characterization by measurements of current-voltage characteristics of MOS capacitors

Slow current transients in metal-oxide-semiconductor (MOS) capacitors have been observed and related to slow states located in the oxide within tunneling distance of the silicon. This paper describes slow-state related current transients induced by voltage stepping as the basis of the recently developed technique for both energy-level and time-response characterization of the slow states. The voltage stepping measurements are compared to the standard linear voltage ramping technique.     

Electrical characteristics of gold nanoparticle-embedded MIS capacitors with parylene gate dielectric

Memory characteristics of gold nanoparticle-embedded metal–insulator–semiconductor (MIS) capacitors with polymer (parylene-C) gate insulating material are investigated in this study. The gold nanoparticles used in this work were synthesized by the colloidal method. Current density versus voltage curves obtained from the MIS capacitors exhibit better performance for the parylene-C gate insulator, compared with other gate insulating materials. Capacitance versus voltage (C–V) curves show a flat band voltage shift, which indicates the possibility of charge storage in the gold nanoparticles. In addition, the charge retention characteristic for the gold nanoparticle-embedded MIS capacitor is described in this paper.     

Single-parameter model for the post-breakdown conduction characteristics of HoTiOx-based MIM capacitors

The post-breakdown conduction characteristics of holmium titanium oxide (HoTiO_x)-based metal–insulator–metal capacitors fabricated by the atomic layer deposition technique on Si substrates were investigated. Diode-like and power-law models were fitted to the experimental current–voltage (I–V) curves and the results assessed with the aim of detecting any possible correlation among the model parameters. It was found that the number of parameters involved can be reduced in both cases and that for the power-law model a single parameter is solely required to approximate the I–V curves in a wide current range (from 10⁻¹¹ to 10⁻⁴ A). This property, which has also been observed in a variety of material systems, was used to simulate the bipolar switching behavior exhibited by the I–V characteristics. The connection with the physics of electron transport through atom-sized constrictions is discussed.     

MFIS结构的C-V特性

研究了运用SOL-GEL方法制备的Au/PZT(铅锆钛)/ZrO2/Si结构电容即MFIS(Metal/Ferroelectr c/Irsulator/Semiconductor)电容的方法,并对其进行了SEM、C-V特性测试及ZrO2介质层介电常数分析.研究了C-V存储窗口(Memory WindoW)电压与铁电薄膜和介质层厚度比的关系,得出MFIS电容结构中最佳铁电薄膜和介质层厚度比为7 10左右,在外加电压5V-+5V时存储窗口可达2.52V左右.