A 5-ns 1-Mb ECL BiCMOS SRAM

A 1-Mword×1-b ECL (emitter coupled logic) 10 K I/O (input/output) compatible SRAM (static random-access memory) with 5-ns typical address access time has been developed using double-level poly-Si, double-level metal, 0.8-μm BiCMOS technology. To achieve 5-ns address access time, high-speed X-address decoding circuits with wired-OR predecoders and ECL-to-CMOS voltage-level converters with partial address decoding function and sensing circuits with small differential signal voltage swing were developed. The die and memory cell sizes are 16.8 mm×6.7 mm and 8.5 μm×5.3 μm, respectively. The active power is 1 W at 100-MHz operation     

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz.<>     

一种低压低功耗Flash BiCMOS SRAM的设计

设计了一种静态随机读写存储器(SRAM)的BiCMOS存储单元及其外围电路。HSpice仿真结果表明，所设计的SRAM电路的电源电压可低于3V以下，它既保留了CMOS SRAM低功耗、高集成度的特征，又获得了双极型电路快速、大电流驱动能力的长处，因而特别适用于高速缓冲静态存储器和便携式数字电子设备的存储系统中。     

A 3.8-ns 16 K BiCMOS SRAM

A 2 K×8-b, ECL 100 K compatible BiCMOS SRAM with 3.8-ns (-4.5 V, 60°) address access time is described. The precisely controlled bit-line voltage swing (60 mV), a current sensing method, and optimized ECL decoding circuits permit a reliable and fast readout operation. The SRAM features an on-chip write pulse generator, latches for input and output bits, and a full six-transistor CMOS cell array. Power dissipation is approximately 2 W, and the chip size is 3.9×5.9 mm². The SRAM was based on 1.2-μm BiCMOS, using double-metal, triple-polysilicon, and self-aligned bipolar transistors     

A 14 ns 256 K×1 CMOS SRAM with multiple test modes

A methodology to enter and exit from test modes in asynchronous static RAMs (SRAMs) is presented. This chip is fabricated in a 0.7 μm twin-tub, single-poly, double-metal technology on p/p⁺ epitaxial substrate. To prevent hot-electron degradation, a voltage regulator is used in the memory matrix, with the cascoding technique applied in the periphery. Circuits were implemented against voltage bumps and data glitching on the output. A small cell size of 5.1×13.7 μm² and a chip size of 3.9×9.5 mm² have been achieved     

A 4-ns 4K×1-bit two-port BiCMOS SRAM

The authors introduce a two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays. The memory can be read and written simultaneously and is therefore well-suited to applications such as high-speed caches and video memories. A read access time of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K×1-bit two-port memory integrated in a 1.5-μm 5-GHz BiCMOS technology. The access time in this prototype design is nearly temperature-insensitive, increasing to only 4 ns at a case temperature of 100°C     

A 150 ns 16-Mb CMOS SRAM with interdigitated bit-line architecture

Circuit techniques for a reduced-voltage-amplitude data bus, fast access 16-Mb CMOS SRAM are described. An interdigitated bit-line architecture reduces data bus line length, thus minimizing bus capacitance. A hierarchical sense amplifier consists of 32 local sense amplifiers and a current sense amplifier. The current sense amplifier is used to reduce the data bus voltage amplitude and the sensing of the 16-b data bus signals in parallel. Access time of 15 ns and an active power of 165 mW were achieved in a 16-Mb CMOS SRAM. A split-word-line layout memory cell with double-gate pMOS thin-film transistors (TFTs) keeps the transistor width stable while providing high-stability memory cell characteristics. The double-gate pMOS TFT also increases cell-storage node capacitance and soft-error immunity     

A 100 Mb/s BiCMOS adaptive pulse-shaping filter

With the growing demand for high-speed transmission of digital data, there is a challenge for utilizing the existing copper plant as the transmission medium, especially for short-hop links. This medium offers a lower cost to a fiber medium, but requires more sophisticated electronics to account for electromagnetic emissions, cross-talk, and cable loss. These include pulse shaping filters, cross-talk cancelers, and equalizers. To maintain system cost at a minimum, analog solutions are preferred. A continuous-time tunable biquad implemented in a 0.8 μm BiCMOS process and configured as an adaptive pulse-shaping filter is described. The biquad is tunable over the range 10-230 MHz with variable Q factors. It is composed of five transconductance-C integrators each dissipating a static power of 10 mW at 5 V. A method for adapting the filter's pole-frequency and Q-factor while servicing 100 Mb/s NRZ data is presented together with experimental results     

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM

The authors report a 4 M word×1 b/1 M word×4 b BiCMOS SRAM that can be metal mask programmed as either a 6-ns access time for an ECL 100 K I/O interface to an 8-ns access time for a 3.3-V TTL I/O interface. Die size is 18.87 mm×8.77 mm. Memory cell size is 5.8 μm×3.2 μm. In order to achieve such high-speed address access times the following technologies were developed: (1) a BiCMOS level converter that directly connects the ECL signal level to the CMOS level; (2) a high-speed BiCMOS circuit with low threshold voltage nMOSFETs; (3) a design method for determining the optimum number of decoder gate stages and the optimum size of gate transistors; (4) high-speed bipolar sensing circuits used at 3.3-V supply voltage; and (5) 0.55-μm BiCMOS process technology with a triple-well structure     

A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-inself-test

An experimental 576 K BiCMOS emitter-coupled-logic (ECL)-compatible SRAM that achieves 3.5-ns access and cycle is discussed. The SRAM is fully self-testable using less than 1 K on-chip logic gates to assist characterization, wafer testing, and package testing. The I/O is also transistor-transistor-logic (TTL) programmable with the first-metal mask     

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportionalself-timing generator

This 512 Kw×8 b×3 way synchronous BiCMOS SRAM uses a 2-stage wave-pipeline scheme, a PLL self-timing generator and a 0.4-μm BiCMOS process to achieve 220 MHz fully-random read/write operations with a GTL I/O interface. Newly developed circuit technologies include: 1) a zig-zag double word-line scheme, 2) a centered bit-line load layout scheme, and 3) a phase-locked-loop (PLL) with a multistage-tapped ring oscillator which generates a clock cycle proportional pulse (CCPP) and a clock edge lookahead pulse (CELP)     

Fast-access BiCMOS SRAM architecture with a VSSgenerator

A high-speed BiCMOS ECL (emitter coupled logic) interface SRAM (static RAM) architecture is described. To obtain high-speed operation for scaled-down devices, such as MOSFETs with a feature size of 0.8 μm or less and with a small MOS level, a new SRAM architecture featuring all-bipolar peripheral circuits and CMOS memory cells with V_SS generator has been developed. Two key circuits, a V_SS generator and a current switch level converter, are described in detail. These circuits reduce the external supply voltage to the internal MOS level, thus permitting high-speed SRAM operation. To demonstrate the effectiveness of the concept, a 256 kb SRAM with an address access time of 5 ns is described     

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces

A 64 K CMOS RAM with emitter-coupled logic (ECL) interfaces having access times of 6.2 ns at room temperature and with a CMOS process specifically optimized for low-temperature operation, 3.5 ns at liquid nitrogen (LN) temperature, is presented. The CMOS processes feature a 0.5 μm L_eff, self-aligned TiSi₂ double-level metal, and an average minimum feature size of 1.35 μm. Circuits keyed to high-speed operation are described with emphasis on low power and safe operation. Unique aspects of LN-temperature operation including circuit-device interactions, the impact of velocity saturation effects on channel length, temperature and power supply sensitivities, and the characteristics of the ECL-to-CMOS receiver circuits are discussed     

A 4.5 ns access time 1K /spl times/ 4 bit ECL RAM

An extremely high-speed ECL 4-kbit RAM with maximum access time of 4.5 ns and typical power dissipation of 1.5 W has been developed for cache memories and control store. This performance has been realized by using a very shallow junction transistor with an emitter size of 1.3 /spl times/ 1.5 /spl mu/m, which has a high cutoff frequency of 9 GHz, in conjunction with optimized circuit design. The RAM was housed in a small leadless chip carrier (LCC) package. The overall package size was 0.335 in/SUP 2/. The RAM was designed to have soft-error immunity. The failure rate due to alpha particles has been estimated, through acceleration tests, to be less than 50 FIT.     

A 5.8-ns 256-Kb BiCMOS TTL SRAM with T-Shaped bit line architecture

Presents a new bit line architecture named T-shaped bit line architecture (TSBA), which is suitable for high speed, high density, and/or large bit-wide configuration SRAMs. TSBA, utilizing orthogonal complimentary bit lines in parallel with the word lines, is the solution to bit line pitch constraint for direct bipolar column sensing. This TSBA is applied to a 256-Kb SRAM with a typical access time of 5.8 ns. To achieve access times below 6 ns, this SRAM employs a bipolar Darlington column sense amplifier, a hierarchical column decoding scheme, a data bus shielding layout combined with TSBA, and a 0.8-μm BiCMOS technology     

A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's

The feasibility of realizing an emitter-coupled-logic (ECL) interface 4-Mb dynamic RAM (DRAM) with an access time under 10 ns using 0.3-μm technology is explored, and a deep submicrometer BiCMOS VLSI using this technology is proposed. Five aspects of such a DRAM are covered. They are the internal power supply voltage scheme using on-chip voltage limiters, an ECL DRAM address buffer with a reset function and level converter, a current source for address buffers compensated for device parameter fluctuation, an overdrive rewrite amplifier for realizing a fast cycle time, and double-stage current sensing for the main amplifier and output buffer. Using these circuit techniques, an access time of 7.8 ns is expected with a supply current of 198 mA at a 16-ns cycle time     

A 3.5-ns, 500-mW, 16-kbit BiCMOS ECL RAM

A 16-kbit BiCMOS ECL SRAM with a typical address access time of 3.5 ns and 500-mW power dissipation was developed. The RAM was fabricated using half-micrometer, triple-poly, and triple-metal BiCMOS technology. The fast access time with moderate power dissipation has been achieved using new circuit techniques: a grounded-gate, nonlatching-type level converter with a wired-OR predecoder and a direct column sensing scheme having a cascode differential amplifier. As a result of extensive use of high-speed bipolar ECL circuits with self-aligned bipolar transistors, the RAM attains high-speed performance without degrading the low-power BiCMOS RAM characteristics.<>     

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM

A 0.3-μm 4-Mb BiCMOS SRAM with a 6-ns access time at a minimum supply voltage of 1.5 V has been developed. Circuit technologies contributing to the low-voltage, high-speed operations include: (1) boost-BiNMOS gates for address decoding circuits; (2) an optimized word-boost technique for a highly-resistive-load memory cell; (3) a stepped-down CML cascoded bipolar sense amplifier; (4) optimum boost-voltage detection circuits with dummies for boost-voltage generators     

A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates

A 1.5-ns address access time, 256-kb BiCMOS SRAM has been developed. To attain this ultra-high-speed access time, an emitter-coupled logic (ECL) word driver is used to access 6-T CMOS memory cells, eliminating the ECL-MOS level-shifter time delay. The RAM uses a low-power active pull down ECL decoder. The chip contains 11-K, 60-ps ECL circuit gates. It provides variable RAM configurations and general logic functions. RAM power consumption is 18 W; chip power consumption is 35 W. The chip is fabricated by using a 0.5-μm BiCMOS process. The memory cell size is 58 μm² and the chip size is 11×11 mm     

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduces output delays by 0.5 ns to 0.75 ns. The 6.6-μm² high-density memory cell uses a parallel transistor layout and phase-shifting photolithography. The critical charge that brings about soft error in a memory cell can be drastically increased by adjusting the resistances of poly-PMOS gate electrodes. This can be done without increasing process complexity or memory cell area. The 1-Mb SRAM was fabricated using 0.3-μm CMOS quadrupole-poly and double-metal technology. The chip measures 3.96 mm×7.4 mm (29 mm²)