SOC可测试性设计与测试技术

超深亚微米工艺和基于芯核的设计给芯片系统(system-on-a-chip,SOC)测试带来了新的问题．对SOC可测试性设计与测试技术的国际研究现状及进展进行了广泛而深入的综述．从芯核级综述了数字逻辑、模拟电路、存储器、处理器4类芯核的可测试性设计与测试技术,从系统级综述了测试激励、测试响应和测试访问机制等SOC测试资源的设计以及压缩／解压缩与测试调度等测试资源划分、优化技术,并介绍了2个标准化组织开展的SOC测试标准工作．最后,展望了SOC测试未来的发展方向．     

Design for Testability Features of Godson-3 Multicore Microprocessor

This paper describes the design for testability (DFT) challenges and techniques of Godson-3 microprocessor,which is a scalable multicore processor based on the scalable mesh of crossbar (SMOC) on-chip network and targets high-end applications.Advanced techniques are adopted to make the DFT design scalable and achieve low-power and low-cost test with limited IO resources.To achieve a scalable and flexible test access,a highly elaborate test access mechanism (TAM) is implemented to support multiple test instructions and test modes.Taking advantage of multiple identical cores embedding in the processor,scan partition and on-chip comparisons are employed to reduce test power and test time.Test compression technique is also utilized to decrease test time.To further reduce test power,clock controlling logics are designed with ability to turn off clocks of non-testing partitions.In addition,scan collars of CACHEs are designed to perform functional test with low-speed ATE for speed-binning purposes,which poses low complexity and has good correlation results.     

X-tolerant test response compaction

Larger, denser designs lead to more defects; higher quality requirements and new test methods lead to an explosion in test data volume. Test compression technique attempt to do more testing with fewer bits. This article summarizes one such method, X compact which addresses how unknowns the bane of compression and logic BIST techniques are eliminated. DFT engineers must spend serious effort to minimize Xs in future designs. It is impossible to eliminate all Xs. X-tolerant response compactors are necessary for tolerating residual Xs to enable massive compaction with practically no impact on test quality. X-compactors are mainly useful for test compression purposes and provide up to 80 times the test response compaction of traditional scan. X-tolerant signature analyzers extend the X-compact concept to incorporate time compaction, thereby tolerating thousands of Xs and reducing test response data volume by 50 to 2,000 times relative to traditional scan. These signature analyzers are extremely beneficial for BIST because Xs can easily corrupt traditional MISR-based BIST signature analyzers. X-tolerant response compactors also enable efficient diagnosis essential to fast yield-learning.     

用扫描链重构来提高EFDR编码的测试压缩率和降低测试功耗

为了解决系统芯片测试中日益增长的测试数据和测试功耗的问题,提出一种不影响芯片正常逻辑功能的扫描链重构算法--Run-Reduced-Reconfiguration(3R).该算法针对扩展频率导向游程(EFDR)编码来重排序扫描链和调整扫描单元极性,重新组织测试数据,减少了游程的数量.从而大人提高了EFDR编码的测试压缩率并降低测试功耗;分析了扫描链调整对布线长度带来的影响后,给出了权衡压缩率和布线长度的解决方案.在ISCAS89基准电路上的实验结果表明,使用3R算法后,测试压缩率提高了52%,测试移位功耗降低了53%.     

Testability features of the AMD-K6 microprocessor

The AMD-K6's embedded design-for-testability structures and test pattern development methodologies provide high-quality manufacturing tests. The DFT features support static voltage-level testing for wafer-sort and debug testing, application of two pattern sequences for detection of timing-related failures, scan-based BIST, and 1149.1 boundary scan     

针对扫描阻塞结构的测试数据压缩方案*

分析了集成电路测试面临的测试数据量大、测试应用时间长等问题,对常用的测试压缩方法进行了介绍,并在扫描阻塞测试结构基础上,提出了对数据进行部分编码压缩的方案。在附加硬件开销很小的情况下,进一步压缩了测试数据。理论分析和实验结果都表明了本压缩方案的可行性和有效性。     

一种基于轮流扫描捕获的低功耗低费用BIST方法

过高的测试功耗和过长的测试应用时间是基于伪随机内建自测试(BIST)的扫描测试所面临的两大主要问题.提出了一种基于扫描子链轮流扫描捕获的BIST方法.在提出的方法中,每条扫描链被划分成N(N>1)条子链,使用扫描链阻塞技术,同一时刻每条扫描链中只有一条扫描子链活跃,扫描子链轮流进行扫描和捕获,有效地降低了扫描移位和响应捕获期间扫描单元的翻转频率.同时,为检测抗随机故障提出了一种适用于所提出测试方法的线性反馈移位寄存器(LFSR)种子产生算法.在ISCAS89基准电路上进行的实验表明,提出的方案不但降低约(N-1)?N的平均功耗和峰值功耗,而且显著地减少随机测试的测试应用时间和LFSR重播种的种子存储量.     

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting

Industry has used scan-based designs widely to promote test quality. However, for larger designs, the growing test data volume has significantly increased test cost because of excessively long test times and elevated tester memory and external test channel requirements. To address these problems, researchers have proposed numerous test compression architectures. In this article, we propose a flexible scan test methodology called universal multicasting scan (UMC scan). It has three major features: First, it provides a better than state-of-the-art test compression ratio using multicasting. Second, it accepts any existing test patterns and doesn't need ATPG support. Third, unlike most previous multicasting schemes that use mapping logic to partition the scan chains into hard configurations, UMC scan's compatible scan chain groups are defined by control bits, as in the segmented addressable scan (SAS) architecture. We have developed several techniques to reduce the extra control bits so that the overall test compression ratio can approach that of the ideal multicasting scheme.     

一种多扫描链混合测试数据压缩方法

针对集成电路测试数据量大、测试应用时间长和测试结构复杂等问题,提出一种多扫描链的混合测试数据压缩方法。对于含无关位较多的测试向量,使用伪随机向量产生器生成。对于含无关位较少的向量,则直接使用自动测试设备存储。将该方法与另一种基于扫描阻塞的测试方法进行比较,理论分析和实验结果表明,该方法对数据的压缩效果优于单纯用伪随机方式的扫描阻塞测试方法。     

可测试性设计技术在一款通用CPU芯片中的应用

可测试性设计(Design-For-Testability,简称DFT)是芯片设计的重要环节,它通过在芯片原始设计中插入各种用于提高芯片可测试性的硬件逻辑,从而使芯片变得容易测试,大幅度节省芯片测试的成本。文中介绍了在一款通用CPU芯片的设计过程中,为提高芯片的易测性而采取的各种可测试性设计技术,主要包括扫描设计(ScanDesign)、存储器内建自测试(Build-in-self-test,简称BIST)以及与IEEE1149.1标准兼容的边界扫描设计(BoundaryScanDesign,简称BSD)等技术。这些技术的使用为该芯片提供了方便可靠的测试方案。     

Cost-driven ranking of memory elements for partial intrusion

DFT techniques such as scan, BIST, or test point insertion intrude the circuitry for ease of testing. However, testing ease incurs increased silicon area requirements and performance penalities. The authors present a method of identifying cost-effect intermediate solutions     

遗传算法的板级边界扫描测试矢量优化及应用

测试矢量是边界扫描技术的关键之一,测试矢量集直接影响测试的效率和结果。文章将遗传算法引入可测性设计中的边界扫描测试领域,以PCB、MCM等为工程对象,探索了遗传算法的互连测试矢量生成,提出了具有互连测试特性的适应度函数、遗传算子和遗传操作,并进行了仿真实验和实际的DEMO板测试,结果表明该算法具有一定的优越性。     

MCU可测性设计的实现

由于 MCU(Micro-Controller Unit)的结构非常复杂 ,因此若在设计时采用一般数字电路设计的从结构出发的 DFT(Design For Testability)技术 (包括扫描设计和 BIST—— Built-In Self-Test)将使电路的规模急剧增大。本文从功能测试的角度出发 ,提出了一种在 MCU中加入规模很小的模式选择电路 ,对部分电路作较小改动 ,就使芯片内的各块电路都可被测试的方法。在完成了 MCU 的可测性设计(Testable Design)后进行了仿真     

Test compression saves bits, cycles, and money

Test data compression became an active research topic in the late 1990s, and has now become a standard offering within commercial DFT solutions. This issue of IEEE Design & Test features a special issue on the current state of test compression. This issue of D&T also concludes the theme of design and test of RFIC chips (featured in the Jan./Feb. 08 issue), with two additional articles. In addition, this issue features two general-interest articles and an interview with DRAM inventor Bob Dennard.     

LOCST: A Built-In Self-Test Technique

A built-in self-test technique utilizing on-chip pseudorandom-pattern generation, on-chip signature analysis, a ``boundary scan' feature, and an on-chip monitor test controller has been implemented on three VLSI chips by the IBM Federal Systems Division. This method (designated LSSD on-chip self-test, or LOCST) uses existing level-sensitive scan design strings to serially scan random test patterns to the chip's combinational logic and to collect test results. On-chip pseudorandom-pattern generation and signature analysis compression are provided via existing latches, which are configured into linear-feedback shift registers during the self-test operation. The LOCST technique is controlled through the on-chip monitor, IBM FSD's standard VLSI test interface/controller. Boundary scan latches are provided on all primary inputs and primary outputs to maximize self-test effectiveness and to facilitate chip I/O testing. Stuck-fault simulation using statistical fault analysis was used to evaluate test coverage effectiveness. Total test coverage values of 81.5, 85.3, and 88.6 percent were achieved for the three chips with less than 5000 random-pattern sequences. Outstanding test coverage (≫97%) was achieved for the interior logic of the chips. The advantages of this technique, namely very low hardware overhead cost (≪2%), design-independent implementation, and effective static testing, make LOCST an attractive and powerful technique.     

嵌入式网卡芯片设计及其低功耗DFT技术考虑

针对目前应用于信息家电的以太网多芯片解决方案具有成本高、性能较低等问题,文章设计实现了一款以太网控制SoC单芯片。同时,为了获得较低的测试功耗,进行了可测试技术的低功耗优化。该芯片采用TSMC0．25／μm 2P4M CMOS工艺流片,裸片面积为4．8×4．6mm^2,测试结果表明,该嵌入式以太网控制SoC芯片的故障覆盖率可达到97％,样片的以太网数据包最高吞吐量可以达到7Mbits／s。     

Testing Defects in Scan Chains

Applying scan-based DFT, I_DDQ testing, or both to sequential circuits does not ensure bridging-fault detection, which depends on the resistance of the fault and circuit level parameters. With a “transparent” scan chain, however, the tester can use both methods to detect manufacturing process defects effectively-including difficult-to-detect shorts in the scan chain. The author presents a strategy for making the scan chain transparent. The test complexity of such a chain is very small, regardless of the number of flip-flops it contains     

基于BIST软件测试思想的单元测试框架

BIST是一种成熟的硬件可测性设计的方法,BIST软件测试思想则借用了该技术,它主要包括模板和自治测试部分两大基本结构。在该思想的指导下,整合测试用例、测试点、插装函数、测试报告等测试要素,提出了各个要素的存储或使用方式,以路径覆盖为测试目标,提出了一种BIST软件自测试的测试框架。实践证明,该测试框架有利于BIST软件测试思想的进一步研究和实现。     

Survey of Scan Chain Diagnosis

Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The cells in the chain are sequentially numbered from scan output to scan input, starting with 0. A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks. The purpose of chain patterns is to test scan chain integrity. A scan pattern (also known as a logic test pattern) is a pattern consisting of a shift-in operation, one or multiple capture clock cycles, and a shift-out operation. The purpose of scan patterns is to test system logic. The scan cells between the scan chain input and a scan cell's scan input terminal are called the upstream cells of that scan cell. The scan cells between the scan chain output and a scan cell's scan output terminal are called the downstream cells of that scan cell.     

Scan Cell Positioning for Boosting the Compression of Fan-Out Networks

Ensuring a high manufacturing test quality of an integrated electronic circuit mandates the application of a large volume test set. Even if the test data can be fit into the memory of an external tester, the consequent increase in test application time reflects into elevated production costs. Test data compression solutions have been proposed to address the test time and data volume problem by storing and delivering the test data in a compressed format, and subsequently by expanding the data on-chip. In this paper, we propose a scan cell positioning methodology that accompanies a compression technique in order to boost the compression ratio, and squash the test data even further. While we present the application of the proposed approach in conjunction with the fan-out based decompression architecture, this approach can be extended for application along with other compression solutions as well. The experimental results also confirm the compression enhancement of the proposed methodology.