A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_ov and fringing C_if+C_of capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.     

Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations

This paper presents a compact model for the electrostatic potentials and the current characteristics of doped long-channel cylindrical surrounding-gate (SRG) MOSFETs. An analytical expression of the potentials is derived as a function of doping concentration. Then, the mobile charge density is calculated using the analytical expressions of the surface potential at the surface and the difference of potentials between the surface and the center of the silicon doped layer. Using the expression obtained for the mobile charge, a drain current expression is derived. Comparisons of the modeled expressions with the simulated characteristics obtained from the 3D ATLAS device simulator for the transfer characteristics, as well for the output characteristics, show good agreement within the practical range of gate and drain voltages and for doping concentrations ranging from 10¹⁶ cm⁻³ to 5 × 10¹⁸ cm⁻³.     

Harmonic distortion analysis using an improved charge sheet model for PD SOI MOSFETs

This work presents an Improved Charge Sheet compact Model (ICSM) especially valuable for distortion analysis, where precise calculation of derivatives of at least third order is required. A new expression for the charge is used in the calculation of the current. Vertical electric field, mobility and DIBL are represented using previously reported for other purposes more precise expressions. The very good agreement obtained between experimental PD SOI MOSFETs with channel lengths from 0.32 to 10 μm and modeled currents, derivatives and distortion figures is shown.     

A physical compact DC drain current model for long-channel undoped ultra-thin body (UTB) SOI and asymmetric double-gate (DG) MOSFETs with independent gate operation

In this paper, a new compact charge based DC model for the drain current of long channel fully depleted ultra-thin body SOI MOSFETs and asymmetric double-gate MOSFETs with independent gate operation (ADGMOSFETs) is presented. The model was validated by both TCAD simulations and electrical measurements with a good agreement. In particular, great care was taken during the derivation of the model in order to respect the physics of the device and to make the correct approximations. The obtained solutions can be viewed as a generalization of classical MOS theory to the case of undoped fully depleted ADGMOS. As a result, the model consists of relatively simple equations and is a promising approach for the compact modeling and parameter extraction of fully depleted SOI transistors.     

A new small-signal MOSFET model and parameter extraction method for RF IC's application

In this paper, an accurate and simple small signal model of RF MOSFETs accounting for the distributed gate effect, the substrate parasitics and charge conservation is proposed. Meanwhile, a direct and accurate extraction method using linear regression approach for the components of the equivalent circuit of the MOSFET with S-parameters analysis is also proposed. The proposed model and extraction method are verified with the experimental data and an excellent agreement is obtained up to 10 GHz. The extraction results from the measured data for various bias conditions are presented. Also, the extracted parameters, such as transconductance g_m, match well with those obtained from DC measurements. Besides, it is shown that a significant error in circuit performances would be found if the charge conservation is not properly considered.     

Compact modeling of 0.35 μm SOI CMOS technology node for 4 K DC operation using Verilog-A

Compact modeling of MOSFETs from a 0.35 μm SOI technology node operating at 4 K is presented. The Verilog-A language is used to modify device equations for BSIM models and more accurately reproduce measured DC behavior, which is not possible with the standard BSIM model set. The model presented exhibits convergent behavior and is shown to be experimentally accurate at 4 K. No design tool currently in place exhibits convergence and/or accuracy over this range. The Verilog-A approach also allows the embedding of nonlinear length, width and bias effects into BSIM calculated curves beyond those that can be achieved by the use of different BSIM parameter sets. Nonlinear dependences are necessary to capture effects particular to 4 K behavior, such as current kinks. The 4 K DC behavior is reproduced well by the compact model and the model seamlessly evolves during simulation of circuits and systems as the simulator encounters SOI MOSFETs with different lengths and widths. The incorporation of various length/width and bias dependent effects into one Verilog-A/BSIM4 library, therefore, produces one model for all sets of devices called up in a given product design kit (PDK) for this technology node.     

A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates

In this paper a computationally efficient surface-potential-based compact model for fully-depleted SOI MOSFETs with independently-controlled front- and back-gates is presented. A fully-depleted SOI MOSFET with a back-gate is essentially an independent double-gate device. To the best of our knowledge, existing surface-potential-based models for independent double-gate devices require numerical iteration to compute the surface potentials. This increases the model computational time and may cause convergence difficulties. In this work, a new approximation scheme is developed to compute the surface potentials and charge densities using explicit analytical equations. The approximation is shown to be computationally efficient and preserves important properties of fully-depleted SOI MOSFETs such as volume inversion. Drain current and charge expressions are derived without using the charge sheet approximation and agree well with TCAD simulations. Non-ideal effects are added to describe the I-V and C-V of a real device. Source-drain symmetry is preserved for both the current and the charge models. The full model is implemented in Verilog-A and its convergence is demonstrated through transient simulation of a coupled ring oscillator circuit with 2020 transistors.     

一种JFET区域具有N型重掺杂的1 200 V碳化硅浅槽平面MOSFET器件的设计与优化

介绍了一种在JFET区域采用浅槽N型重掺杂降低器件比导通电阻与开启损耗的1 200 V碳化硅平面栅MOSFET器件。采用浅槽结构设计,减小了器件栅源电容CGS及栅漏电容与栅源电容比值CGD/CGS,降低了器件的开启损耗。浅槽下方采用的N型重掺杂使得器件反型层沟道压降明显提高,使器件获得了更低的比导通电阻。仿真结果表明,相比于平面栅MOSFET器件,开启损耗降低了20%;相比于平面栅MOSFET与分裂栅MOSFET,器件比导通电阻分别减小了14%和17%。     

Compact modeling of quantum effects in symmetric double-gate MOSFETs

Quantum effects have been incorporated in the analytic potential model for double-gate MOSFETs. From extensive solutions to the coupled Schrodinger and Poisson equations, threshold voltage shift and inversion layer capacitance are extracted as closed form functions of silicon thickness and inversion charge density. With these modifications, the compact model is shown to reproduce C-V and I-V curves of double-gate MOSFETs consistent with those obtained from those measured from experimental FinFET hardware.     

A novel surface potential-based short channel MOSFET model for circuit simulation

In this paper a novel analytical approximation method for surface potential (ψ_s) calculation in compact MOSFET model is presented. It achieves excellent accuracy and good calculation speed over all regions from accumulation to strong inversion. With this approximation method, a surface potential-based compact model for short channel MOSFET is developed. Comparison with measured data is also presented to validate the new model.     

高速纳秒脉冲激光器驱动电源的设计

介绍了一种可靠的脉冲激光器驱动电源的设计方法。采用直接调制技术,通过高速场效应管作为开关器件,辅以稳定的外围电路,调制出脉冲宽度小于2ns纳秒的窄脉冲光。     

一种电荷平衡结构的沟槽MOSFET的优化设计

为了降低传统沟槽MOSFET的导通电阻和栅漏电容,科研人员提出一种具有电荷平衡结构的SG-RSO MOSFET。在此基础上,利用电荷平衡理论计算出SG-RSO MOSFET结构的主要参数,并借助TCAD仿真软件对外延层厚度及其掺杂浓度、场板氧化层厚度和沟槽深度等主要参数进行合理优化设计。最终,仿真得到击穿电压为92.6 V、特征导通电阻为19.01 mΩ·mm²、特征栅漏电容为1.45 nF·cm-2的SG-RSO MOSFET。该器件性能优于传统沟槽MOSFET。     

功率MOSFET寄生振荡的研究

针对MOSFET易产生寄生振荡的问题,在分析振荡与驱动电路各参数之间关系的基础上,通过加入合适的驱动电阻来解决该振荡问题,从而保证MOSFET能在高速应用场合的可靠运行.该方法具有实现简单、成本低廉、安全可靠的特点.经过1000W纯正弦波逆变器设计应用,实验波形表明驱动电路的合理性和有效性.     

并联电容对DE类功率放大器的影响

DE类功率放大器既综合了D类和E类功率放大器的优点,继承了开关型功率放大器高效率的特征,又同时避免了D类和E类功率放大器的缺陷,使其成为了人们关注和研究的热点。随着工作频率的升高,MOSFET寄生电容在DE类功率放大器并联电容的计算中无法忽略。经过理论分析得到了MOSFET寄生电容的等效电容表达式,通过使用等效电容表达式,可以获得包含MOSFET寄生电容影响的并联电容的取值,提高了DE类功率放大器设计精度,保证了DE类功率放大器在高频时的高效率。通过SPICE模型仿真和电路实验验证了分析的有效性。     

Electrical characterization and TCAD simulations of multi-gate bulk nMOSFET

A multi-gate nMOSFET in bulk CMOS process has been fabricated by integration of polysilicon-filled trenches. We have simulated its electrical characteristics by using TCAD software and compared them with results obtained from electrical measurements. The threshold voltage and the subthreshold slope of the top gate have been extracted and we found a good accordance, for both parameters, between the measurements (V_TH=0.59 V, S=90 mV/dec) and simulations (V_TH=0.50 V, S=92 mV/dec). The surface channel effective mobility of this multi-gate MOSFET was extracted and evaluated with both effective length and surface. The studies revealed that mobility degraded towards smaller dimensions of the MOS channel. At last, the Si/SiO₂ interface quality studies were carried out. We noticed that the injected donor traps have a larger influence on the current–voltage characteristics than acceptor-like traps. With its good electrical performances, this low-cost multi-gate MOSFET technology presents interesting perspective in CMOS image sensors and more generally in analog application taking benefit of the multi-threshold for example.     

A compact deep-submicron MOSFET gds model including hot-electron and thermoelectric effects

A compact I_ds model with physical drain-conductance (g_ds) modeling for deep-submicron MOSFETs is formulated based on first-principle momentum-/energy-balance equations, which simultaneously includes the hot-electron and thermoelectric effects in a unified compact form with two fitting parameters and one-step extraction. The model has been verified with 0.18-μm experimental data with good g_ds prediction.     

77K低温下MOSFET非固有电容参数提取研究

77 K 低温参数是制冷型碲镉汞红外焦平面探测器读出电路设计与精确仿真的关键点之一.通过研究 MOSFET 非固有电容的特性,并基于 BSIM3通用模型对电容的描述,在77 K 低温下进行测试提取,得到了相关的模型参数.嵌入 SPICE 软件仿真对比,证明了参数的准确性.     

一种优化的SiGe HBT集约模型及参数提取方法

通过合理简化和改进MEXTRAM模型,提出了一种优化的SiGe HBT集约模型和参数提取方法;精确提取了一组微波SiGe HBT的模型参数。仿真结果与测试数据的相对误差不超过3%。     

纳米级MOSFET多晶区量子修正解析模型

利用ISE8．0的DESSIS，对多晶区量子力学效应进行了模拟。结果表明，纳米级MOS—FET多晶区内的量子效应不可忽略，且它对器件特性的影响与多晶耗尽效应相反。从密度梯度模型，简化得到多晶区量子效应修正，并建立了多晶区内量子效应的集约模型。该模型与数值模拟结果吻合。