A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap C_ov and fringing C_if+C_of capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.     

功率MOSFET寄生振荡的研究

针对MOSFET易产生寄生振荡的问题,在分析振荡与驱动电路各参数之间关系的基础上,通过加入合适的驱动电阻来解决该振荡问题,从而保证MOSFET能在高速应用场合的可靠运行.该方法具有实现简单、成本低廉、安全可靠的特点.经过1000W纯正弦波逆变器设计应用,实验波形表明驱动电路的合理性和有效性.     

射频场效应晶体管的交流小信号建模技术研究

提出了新的金属-氧化层-半导体-场效晶体管（MOSFET）器件的小信号等效电路结构,提取了等效电路结构的元件参数值,在器件建模型软件IC-CAP2008下,对等效电路模型和提取的元件参数进行编译,生成了能够应用于射频与微波领域的场效应晶体管的高频小信号器件模型,将生成的器件模型编译到高频仿真软件ADS中,并调用S参数仿真器对器件模型进行S参数仿真,最后对比了仿真结果与测试数据的差异性,对生成的器件模型做出了误差分析,展示了所建小信号模型的良好性能。     

基于BSIM深亚微米级MOSFET短沟道效应建模和特征提取方法研究

本文基于BSIM标准研究了现代深亚微米级MOSFET器件的建模和特征提取方法,着重在于短沟道效应方面,其中测试样品由Micron^TM公司提供,最短沟道长度仅为0.16微米.内容包括一般短沟道效应、基板效应和漏极感应势垒降低效应(简称DIBL效应)等.研究表明,实验数据和BSIM模型结果较好吻合,证明文中方法的有效性以及较好的应用前景.     

A new small-signal MOSFET model and parameter extraction method for RF IC's application

In this paper, an accurate and simple small signal model of RF MOSFETs accounting for the distributed gate effect, the substrate parasitics and charge conservation is proposed. Meanwhile, a direct and accurate extraction method using linear regression approach for the components of the equivalent circuit of the MOSFET with S-parameters analysis is also proposed. The proposed model and extraction method are verified with the experimental data and an excellent agreement is obtained up to 10 GHz. The extraction results from the measured data for various bias conditions are presented. Also, the extracted parameters, such as transconductance g_m, match well with those obtained from DC measurements. Besides, it is shown that a significant error in circuit performances would be found if the charge conservation is not properly considered.     

基于MOSFET设计优化的功率驱动电路

在分析了功率MOSFET结构特性的基础上,讨论驱动电路的设计,从而优化MOSFET的驱动性能,提高设计的可靠性。     

纳米双栅MOS器件的二维量子模拟

利用非平衡格林函数法处理开放边界条件的薛定谔方程,与泊松方程自洽求解,在实空间实现了对纳米量级双栅MOS器件的二维量子模拟。与模空间法的仿真效率及模拟结果进行了比较,对栅极漏电流受栅介质、栅与源漏交叠、栅氧层厚度的影响进行了研究。     

模拟集成电路仿真中的UDSM MOSFET建模

对MOSFET器件特性、MOSFET建模方法和建模发展历程进行了回顾,重点分析了在模拟集成电路设计中较为流行的几种模型:BSIM3、EKV和SP2001模型,对其各自的优缺点进行了比较。结果表明,获得能够精确地预测高性能模拟系统的模型是很困难的;几种模型中,EKV模型在模拟集成电路的低功耗设计中具有一定的优势。     

一种JFET区域具有N型重掺杂的1200 V碳化硅浅槽平面MOSFET器件的设计与优化北大核心

介绍了一种在JFET区域采用浅槽N型重掺杂降低器件比导通电阻与开启损耗的1 200 V碳化硅平面栅MOSFET器件。采用浅槽结构设计，减小了器件栅源电容CGS及栅漏电容与栅源电容比值CGD/CGS,降低了器件的开启损耗。浅槽下方采用的N型重掺杂使得器件反型层沟道压降明显提高，使器件获得了更低的比导通电阻。仿真结果表明，相比于平面栅MOSFET器件，开启损耗降低了20%;相比于平面栅MOSFET与分裂栅MOSFET,器件比导通电阻分别减小了14%和17%。     

MOSFET的驱动保护电路的设计与应用

率场效应晶体管由于具有诸多优点而得到广泛的应用;但它承受短时过载的能力较弱,使其应用受到一定的限制。分析了MOSFET器件驱动与保护电路的设计要求;计算了MOSFET驱动器的功耗及MOSFET驱动器与MOS-FET的匹配;设计了基于IR2130驱动模块的MOSFET驱动保护电路。该电路具有结构简单,实用性强,响应速度快等特点。在驱动无刷直流电机的应用中证明,该电路驱动能力及保护功能效果良好。     

Harmonic and intermodulation performance of moderate inversion MOSFET transconductors

This article discusses the harmonic and intermodulation performance of moderate inversion MOSFET transconductors. The bulk of the nMOS transistor is tied to ground, at all levels of inversion, including moderate inversion and the transistor is operating in the saturation region where it behaves qualitatively as a constant current source. The current–voltage characteristic of the transistor is approximated using a Fourier-series model. Using this model, analytical expressions are obtained for amplitudes of the harmonics and intermodulation products resulting from multi-sinusoidal gate-to-source input voltages. The special case of a two equal-amplitude sinusoidal input is considered in detail and the results are compared with previously published results.     

Design and performance analysis of double-gate MOSFET over single-gate MOSFET for RF switch

In this paper, we have designed a double-gate MOSFET and compared its performance parameters with the single-gate MOSFET as RF CMOS switch, particularly the double-pole four-throw (DP4T) switch, for the wireless telecommunication systems. A double-gate radio-frequency complementary metal-oxide-semiconductor (DG RF CMOS) switch operating at the frequency of microwave range is investigated. This RF switch is capable to select the data streams from antennas for both the transmitting and receiving processes. We emphasize on the basics of the circuit elements (such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, and switching speed) required for the integrated circuit of the radio frequency sub-system of the DG RF CMOS switch and the role of these basic circuit elements are also discussed. These properties presented in the switches due to the double-gate MOSFET and single-gate MOSFET have been discussed.     

Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch

In this paper, we have analyzed the design parameters of Cylindrical Surrounding Double-Gate (CSDG) MOSFETs as an RF switch for the advanced wireless telecommunication systems. The proposed CSDG RF MOSFET is operated at the microwave regime of the spectrum. We emphasize on the basics of the circuit elements such as drain current, threshold voltage, resonant frequency, resistances at switch ON condition, capacitances, energy stored, cross talk and switching speed required for the integrated circuit of the radio frequency sub-system of the CSDG RF CMOS device and the physical significance of these basic circuit elements is also discussed. We observed that the total capacitance between the source to drain for the proposed CSDG MOSFET is more compared to the Cylindrical Surrounding Single-Gate (CSSG) MOSFET due to the greater drain current passing area of the CSDG MOSFET, which reveals that the isolation is better in the CSDG MOSFET compared to that of the simple double-gate MOSFET and single-gate MOSFET. We analyzed that the CSDG MOSFET stores more energy (1.4 times) as compared to the CSSG MOSFET. Therefore, the CSDG MOSFET has more stored energy. The ON-resistance of CSDG MOSFET is half than that of the double-gate MOSFET and single-gate MOSFET, which reveals that the current flow from source to drain in CSDG MOSFET is better than the double-gate MOSFET and single-gate MOSFET.     

多胞MOSFET器件的射频建模和参数提取

对纳米级金属氧化物半导体场效应管器件提出了改进的小信号模型.该改进模型中综合考虑了馈线的趋肤效应和器件多胞结构的影响.提取过程中, 根据可缩放规律, 由传统模型的参数推导出元胞参数.将模型应用于8×0.6×12 μm (栅指数×栅宽×元胞数量)、栅长为90 nm的MOSFET器件在1~40 GHz范围内的建模, 测试所得S参数和模型仿真所得S参数能够高度地吻合.     

Mobility degradation and transistor asymmetry impact on field effect transistor access resistances extraction

With the downscaling of MOSFETs the relative importance of access resistances on transistor behavior and thus on integrated circuits performance significantly increases. Several DC and Radio Frequency characterization techniques have been proposed in the literature to extract the access resistances. It has been demonstrated that the mobility degradation with the vertical electric field in advanced MOSFETs and the transistor asymmetry might strongly degrade the accuracy of the extracted resistance values. Based on simulation and experimental results, correction factors are proposed and guidelines are drawn to help the user for choosing the right extrinsic resistance extraction methodology depending on a few figures of merit associated to the measured data of the FET device. Based on our conclusions, a robust characterization method for deep-submicron devices is proposed and successfully applied to FinFETs.     

Effects of BOX engineering on analogue/RF and circuit performance of InGaAs-OI-Si MOSFET

InGaAs is an attractive choice as alternate channel material in n-channel metal oxide semiconductor transistor for high-performance applications. However, electrostatic integrity of such device is poor. In this paper, we present a comprehensive technology computer-aided design simulation-based study of the effect of scaling the thickness of the buried oxide (BOX) region and varying the dielectric constant of BOX material on the electrostatic integrity, analogue/radio frequency (RF) performance and circuit performance of InGaAs-on-Insulator device. Device with thin BOX layer gives better drain-induced barrier lowering performance which enhances output resistance. The carrier mobility remains almost constant with thinning of BOX layer up to certain value. By lowering the dielectric constant of the BOX material, it is further possible to improve the analogue and RF performance. Effect of BOX thickness scaling and role of BOX dielectric material on gain–frequency response of common source amplifier is also studied. It is observed that frequency response of the amplifier improves for thin BOX and with low dielectric constant-based material.     

Physics of Gate Modulated Resonant Tunneling (RT)-FETs: Multi-barrier MOSFET for steep slope and high on-current

A new concept of nanoscale MOSFET, the Gate Modulated Resonant Tunneling Transistor (RT-FET), is presented and modeled using 3D Non-Equilibrium Green’s Function simulations enlightening the main physical mechanisms. Owing to the additional tunnel barriers and the related longitudinal confinement present in the device, the density of state is reduced in its off-state, while remaining comparable in its on-state, to that of a MOS transistor without barriers. The RT-FET thus features both a lower RT-limited off-current and a faster increase of the current with V_G, i.e. an improved slope characteristic, and hence an improved I_on/I_off ratio. Such improvement of the slope can happen in subthreshold regime, and therefore lead to subthreshold slope below the kT/q limit. In addition, faster increase of current and improved slope occur above threshold and lead to high thermionic on-current and significant I_on/I_off ratio improvement, even with threshold voltage below 0.2 V and supply voltage V_dd of a few hundreds of mV as critically needed for future technology nodes. Finally RT-FETs are intrinsically immune to source-drain tunneling and are therefore promising candidate for extending the roadmap below 10 nm.     

MOSFET失配的研究现状与进展

特定工艺条件下的器件失配程度限制了射频／模拟集成电路的设计精度和成品率。电路设计者需要精确的MOSFET失配模型来约束电路优化设计,版图设计者需要相应的设计规则来减小芯片失配。本文介绍了MOSFET失配的基本概念;回顾了MOSFET模型的研究进展及相关的版图设计技术、计算机仿真方法;总结了MOSFET失酉己对电路性能的影响及消除技术。最后探讨了MOSFET失配的研究趋势。