一种12GHz的高增益低噪声放大器

通过分析GaAs pHEMT器件特性设计了一款两级高增益、低功耗的低噪声放大器.采用两级结构提高低噪声放大器的增益,设计了一种共用电流结构,降低了放大器的功耗,同时降低电路噪声.输入、输出匹配均采用LC阶梯匹配网络,具有良好的匹配性,并使用CAD软件对电路进行设计优化.电路仿真结果表明,在中心频率12 GHz下实现了增...     

一种低噪声放大器的自适应阻抗匹配网络模型的设计

为了解决微弱信号检测过程中的输入噪声匹配问题,文章根据低噪声放大器的噪声匹配特点设计了一种自适应阻抗匹配网络模型;该模型通过实时测算信号源阻抗和低噪声放大器最佳源阻抗的变化自动调整匹配网络的相关参数,从而达到输入阻抗匹配的目的;仿真实验结果表明,此模型在一定程度上能较为准确地实现低噪声放大器的噪声匹配,稳定性较好,解决了微弱信号检测中因源阻抗的变化引起的放大器噪声系数恶化、检测灵敏度下降等问题,具有一定的工程应用意义。     

采用新型电流舵结构的增益可调UWBLNA

基于TSMC 0.18μm CMOS工艺,设计了一款工作在3 GHz⁵ GHz频段的增益可调超宽带低噪声放大器(LNA)。LNA输入级采用局部反馈的共栅结构,实现了超宽带输入匹配和良好的噪声性能;放大电路级采用提出的新型电流舵结构,实现了放大器增益连续可调;输出级采用源极跟随器,获得了良好的输出匹配。利用ADS2009进行仿真验证,结果表明,在3 GHz5 GHz频段的增益可调超宽带低噪声放大器(LNA)。LNA输入级采用局部反馈的共栅结构,实现了超宽带输入匹配和良好的噪声性能;放大电路级采用提出的新型电流舵结构,实现了放大器增益连续可调;输出级采用源极跟随器,获得了良好的输出匹配。利用ADS2009进行仿真验证,结果表明,在3 GHz⁵ GHz工作频段内,LNA获得了25 dB的增益可调范围,最高增益达到24 dB,输入端口反射系数小于-11 dB,输出端口反射系数小于-14 dB,最小噪声系数为2.3 dB,三阶交调点(IIP3)为4 dBm,在1.2 V电压下,电路功耗仅为8.8 mW。     

一种新的ISM频段低噪声放大器设计方法

为解决ISM频段低噪声放大器降低失配与减小噪声之间的矛盾,提出了一种改善放大器性能的设计方法。分析了单项参数的变化规律,提出了提高综合性能的方法,给出了放大器封装模型的电路结构。对射频放大器SP模型和封装模型进行仿真。仿真结果表明,输入和输出匹配网络对放大器的性能有影响,所提出的设计方法能有效分配性能指标,为改善ISM频段低噪声放大器的性能提出了一种新的途径。     

用于FM调谐器的新式低噪声放大器设计

论文设计实现了一个用于单芯片FM调谐器的低噪声放大器,放大器采用0.6 um BiCMOS工艺实现.低噪声放大器采用匹配简单并且线性度很高的新式共基结构实现.仿真结果显示采用此结构的低噪声放大器的正向增益(S21)为24dB,信号频率范围内的噪声系数(Noise Figure)仅仅为2.5dB.输入3阶交调点(IIP3)为-15.25dB.本文中,我们将对该结构低噪声放大器进行具体的分析.     

航天GPS接收机的低噪声放大器设计

介绍一种用于航天GPS接收机的无源微带天线的低噪声放大器设计。内容涉及选择低噪声放大器的输入匹配网络及优化匹配参数;并通过实际测试验证了它在天线中应用的有效性。实验结果表明性能优于已有的星载GPS接收机天线。     

一种噪声优化的900MHz低噪声放大器设计

设计了一种900MHz的低噪声放大器,采用新的优化方法,同时获得了功率匹配和噪声匹配,在工作电流3．4mA时,得到了0．2dB的噪声系数,20dB的增益以及良好的隔离度和线性度。     

基于噪声消除技术的超宽带低噪声放大器设计

基于TSMC 0.18μm工艺研究3 GHz~5 GHz CMOS超宽带无线通信系统接收信号前端的低噪声放大器设计。采用单端转差分电路实现对低噪声放大器噪声消除的目的,利用串联电感作为负载提供宽带匹配。仿真结果表明,所设计的电路正向电压增益S21为17.8 dB~19.6 dB,输入、输出端口反射系数均小于-11 dB,噪声系数NF为2.02 dB~2.4 dB。在1.8 V供电电压下电路功耗为12.5 mW。     

基于切比雪夫网络修正的噪声优化超宽带LNA设计

基于TSMC 0.18μm CMOS工艺的研究,设计了一个应用于3~10 GHz超宽带无线通信系统接收前端的低噪声放大器。以经典的共源共栅的结构作为放大主架构,结合切比雪夫滤波器,实现超宽带输入匹配,并采用噪声消除技术优化LNA噪声性能。电路结构具有工作带宽大、输入匹配简单并且噪声性能优异的优点。仿真结果表明:在3~10 GHz频段内,S11和S22均小于-10 d B,S21为15 d B~10 d B,噪声系数NF为1.5 d B~2.3 d B,在1.8 V供电电压下电路功耗为14.5 m W。     

一种L波段低噪声放大器的设计与仿真

研究射频电路前端的天线信号放大和抑制噪声,进行了加快低噪声放大器的设计,提出了一种利用史密斯圆图和ADS软件快速设计和仿真LNA的方法.设计时输入端采用最佳噪声匹配,以获得较小的噪声系数;输出端采用输出共扼匹配,以获得较高的功率增益和较好的输出驻波比.通过对一个L波段低噪声放大器的噪声系数、功率增益、输入输出驻波比等参数进行仿真,结果验证了上述的方法.经反复调整后放大器在L波段内噪声系数小于1dB,增益达30dB,输出驻波比小于1.5,满足了设计要求,对从事LNA的设计来说有着重要的参考价值.     

3GHz～5GHz CMOS超宽带低噪声放大器设计

提出了一个低噪声、高线性的超宽带低噪声放大器(UWB LNA).电路由窄带PCSNIM LNA拓扑结构和并联低Q负载结构组成,采用TSMC 0.18 μm RFCMOS工艺,并在其输入输出端引入了高阶带通滤波器.仿真结果表明,在1.8V直流电压下LNA的功耗约为10.6 mW.在3 GHz～5 GHz 的超宽带频段内,...     

A 3.4 dB NF k‐band LNA with a tapped capacitor matching network in 65 nm CMOS technology

This article proposes a tapped capacitor network for low‐noise amplifier (LNA) input matching which can provide much broader bandwidth than traditional ones. According to the design, the implemented LNA can realize noise match and power match simultaneously, which will broaden LNA's bandwidth without introducing larger noise than traditional ones. In addition, input pad parasitic capacitance can be absorbed by the network. Then a k‐band LNA with the matching network designed in 65 nm CMOS technology is shown to demonstrate the performance of the matching network. The tested results show that frequency band of S₁₁ less than ?10 dB is about 17 GHz and minimum NF is about 3.4 dB. © 2014 Wiley Periodicals, Inc. Int J RF and Microwave CAE 25:146–153, 2015.     

一种0.8GHz～6GHz CMOS超宽带低噪声放大器设计

给出了一个针对0.8GHz～6GHz 的超宽带低噪声放大器 UWB LNA(ultra-wideband low noiseamplifier)设计。设计采用0.18μm RF CMOS 工艺完成。在0.8GHz～6GHz 的频段内,放大器增益 S21达到了17.6dB～13.6dB。输入、输出均实现良好的阻抗匹配,S11、S22均低于-10dB。噪声系数(NF)为2.7dB～4.6dB。在1.8V 工作电压下放大器的直流功耗约为12mW。     

A miniature low‐power ultra‐wideband low noise amplifier in 0.18 μm CMOS

A 0.18‐μm CMOS low‐noise amplifier (LNA) operating over the entire ultra‐wideband (UWB) frequency range of 3.1–10.6 GHz, has been designed, fabricated, and tested. The UWB LNA achieves the measured power gain of 7.5 ± 2.5 dB, minimum input matching of ?8 dB, noise figure from 3.9 to 6.3 dB, and IIP3 from ?8 to ?1.9 dBm, while consuming only 9 mW over 3–10 GHz. It occupies only 0.55 × 0.4 mm² without RF and DC pads. The design uses only two on‐chip inductors, one of which is such small that could be replaced by a bonding wire. The gain, noise figure, and matching of the amplifier are also analyzed. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

Design of 5.5 GHz linear low noise amplifier using post distortion technique with body biasing

A highly linear 5.5 GHz low noise amplifier (LNA) has been designed exploiting source inductive degeneration topology by using post distortion linearization techniques in 0.18 m CMOS technology. This technique improves the input third order intercept point \((IIP_{3})\) of a low noise amplifier. For enhancing the linearity, this technique used a diode connected MOSFET as IMD sinker and forward body biased which is done in cadence tool. The proposed low noise amplifier achieves high \(IIP_{3}\) by using two transistors, main and auxiliary transistors. Also source inductive degeneration topology is employed in the proposed LNA to optimize the noise figure (NF) and \(S_{11}\) at high frequency. In order to reduce power consumption and threshold voltage, Forward Body Biased technique was implemented. In this paper, the first section discusses the most widely used eight linearization techniques and in the second section, the proposed circuit is represented along with its employed topology, techniques and the simulated results. The proposed LNA achieves a simulated third order input intercept \((IIP_{3})\) of 9.20 dBm while consuming 10.8 mW from a power supply of 1.8 V. it also exhibits a measured gain of 11.34 dB and NF, NF of 2.33 dB.     

Analysis and design of a fully integrated CMOS low‐noise amplifier for concurrent dual‐band receivers

This article thoroughly analyzes a concurrent dual‐band low‐noise amplifier (LNA) and carefully examines the effects of both active and passive elements on the performance of the dual‐band LNA. As an example of the analysis, a fully integrated dual‐band LNA is designed in a standard 0.18‐μm 6M1P CMOS technology from the system viewpoint for the first time to provide a higher gain at the high band in order to compensate the high‐band signal's extra loss over the air transmission. The LNA drains 6.21 mA of current from a 1.5‐V supply voltage and achieves voltage gains of 14 and 22 dB, input S₁₁ of 15 and 18 dB, and noise figures of 2.45 and 2.51 dB at 2.4 and 5.2 GHz, respectively. © 2006 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2006.     

A CMOS low noise amplifier based on common source technique for ISM band application

In this paper a 2.45 GHz narrowband low noise amplifier (LNA) for wireless communication system is enunciated. The proposed CMOS Low Noise amplifier has been verified through cadence spectre RF simulation in standard UMC 90 nm CMOS process. The proposed LNA is designed by cascoding of two transistors; that is the common source transistor drives a common gate transistor. To achieve better power gain along with low noise figure, cascoding of two transistor and source degeneration technique is used and for low power consumption, the MOS transistors are biased in subthreshold region. At 2.45 GHz frequency, it exhibits power gain 31.53 dB. The S11, S22 and S12 of the circuit is ?9.14, ?9.22 and ?38.03 dB respectively. The 1 dB compression point of the circuit is ?16.89 dBm and IIP3 is ?5.70 dBm. The noise figure is 2.34 dB, input/output match of ?9.14 dB/?9.22 dB and power consumption 8.5 mW at 1.2 V.     

3～5GHz超宽带可变增益CMOS低噪声放大器的设计

基于TSMC 0.18μm RF CMOS工艺,设计了一款工作在3 GHz～5 GHz的增益连续可调CMOS低噪声放大器。采用RC电阻负反馈式结构以获得良好的输入匹配和噪声性能。通过改变第二级MOS管的偏流,在工作频段内获得了36.5 dB的连续增益可调。     

A broadband hybrid GaN cascode low noise amplifier for WiMax applications

This article reports a Microstrip design for low noise amplifier (LNA) using a packaged commercial GaN‐on‐SiC high electron mobility transistor (HEMT). A cascode configuration with an inter‐stage matching and an independent biasing technique was used. A lumped elements design was first developed, analyzed, and simulated in ADS. Then the design was implemented using microstrip technology and simulated using the momentum EM simulation in ADS. The LNA is easy to fabricate, has a low cost, and can be easily modified for other applications. The proposed GaN LNA showed a gain of 13.5 dB with a noise figure (NF) of 3 dB from 2.8 to 3.8 GHz.     

A straightforward design technique for narrowband multi‐stage low‐noise amplifiers with I/O conjugate match

Low‐noise amplifier (LNA) designers often struggle to simultaneously satisfy gain, noise, stability, and I/O matching requirements. In this article, a novel design technique, tailored for two‐stage low‐noise amplifiers, is presented. The proposed design method is completely deterministic and exploits inductive source degeneration to obtain a two‐stage LNA featuring perfect input and output match together with low noise figure (NF) and a pre‐determined gain, including stability analysis. A novel flowchart is provided together with the corresponding design chart that contains gain, matching, and stability information, therefore addressing all key figures‐of‐merit of a linear amplifier. The design chart is easily implementable in commercial Electronic Design Automation software, to aid designers in the difficult task of selecting the appropriate source degeneration inductor value. The noise performance, on the other hand, is the best possible since the matching networks are designed to provide the input of the two Field Effect Transistors with the optimum termination for noise. The design method is validated with two separate test vehicles operating respectively at Ka‐band (26.5‐31.5 GHz) and K‐band (20.0‐24.0 GHz). The realized Monolithic Microwave Integrated Circuits exhibit 18 dB gain for both versions, NF of 1.5 and 1.2 dB, respectively for the Ka‐band and K‐band version. Input and output matching are typically better than 12 and 15 dB.