Pulse frequency modulation based CMOS image sensor for subretinal stimulation

We have developed a CMOS image sensor based on pulse frequency modulation for subretinal implantation. The sensor chip forms part of the proposed intraocular retinal prosthesis system where data and power transmission are provided wirelessly from an extraocular unit. Image sensing and electrical stimulus are integrated onto the same chip. Image of sufficient resolution has been demonstrated using 16/spl times/16 pixels. Biphasic current stimulus pulses at above threshold levels of the human retina (500 /spl mu/A) at varying frame rates (4 Hz to 8 kHz) have been achieved. The implant chip was fabricated using standard CMOS technology.     

An implantable multielectrode array with on-chip signal processing

This active probe can be used for the long-term recording of extracellular neural biopotentials and as a basis for closed-loop neural prostheses. The probe incorporates on-chip circuitry for amplifying, multiplexing, and buffering neural signals recorded from ten recording electrodes spaced 100-/spl mu/m apart. It requires only three leads and operates from a single 5-V supply. On-chip self-test circuitry for testing electrode impedance levels is provided. The on-chip circuitry is fabricated in a die area of 1.3 mm/SUP 2/ using 6-/spl mu/m LOCOS enhancement-depletion NMOS technology, and dissipates 5 mW of power. The probe is 4.7 mm long and 15 /spl mu/m thick, and has a shank which tapers from 160 /spl mu/m near the base to less than 15 /spl mu/m near the tip.     

A W-band InAs/AlSb low-noise/low-power amplifier

The first W-band antimonide based compound semiconductor low-noise amplifier has been demonstrated. The compact 1.4-mm/sup 2/ three-stage co-planar waveguide amplifier with 0.1-/spl mu/m InAs/AlSb high electron mobility transistor devices is fabricated on a 100-/spl mu/m GaAs substrate. Minimum noise-figure of 5.4dB with an associated gain of 11.1 dB is demonstrated at a total chip dissipation of 1.8 mW at 94 GHz. Biased for higher gain, 16/spl plusmn/1 dB is measured over a 77-103 GHz frequency band.     

A true single-phase energy-recovery multiplier

In this paper, we present the design and experimental evaluation of an 8-bit energy-recovery multiplier with built-in self-test logic and an internal single-phase sinusoidal power-clock generator. Both the multiplier and the built-in self-test have been designed in SCAL-D, a true single-phase adiabatic logic family. Fabricated in a 0.5-/spl mu/m standard n-well CMOS process, the chip has an active area of 0.47 mm/sup 2/. Correct chip operation has been verified for clock rates up to 140 MHz. Moreover, chip dissipation measurements correlate well with HSPICE simulation results. For a selection of biasing conditions that yield correct operation at 140 MHz, total measured average dissipation for the multiplier and the power-clock generator is 250 pJ per operation.     

A high-speed multiplier using a redundant binary adder tree

A 16-bit /spl times/ 16-bit multiplier for 2 two's-complement binary numbers based on a new algorithm is described. This multiplier has been fabricated on an LSI chip using a standard n-E/D MOS process technology with a 2.7-/spl mu/m design rule. This multiplier is characterized by use of a binary tree of redundant binary adders. In the new algorithm, n-bit multiplication is performed in a time proportional to log/SUB 2/ n and the physical design of the multiplier is constructed of a regular cellular array. This new algorithm has been proposed by N. Takagi et al. (1982, 1983). The 16-bit/spl times/16-bit multiplier chip size is 5.8 /spl times/ 6.3 mm/SUP 2/ using the new layout for a binary adder tree. The chip contains about 10600 transistors, and the longest logic path includes 46 gates. The multiplication time was measured as 120 ns. It is estimated that a 32-bit /spl times/ 32-bit multiplication time is about 140 ns.     

16-wavelength gain-coupled DFB laser array with fine tunability

16-wavelength semiconductor laser array with fine wavelength tunability is demonstrated, utilizing gain-coupled distributed feedback (DFB) lasers with different ridge waveguide widths. Besides the coarse tuning by the ridge widths, the fine post-fabrication tunability for individual lasers in the array is achieved with a Ti thin-film resistor integrated on the chip. Due to the gain-coupling effect, 16 single-mode lasing wavelengths around 1.55 /spl mu/m in /spl sim/1 nm spacing are obtained simultaneously. An effective fine-tuning up to 1 nm is observed at a moderate heating power of 100 mW.     

A 2-Gb/s optical transceiver with accelerated bit-error-ratio test capability

Accelerated bit-error-ratio (BER) measurement techniques using specialized test equipment are widely used for rapidly verifying the low BER (<10/sup -12/) of high-performance optical links. However, once these links are deployed in the field, it takes days to weeks to complete such BER measurements using a conventional testing method. This paper describes an optical transceiver architecture with on-chip accelerated BER measurement mechanics that reduces "in the field" BER testing time to minutes. The approach described in this paper uses an integrated interference generator to degrade receiver performance and raise the BER to a range that allows a substantially reduced measurement time. Values of BER versus the amount of interference are then extrapolated to the point of zero artificial degradation for actual BER. A 0.5-/spl mu/m complementary metal-oxide-semiconductor, 2-Gb/s, four-channel optical transceiver chip was designed, fabricated, and tested to serve as a vehicle for verifying the concept. The experimental results show excellent agreement between the extrapolated and actual BER values. The architecture described here points to a practical built-in self-test capability for optical links within high-performance digital systems, specifically in board- and backplane-level interconnections.     

A 16384-bit high-density CCD memory

A 16384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 3.45/spl times/4.29 mm/SUP 2/ (136/spl times/169 mil/SUP 2/), fits a standard 16-pin package, and is organized as four separate shift registers of 4096 bits, each with its own data input and data output terminals. A two-level polysilicon gate n-channel process was used for device fabrication. A condensed serial-parallel-serial (CSPS) structure was found to provide the highest packing density. Only two external clocks are required driving capacitances of 60 pF each at one-half the data transfer rate. Operations at data rates of 100 kHz to 10 MHz have been demonstrated experimentally, the on-chip power dissipation at 10 MHz being less than 20 /spl mu/W/bit.     

A biologically inspired analog IC for visual collision detection

We have designed and tested a single-chip analog VLSI sensor that detects imminent collisions by measuring radially expanding optic flow. The design of the chip is based on a model proposed to explain leg-extension behavior in flies during landing approaches. We evaluated a detailed version of this model in simulation using a library of 50 test movies taken through a fisheye lens. The algorithm was evaluated on its ability to distinguish movies ending in collisions from movies in which no collision occurred. This biologically inspired algorithm is capable of 94% correct performance in this task using an ultra-low-resolution (132-pixel) image as input. A new elementary motion detector (EMD) circuit was developed to measure optic flow on a CMOS focal-plane sensor. This EMD circuit models the bandpass nature of large monopolar cells (LMCs) immediately postsynaptic to photoreceptors in the fly visual system as well as a saturating multiplication operation proposed for Reichart-type motion detectors. A 16/spl times/16 array of two-dimensional motion detectors was fabricated in a standard 0.5-/spl mu/m CMOS process. The chip consumes 140 /spl mu/W of power from a 5 V supply. With the addition of wide-angle optics, the sensor is able to detect collisions 100-400 ms before impact in complex, real-world scenes.     

Low-voltage high-speed travelling wave InGaAsP-InP phase modulator

A high-speed low-drive-voltage travelling wave electrodes InGaAsP-InP phase modulator operated at 1.55 /spl mu/m is demonstrated. The modulator is fabricated using a multiple quantum-well optical waveguide with an on chip integrated termination resistor. A small signal bandwidth of 35 GHz and a V/spl pi/ of 1.8 V has been demonstrated.     

Analysis and characterization of device variations in an LSI chip using an integrated device matrix array

For future large-scale integration design technology, the device matrix array (DMA), which precisely evaluates within-die variation in device parameters, has been developed. The DMA consists of a 14-by-14 array of common units. The unit size is 240 by 240 /spl mu/m, and each unit contains 148 measurement elements (52 transistors, 30 capacitors, 51 resistors, and 15 ring oscillators). The element selection and precise measurement are achieved with low parasitic resistance measurement buses and leakage-controlled switching circuits, which allow the measurement accuracy for a transistor, resistor, or capacitor of 90 pA, 11 m/spl Omega/, and 23 aF, respectively, in the 3/spl sigma/ range. The ability to obtain 29 008 samples from a chip enables statistical analysis of the variation in 148 elements of each chip with 240-/spl mu/m spatial resolution. This high resolution and large sample number allows us to precisely decompose the data into systematic and random variation parts with newly developed fourth-order polynomial fitting. Our methodology has been verified using a test chip fabricated by a 130-nm CMOS process with a 100-nm physical gate length and five Cu interconnect layers. In MOSFETs, the random part was dominant and indicated a certain /spl sigma/ value in every chip. In the case of the interconnect layers, the random and systematic parts of the resistance and the capacitance indicated variance fluctuations. By chip, by item, by size, by structure, random or systematic, the /spl sigma/ values of each variation show inconsistency which we believe is attributable to the Cu process. The correlation coefficients of systematic part between device element and ring oscillator frequency shown very high value (0.87-0.98), and those of a random part were low enough (-0.10-0.22) to prove the accuracy of decomposition.     

A 20 ns 64K (4K/spl times/16) NMOS RAM

A 64K (4K/spl times/16) NMOS RAM is described which uses new circuit techniques and design concepts to achieve an average nominal access time of 20 ns. The RAM was built using a relatively straightforward NMOS technology with single-level metal, single-level polycide, an average minimum feature size of 1.7 /spl mu/m, and an effective channel length of 1.2 /spl mu/m. The chip is organized physically into four 16K blocks. Cell area is 292 /spl mu/m/SUP 2/ with a chip area of 32.6 mm/SUP 2/. A four-device split-wordline cell was used to reduce the wordline delay. Chip organization, simplified clocking and timing, and new circuits were especially important for improved performance. An address buffer with internal reference, a switched decoupled bootstrapped decoder, and a self-timed sense amplifier are described.     

A 55-ns 16-Mb DRAM with built-in self-test function usingmicroprogram ROM

A single 5-V power supply 16-Mb dynamic random-access memory (DRAM) has been developed using high-speed latched sensing and a built-in self-test (BIST) function with a microprogrammed ROM, in which automatic test pattern generation procedures were stored by microcoded programs. The chip was designed using a double-level Al wiring, 0.55-μm CMOS technology. As a result, a 16-Mb CMOS DRAM with 55-ns typical access time and 130-mm² chip area was attained by implementing 4.05-μm² storage cells. The installed ROM was composed of 18 words×10 b, where the marching test and checkerboard scan write/read test procedures were stored, resulting in successful self-test operation. As the BIST circuit occupies 1 mm² and the area overhead is about 1%, it proves to be promising for large-scale DRAMs     

A 500-MHz 16*16 complex multiplier using self-aligned gate GaAs heterostructure FET technology

A 16*16-bit complex multiplier using self-aligned gate GaAs heterostructure FET technology has been demonstrated. The multiplier uses a modified Booth's algorithm and three stages of pipeline with an embedded accumulator to allow the computation of a complex multiply function. A total of 4500 gates and over 20000 devices are required to implement this function and self-test functions. The chip produces a 20-bit output allowing 40 bits to describe a complex number result. Direct coupled NOR-gate FET logic was used throughout. The complex multiplier operated at a clock rate of 520 MHz with a power dissipation of 4 W under self-test. This corresponds to an average 'loaded' gate delay of 96 ps at 0.89 mW/gate. It also means that the multiplier produces a complex product, generated using four real multiplications and two additions, in less than 8 ns. This result demonstrates the high-speed capability of LSI digital circuits fabricated using MBE-grown GaAs heterostructure FET technology.<>     

A 16-Mb MRAM featuring bootstrapped write drivers

A 16-Mb magnetic random access memory (MRAM) is demonstrated in 0.18-/spl mu/m three-Cu-level CMOS with a three-level MRAM process adder. The chip, the highest density MRAM reported to date, utilizes a 1.42/spl mu/m/sup 2/ 1-transistor 1-magnetic tunnel junction (1T1MTJ) cell, measures 79 mm/sup 2/ and features a /spl times/16 asynchronous SRAM-like interface. The paper describes the cell, architecture, and circuit techniques unique to multi-Mb MRAM design, including a novel bootstrapped write driver circuit. Hardware results are presented.     

A self-testing 2-/spl mu/m CMOS chip set for FFT applications

A chip set for high-speed radix-2 fast Fourier transform (FFT) applications up to 512 points is described. The chip set comprises a (16+16)/spl times/(12+12)-bit complex number multiplier, and a 16-bit butterfly chip for data reordering, twiddle factor generation, and butterfly arithmetic. The chips have been implemented using a standard cell design methodology on a 2-/spl mu/m bulk CMOS process. Three chips implement a complex FFT butterfly with a throughput of 10 MHz, and are cascadable up to 512 points. The chips feature an offline self-testing capability.     

A transmit/receive IF chip set for WCDMA mobiles in 0.35 /spl mu/m CMOS

An implementation of the IF section of WCDMA mobile transceivers with a set of two chips fabricated in an inexpensive 0.35-/spl mu/m two-poly three-metal CMOS process is presented. The transmit/receive chip set integrates quadrature modulators and demodulators, wide dynamic range automatic gain control (AGC) amplifiers, with linear-in-decibel gain control, and associated circuitry. This paper describes the problems encountered and the solutions envisaged to meet stringent specifications, with process and temperature variations, thus overcoming the limitations of CMOS devices, while operating at frequencies in the range of 100 MHz-1 GHz. Detailed measurement results corroborating successful application of the new techniques are reported. A receive AGC dynamic range of 73 dB with linearity error of less than /spl plusmn/2 dB and spread of less than 5 dB for a temperature range of -30/spl deg/C to +85/spl deg/C in the gain control characteristic has been measured. The modulator measurement shows a carrier suppression of 35 dB and sideband/third harmonic suppression of over 46 dB. The core die area of each chip is 1.5 mm/sup 2/.     

A new CMOS pixel structure for low-dark-current and large-array-size still imager applications

A pixel structure for still CMOS imager application called the pseudoactive pixel sensor (PAPS) is proposed and analyzed in this paper. It has the advantages of a low dark current, high signal-to-noise ratio, and a high fill factor over the conventional passive pixel sensor imager or active pixel sensor imager. The readout circuit called the zero-bias column buffer-direct-injection structure is also proposed to suppress both the dark current of the photodiode and the leakage current of row switches by keeping both biases of photodiode and the parasitic p-n junction in the column bus at or near zero voltage. The improved double delta sampling circuits are also used to suppress fixed pattern noise, clock feedthrough noise, and channel charge injection. An experimental chip of the proposed PAPS CMOS imager with the format of 352/spl times/288 (CIF) has been fabricated by using a 0.25-/spl mu/m single-poly-five-level-metal (1P5M) n-well CMOS process. The pixel size is 5.8 /spl mu/m/spl times/5.8 /spl mu/m. The pixel readout speed is from 100 kHz to 10 MHz, corresponding to the maximum frame rate above 30 frames/s. The proposed still CMOS imager has a fill factor of 58%, chip size of 3660 /spl mu/m/spl times/3500 /spl mu/m, and power dissipation of 24 mW under the power supply of 3.3 V. The experimental chip has successfully demonstrated the function of the proposed new PAPS structure. It can be applied in the design of large-array-size still CMOS imager systems with a low dark current and high resolution.     

16.7-fA/cell tunnel-leakage-suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors

Tunnel-leakage currents become the dominant form of leakage as MOS technology advances. An electric-field-relaxation scheme that suppresses these currents is described. Cosmic-ray-induced multierrors have now become a serious problem at sea level. An alternate error checking and correction architecture for the handling of such errors is also described, along with the application of both schemes in an ultralow-power 16-Mb SRAM. A test chip fabricated by using 0.13-/spl mu/m CMOS technology showed per-cell standby-current values of 16.7 fA at 25/spl deg/C and 101.7 fA at 90/spl deg/C. The chip provided a 99.5% reduction in soft errors under accelerated neutron-exposure testing.     

A new type of demountable optical device for coupling single-mode planar waveguides to a multifiber array using passive alignment

A novel demountable optical device is developed for coupling single-mode waveguides to a multifiber array using passive alignment. This device is fabricated by forming V-grooves on a waveguide chip and precisely molding both end portions of the chip. The 1/spl times/8 coupling device exhibits a low insertion loss of 10.7 dB and a small loss change of /spl plusmn/0.2 dB for 100 reconnections.