Variability aware SVM macromodel based design centering of analog circuits

Design centering is the term used for a procedure of obtaining enhanced parametric yield of a circuit despite the variations in device and design parameters. The process variability in nanometer regimes manifest into variations in these devices and design parameters. During design space exploration of analog circuits, a methodology to find design-instances with better yield is necessitated; this would ensure that the circuit will function as per specifications after fabrication, even with impact of statistical variations. We need to evaluate circuit performance for a given instance of a circuit-design identified by possessing a set of nominal values of device-design parameters. A lot of instances need be searched, having different sizes for a given circuit topology. HSPICE is very compute intensive. Instead, we employ macromodeling approach for analog circuits based on support vector machine (SVM), which enables efficient evaluation of performance of such circuits of different sizing during yield optimization loops. These performance macromodels are found to be as accurate as SPICE and at the same time, time-efficient for use in sizing of analog circuits with optimal yield. Process variability aware SVM macromodels are first trained and then used inside the Genetic algorithm loops for design centering of different circuits, subsequently resulting into sized-circuit instances having optimal yield. Post design centering, the sized circuits will be able to provide functions as per specifications upon fabrication. The application of this design centering approach as process variability analysis tool is illustrated on various circuits e.g. two stage op amp, voltage controlled oscillator and mixer circuit with layouts drawn into 90?nm UMC technology (Euro-practice).     

MOS current mode circuits: analysis, design, and variability

The interest in MOS current-mode logic (MCML) is increasing because of its ability to dissipate less power than conventional CMOS circuits at high frequencies, while providing an analog friendly environment. Moreover, automated design methodologies are gaining attention by circuit designers to provide shorter design cycles and faster time to market. This paper provides designers with an insight to the different tradeoffs involved in the design of MCML circuits to efficiently and systematically design MCML circuits. A comprehensive analytical formulation for the design parameters of MCML circuits using the BSIM3v3 model is introduced. In addition, a closed-form expression for the noise margin of two-level MCML circuits is derived. In order to verify the validity of the analytical formulations, an automated design methodology for MCML circuits is proposed to overcome the complexities of the design process. The effectiveness of the design methodology and the accuracy of the analytical formulations are tested by designing several MCML benchmarks built in a 0.18-/spl mu/m CMOS technology. The error in the required performance in the designed circuits is within 11% when compared to HSPICE simulations. A worst case parameter variations modeling is presented to investigate the impact of variations on MCML circuits as well as designing MCML circuits for variability. Finally, the impact of variations on MCML circuits is investigated with technology scaling and different circuit architectures.     

Power partition and emitter size optimization for bipolar ECLcircuit

An automated approach for optimizing the performance of a bipolar ECL circuit is described. A quadratic equation representing an approximate surface is used to express the circuit delay in terms of the power partition and current densities in the current-switch and emitter-follower stages. During the iteration of the optimization process, the optimum obtained from each approximate surface is used as the nominal point for the next iteration. As the nominal point converges to the optimal, the approximate surface converges to a section of the real optimum surface. This methodology transforms the circuit optimization into a multivariable optimization problem and is shown to provide an optimum design with circuit analysis accuracy. The design considerations for high-performance ECL circuits are also discussed     

Mass characterisation of organic transistors and Monte-Carlo circuit simulation

We present a method for designing organic circuits using Monte-Carlo based circuit simulation. The organic devices suffer from mismatch and variations that are due to systematic and random fluctuations in the process and material characteristics. In this work, we have used the variable range hopping model to extract the model parameters using a mass characterisation technique. The parameter fluctuations of organic transistors are taken into account and process corners determined based on static (noise margin) and transient (delay) characteristics. Thus a methodology is developed to find the parameter range of individual devices, within which the circuits are having good performance, for instance inverters working with desired noise margin. We also found out the critical parameters of the transistor, that predominantly affects the static and transient performance of an inverter. These critical parameters can be provided as input to the process engineers to fine tune the process. This information can also be used in developing robust circuit design techniques, which can overcome the variation effects of these critical parameters. Thus, a mass characterisation of transistors combined with the proposed method, allows robust circuit design in the presence of huge process variations.     

Statistical computer-aided design for microwave circuits

A useful methodology for microwave circuit design is presented. A statistical technique known as Design of Experiments is used in conjunction with computer-aided design (CAD) tools to obtain simple mathematical expressions for circuit responses. The response models can then be used to quantify response trade-offs, optimize designs, and minimize circuit variations. The use of this methodology puts the designer's intelligence back into design optimization while making “designing for circuit manufacturability” a more systematic and straightforward process. The method improves the design process, circuit performance, and manufacturability. Two design examples are presented in context to the new design methodology     

Body Bias Voltage Computations for Process and Temperature Compensation

With continued scaling into the sub-90-nm regime, the role of process, voltage, and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. These variations can cause the delay and the leakage of the chip to vary significantly from their expected values, thereby affecting the yield. Circuit designers have proposed the use of threshold voltage modulation techniques to pull back the chip to the nominal operational region. One such scheme, known as adaptive body bias (ABB), has become extremely effective in ensuring optimal performance or leakage savings. Our work provides a means to efficiently compute the body bias voltages required for ensuring high performance operation in gigascale systems. We provide a computer-aided design (CAD) perspective for determining the exact amount of bias voltages that can compensate both temperature and process variations. Mathematical models for delay and leakage based on minimal tester measurements are built, and a nonlinear optimization problem is formulated to ensure highest frequency operation under all conditions, and thereby minimize the overall circuit leakage. Three different algorithms are presented and their accuracies and runtimes are compared. The algorithms have been applied to a wide range of process and temperature corners, for a 65- and 45-nm technology node-based process. A suitable implementation mechanism has also been outlined.     

Impact of Supply Voltage Variations on Full Adder Delay: Analysis and Comparison

In this paper, some of the most practically interesting full adder topologies are analyzed in terms of their delay dependence on the supply voltage fluctuations, which are a major contribution to the delay uncertainty, which in turn limits the speed performance of current VLSI circuits. Analytical models of the delay sensitivity with respect to supply variations are derived by following a simplified circuit analysis, and the resulting expressions are simple enough to afford a deeper insight into the impact of supply voltage variations on each topology. The models are shown to be sufficiently accurate through simulations with CMOS technologies having a minimum feature size ranging from 90 nm to 0.35 mum. Several interesting properties and design considerations are derived from these models, and the effect of the supply voltage scaling, technology scaling, transistor sizing, and input transition time is discussed. Strategies to evaluate the delay sensitivity since the early design phases (e.g., from ring oscillator measurements) are also introduced. As a fundamental result, it is shown that the delay sensitivity to supply variations will increase in the next technology nodes, thus, it is expected that controlling the supply variations will be an increasingly important issue in the design of the next generation VLSI circuits. The proposed methodology is also analyzed in the case of more general digital circuits, and is used to estimate the impact of the inter-die threshold voltage variations on the delay of the considered full adder topologies     

Realistic statistical worst-case simulations of VLSI circuits

A simple and cost-effective method for evaluating the parametric product manufacturability of VLSI circuits is presented. The method, named gradient analysis, enables designers to predict the standard deviation of the circuit performance from measured or specified design parameter variations. This method, with a minimum extra design cost, avoids the overdesign associated with the traditional prediction of the worst-case performance of VLSI circuits. Gradient analysis also provides designers with information on the sensitivity of the circuit performance variations to the design parameter variations. In this way the key design parameters for process monitoring and control are identified. Experimental qualification of the method is discussed based on development and production data of VLSI products such as high-speed 1.2 μm 64 K CMOS static RAMs (SRAMs),     

Reversed Temperature-Dependent Propagation Delay Characteristics in Nanometer CMOS Circuits

The supply voltage to threshold voltage ratio is reduced with each new technology generation. The gate overdrive variation with temperature plays an increasingly important role in determining the speed characteristics of CMOS integrated circuits. The temperature-dependent propagation delay characteristics, as shown in this brief, will experience a complete reversal in the near future. Contrary to the older technology generations, the speed of circuits in a 45-nm CMOS technology is enhanced when the temperature is increased at the nominal supply voltage. Operating an integrated circuit at the prescribed nominal supply voltage is not preferable for reliable operation under temperature fluctuations. A design methodology based on optimizing the supply voltage for temperature-variation-insensitive circuit performance is proposed in this brief. The optimum supply voltage is 45% to 53% lower than the nominal supply voltage in a 180-nm CMOS technology. Alternatively, the optimum supply voltage is 15% to 35% higher than the nominal supply voltage in a 45-nm CMOS technology. The speed and energy tradeoffs in the supply voltage optimization technique are also presented     

An Effective Power-Aware At-Speed Test Methodology for IP Qualification and Characterization

Advanced nanometer technologies have led to a drastic increase in operational frequencies resulting in the performance of circuits becoming increasingly vulnerable to timing variations. The increasing process spread in advanced nanometer nodes poses considerable challenges in predicting post-fabrication silicon performance from timing models. Thus, there is a great need to qualify basic building structures on silicon in terms of critical parameters before they could be integrated within a complex System-on-Chip (SoC). The work of this paper presents a configurable circuit and an associated power-aware at-speed test methodology for the purpose of qualifying basic standard cells and complex IP structures to detect the presence of timing faults. Our design has been embedded within test-chips used for the development of the 28 nm Fully Depleted Silicon On Insulator (FD-SOI) technology node. The relevant silicon results and analysis validate the proposed power-aware test methodology for qualification and characterization of IPs and provide deeper insights for process improvements.     

Quantized Probability Circuit Design Principles Applied to Linear Circuits

A circuit design method for linear circuits is needed which will adequately predict circuit per formance as a function of component tolerances. This paper describes a method which weights the probable component variation from its nominal value into one of three groups; the group assignment depends on how seriously the component variation affects over-all performance This technique, identified as the quantized probability design (QPD) method, is compared with the absolute worst case (AWC), the Taylor worst case (TWC), and the uniform probability (UP) methods. The QPD procedure is given, based on the circuit performance equation. Two linear circuit applications are presented and analyzed whic show the effect each component will have on circuit performance. A comparison of design methods shows that the quantized probability design predicts less amplifier gain variation. Actual experience has shown that a closer correlation exists with the quantized probability design method, and therefore its use for linear circuits is recommended.     

A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies

As CMOS technology scales deeper into the nanometer regime, factors such as leakage power and chip temperature emerge as critically important concerns for high-performance VLSI design. Consequently, enhancing processing performance is no longer the most important factor that dominates future circuit design considerations. This paper, for the first time, proposes a systematic methodology to determine a generalized design optimization metric for simultaneously trading-off power and performance in nanometer scale integrated circuits to achieve design-specific targets. The methodology incorporates interconnect effects as well as electrothermal couplings between substrate temperature, power, and performance for nanometer scale design optimization. Implications of choosing a specific design optimization metric on power, performance, and operating temperature are illustrated and discussed. The proposed methodology is shown to provide a more meaningful optimization metric (for power-performance tradeoff analysis) and basis, with considerations of chip-level thermal management including maximum allowable operating temperature and packaging/cooling solutions. Furthermore, implications of CMOS technology scaling and parameter variations on the proposed methodology are discussed.      

Performance-Oriented Parameter Dimension Reduction of VLSI Circuits

To account for the growing process variability in modern VLSI technologies, circuit models parameterized in a multitude of parametric variations are becoming increasingly indispensable in robust circuit design. However, the high parameter dimensionality can introduce significant complexity and may even render variation-aware performance analysis and optimization completely intractable. We present a performance-oriented parameter dimension reduction framework to reduce the modeling complexity associated with high parameter dimensionality. Our framework has a theoretically sound statistical basis, namely, reduced rank regression (RRR) and its various extensions that we have introduced for more practical VLSI circuit modeling. For a variety of VLSI circuits including interconnects and CMOS digital circuits, it is shown that this parameter reduction framework can provide more than one order of magnitude reduction in parameter dimensionality. Such parameter reduction immediately leads to reduced simulation cost in sampling-based performance analysis, and more importantly, highly efficient parameterized sub-circuit models that are instrumental in tackling the complexity of variation-tolerance VLSI system design.      

An adjustable accuracy model for VLSI analog circuits using lookup tables

The successful design of analog VLSI circuits requires both a precise and computationally efficient device model. An accuracy adjustable table look-up modeling methodology, using a multidimensional gradient data tracing methodology and an interpolation technique with monotonicity, has been developed for analog circuit simulation. Using this technique, several table models with different accuracies have been compiled and utilized to simulate analog circuits such as a CMOS push-pull inverter and cascode opamp with a regulated current sink without loss of computational efficiency. This accuracy adjustable modeling approach has the ability to compromise between table size (speed) and model accuracy. Model accuracy can be emphasized in a specific device operation range where accuracy is critical to circuit performance by utilizing an accuracy partitioning methodology. A generic modeling methodology has been successfully generalized with dependent and independent variables applicable to several technologies, including CMOS, bipolar, and GaAs technologies. Simulation results from table models compiled by this new approach are not only more accurate but also more computationally efficient (faster) than conventional device models such as SPICE level 2 and BSIM models.     

Yield optimization of integrated circuits

A design approach is presented that optimizes the component areas of integrated circuits so as to maximize the yield. The performance index to be optimized is defined as the chip yield divided by the chip area, which corresponds to the number of good chips in a wafer. The area of each component is determined to maximize this performance index by a nonlinear programming technique. The design of integrated circuits with respect to the yield may be mostly narrowed down to the determination of component areas, since the process parameters cannot be adjusted individually for each circuit component. This design approach is described in more detail for the kinds of components whose surface areas cannot be uniquely determined by their nominal parameter values. As a demonstration, the width of a diffused resistor in bipolar integrated circuits was optimized for some example circuits. Some useful results have been obtained for the design of circuit patterns.     

Thermal macromodelling of integrated circuits

Most of the existing macromodels for integrated circuits (ICs) today have characteristics that are independent of temperature. The macromodels usually assume the IC operates at a fixed temperature, frequently taken to be a defined nominal temperature representing room temperature. This is in spite of the fact that IC characteristics are strongly dependent on the temperature of the device. In this paper, we discuss a methodology for thermal macromodelling of ICs to take into account the temperature dependence of the IC being modelled. The methodology may be used to convert a macromodel that models no thermal effects into one that models both thermal and electrothermal effects. The methodology is applied to a positive voltage regulator and is implemented in the circuit simulator PSpice.     

Reliability optimization of analog integrated circuits considering the trade-off between lifetime and area

The reliability of analog integrated circuits becomes a major concern for the semiconductor industry as technology continuously scales. Among the many contributing factors, manufacturing process induced parameter variations and lifetime operational-condition-dependent transistor aging are two major hurdles limiting the reliability of analog circuits. Process variations mainly influence the parametric yield value of the fresh circuits, while transistor aging due to physical effects, such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), will cause another yield loss during circuit lifetime. In the past decades, the two issues were mainly studied separately by various communities, but analog designers nowadays need an accurate yet efficient method to analyze and optimize their circuits during the design phase, to ensure a more robust design tolerant of such joint effects.This paper proposes an efficient method for sizing of analog circuits for reliability. It is based on the analysis and optimization of the fresh worst-case distance value for each circuit performance, which can be used to characterize the robustness of circuits considering process variations and aging effects in terms of x-sigma. The fresh and aged sizing rules as well as the maximum area constraints are checked during the optimization. The trade-off between the circuit lifetime and the price we pay in terms of layout area is studied in detail. According to the result of this trade-off analysis, a longer circuit lifetime requires more total area to be spent in layout, and designers can ensure the circuit robustness with certain layout area consumption.     

Analog circuit design optimization based on symbolic simulation andsimulated annealing

A methodology for the automatic design optimization of analog integrated circuits is presented. A non-fixed-topology approach is realized by combining the optimization program OPTIMAN with the symbolic simulator ISAAC. After selecting a circuit topology, the user invokes ISAAC to model the circuit. ISAAC generates both exact and simplified analytic expressions, describing the circuit's behavior. The model is then passed to the design optimization program OPTIMAN. This program is based on a generalized formulation of the analog design problem. For the selected topology, the independent design variables are automatically extracted and OPTIMAN sizes all elements to satisfy the performance constraints, thereby optimizing a user-defined design objective. The global optimization method used on the analytic circuit models is simulated annealing. Practical examples show that OPTIMAN quickly designs analog circuits, closely meeting the specifications, and that it is a flexible and reliable design and exploration tool     

Design Considerations for High Performance RF Cores Based on Process Variation Study

RF circuits play a vital role in high data rate communication systems. Although at the design stage several considerations are made to ensure that the designed circuit functions as per desired specifications, the effect of process variations on the circuit’s performance is less understood. The parametric variations arising from the various stages of fabrication play a significant role in determining the device characteristics. In this paper, in order to analyze the effect of process variations, we consider a bottom–up approach beginning at the component level for active and passive elements and then move to the circuit level in an RF circuit consisting of both analog and digital components. We take Low Noise Amplifier (LNA) and a Phase Frequency Detector (PFD) which is one of the important building blocks of a Phase Locked Loop (PLL) as case studies for circuit level analysis. In the case of LNA, the performance is analyzed in terms of the S-parameters, gain and Noise Factor on different topologies and for a PFD, an analytical model is developed and the analysis is carried out using the Monte Carlo method to verify the robustness of the circuit elements towards phase noise. Our hierarchical multi-phase analysis technique is shown to provide valuable insights into designing robust RF circuits.