Digital Signal Processing with Interleaved ADC Systems

This paper addresses a problem associated with interleaved ADC systems from the digital signal processing algorithm design perspective. The output streams of an interleaved ADC system are inherently in parallel format. It would be nice if DSP algorithms can be designed to take advantage of the inherently parallel signal streams in the interleaved ADC system without the need of a high speed parallel-to-serial multiplexer. Frequency response of a parallel filter bank is derived. It is found that the overall frequency response is the average of each individual interpolated channel filter plus the aliasing components. The aliasing components come from the deviation of each individual channel from the average response.Results are applied to characterize the gain mismatch of ADC arrays. Sinusoidal response is also investigated. The results can be used to characterize the frequency response mismatch of ADC arrays.Yih-Chyun Jenq received the B.S.E. degree from National Taiwan University, Taipei, Taiwan in 1971, and the M.S.E., M.A., and Ph.D. degrees in Electrical Engineering from Princeton University, Princeton, NJ in 1974, 1975, and 1976, respectively. From 1976 to 1980, he was Assistant Professor of Electrical Engineering at the State University of New York at Stony Brook, Stony Brook, NY. From 1980 to 1984, he was a Member of Technical Staff at AT&T Bell Laboratories, Homdel, NJ. From 1984 to 1990, he was a Research Manager and Principal Engineer at Tektronix Laboratories, Beaverton, OR. In September 1990, he joined the Faculty of the Department of Electrical and Computer Engineering at Portland State University, Portland, OR where he is currently a Full Professor. From 1987 to 1989, Dr. Jenq served as Associate Editor of the IEEE Transactions on Circuits and Systems in charge of Digital Signal Processing. He was the recipient of the 1988 Andrew R. Chi Prize Paper Award of the IEEE Instrumentation and Measurement Society. He holds ten (10) U.S. patents. Dr. Jenq is a fellow of the IEEE.     

New op-amp-RC to G m -C transformation method

A new transformation method is proposed and used to transform op-amp-RC circuits to G _m -C ones with only grounded capacitors. The proposed method enables the generation of high-performance G _m -C filters that benefit from the advantages of good and well-known op-amp-RC structures and at the same time feature electronic tunability, high frequency capability and monolithic integration ability. An attractive feature of the proposed method is that it results in G _m -C structures with only grounded capacitors in spite of the presence of floating capacitors in the original op-amp-RC circuits. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA, U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr. Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr. Soliman gave a lecture at Nanyang Technological University, Singapore. Dr. Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr. Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr. Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr. Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004–Now.     

Analysis and VLSI Realization of a Blind Beamforming Algorithm

We present the fixed-point analysis and VLSI realization of a maximum-power blind beamforming algorithm. This algorithm consists of the computation of a correlation matrix and its dominant eigenvector, and we propose that the latter be accomplished by the power method. After analyzing the numerical stability of the power method, we derive a division-free form of the algorithm. Based on a block-Toeplitz assumption, we design an FIR filter based system to realize both the correlation computation and the power method. Our ring processor, which is optimized to implement digital filters, is used as the core of the architecture. A special technique for dynamically switching filter inputs is shown to double the system throughput. VLSI design is discussed in detail and chip fabrication results are presented.Fan Xu received the B.S. and M.S. degrees in electronics engineering from Tsinghua University, Beijing, China, in 1993 and 1996, respectively, and the Ph.D. degree in electrical engineering from the University of California, Los Angeles, in 2001. His Ph.D. research focused on algorithm design and analysis for digital signal processors and eigenvector estimation architectures.In 1997, he held an internship at Bell Labs, Lucent Technologies, Holmdel, NJ, where he worked on equalization algorithms for cellular systems. He joined Broadcom Co., Irvine, CA, in 2001. His research interests include VLSI signal processing, customized digital signal processor, efficient hardware architectures for adaptive signal processing and high-performance VLSI design.Guichang Zhong received the B.S. degree from Xi an Jiaotong University, China, in 1996 and the M.S. degree from the Institute of Microelectronics of Chinese Academy of Sciences, Beijing, China, in 2000, both in electrical engineering. He is currently working toward the Ph.D. degree in integrated circuits and systems at the University of California, Los Angeles.His present research interests are in high-performance VLSI digital signal processors design, with an emphasis on reconfigurable and energy-efficient architecture.Alan N. Willson, Jr. received the B.E.E. degree from the Georgia Institute of Technology, Atlanta, in 1961, and the M.S. and Ph.D. degrees from Syracuse University, Syracuse, NY, in 1965 and 1967 respectively.From 1961 to 1964 he was with IBM, Poughkeepsie, NY. He was an Instructor in electrical engineering at Syracuse University from 1965 to 1967. From 1967 to 1973 he was a Member of the Technical Staff at Bell Laboratories, Murray Hill, NJ. Since 1973, he has been on the faculty of the University of California, Los Angeles (UCLA), where he is Professor of Engineering and Applied Science in the Electrical Engineering Department. In addition, he served the UCLA School of Engineering and Applied Science as Assistant Dean for Graduate Studies from 1977 through 1981 and as Associate Dean of Engineering from 1987 through 2001. He has been engaged in research concerning computer-aided circuit analysis and design, the stability of distributed circuits, properties of nonlinear networks, theory of active circuits, digital signal processing, analog circuit fault diagnosis, and integrated circuits for signal processing. He is editor of Nonlinear Networks: Theory and Analysis (New York: IEEE Press, 1974). In 1991 he founded Pentomics, Inc.Dr. Willson is a member of Eta Kappa Nu, Sigma Xi, Tau Beta Pi, the Society for Industrial and Applied Mathematics, and the American Society for Engineering Education. From 1977 to 1979, he served as Editor of the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. In 1980, he was General Chairman of the 14th Asilomar Conference on Circuits, Systems, and Computers. During 1984, he served as President of the IEEE Circuits and Systems Society. He was the recipient of the 1978 and 1994 Guillemin-Cauer Awards of the IEEE Circuits and Systems Society, the 1982 GeorgeWestinghouse Award of the American Society for Engineering Education, the 1982 Distinguished Faculty Award of the UCLA Engineering Alumni Association, the 1984 Myril B. Reed Best Paper Award of the Midwest Symposium on Circuits and Systems, the 1985 and 1994 W.R.G. Baker Awards of the IEEE, the 2000 Technical Achievement Award and the 2003 Mac Van Valkenburg Award of the IEEE Circuits and Systems Society.     

An Integrated Power Recovery Module Dedicated to Implantable Electronic Devices

This paper concerns the design and implementation of an inductively coupled RF telemetry for both power and data transferring to implantable microelectronic devices. The major shortcomings of available inductive powering designs are their low power-transfer efficiency and large size of the implantable unit. Therefore, there is a need to fully integrate interfacing module of the implantable unit. The presented power recovery module is dedicated to the biotelemetry application of cortical/nerve stimulation. The proposed strategy allows providing dual regulated output voltages 3.3 V/1.8 V to the electrodes driver and other implantable circuitry, respectively. Its low dropout voltage makes high power efficiency attainable. Fabricated integrated prototype in a CMOS 0.18 m technology has demonstrated its feasibility, providing a load current driving ability of 5 mA for each one of the two supply voltages.Yamu Hu received the B.S. degree in electrical engineering from Huazhong University of Science & Technology (HUST), Wuhan, P. R. China, in 1993, and the M.S. degree in electronics engineering from Ecole Polytechnique of Montreal, Canada, in 2000. He is currently working toward the Ph.D degree in electronics engineering at the same university. His research interest includes low-noise, low-power Analog/Mixed-Signal ICs for biomedical applications, RF front-end for wireless communications.Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics.His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the ReSMiQ (Microelectronics Strategic Alliance of Quebec) research center. He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter and the IEEE-Northeastern workshop on Circuits and Systems (NewCAS). Also, he is cofounder of the International Functional Electrical Stimulation Society, and founder of PolySTIM neurotechnology laboratory at the Ecole Polytechnique de Montreal.He published more than 250 papers in peer reviewed journals and conference proceedings and was awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society. He received the Barbara Turnbull 2003 award for spinal cord research. He is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE.Mourad El-Gamal received the B.Sc. degree with Honours from Ain-Shams University, Cairo, Egypt, in 1987, the M.Sc. degree from Vanderbilt University, Nashville, TN, in 1993, and the Ph.D. degree from McGill University, Montré al, Canada, in 1998, all in electrical engineering.He is currently an Associate Professor and William Dawson Scholar at McGill University. His research interests include integrated circuits and MEMS for communications applications, on which he has published many papers, and most recently contributed to a chapter on low voltage 5-GHz RFIC front-ends, published by the IEE in 2003. He has received several teaching awards and recognitions, and holds one patent. He was on leave of absence from McGill in 2002 to assume the role of Director of Engineering, then Vice President, of the Wireless Business Unit of MEMSCAP, headquartered in France—a 165 employee, publicly trading company specializing in MEMS. He oversaw all the business and technical aspects in different sites around the world related to RF-MEMS devices, RFICs, and millimeter-wave passive circuits. Earlier, he worked for the French telecommunications company ALCATEL and was a Member of the Technical Staff at IBM. He regularly serves as a consultant for leading microelectronics companies in North America and in Europe.Dr. El-Gamal is a member of the Analog Signal Processing Technical Committee of the IEEE Circuits and Systems (CAS) Society, and is a member of the Technical Committee of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM). He was a Guest Editor for the October 2004 issue of the Journal of Solid-State Circuits. He is the co-recipient of several research awards, the most recent being the 2003 Myril B. Reed Best Paper Award of the IEEE International Midwest Symposium on Circuits and Systems for work on frequency synthesizer covering the lower and upper bands of 5 GHz WLANs.     

An On-Chip Spectrum Analyzer for Analog Built-In Testing

This paper presents an analog built-in testing (BIT) architecture and its implementation. It enables the frequency response and harmonic distortion characterizations of an integrated device-under-test (DUT) through a digital off-chip interface. External analog instrumentation is avoided, reducing test time and cost. The proposed on-chip testing scheme uses a digital frequency synthesizer and a simple signal generator synchronized with a switched capacitor bandpass filter. A general methodology for the use of this structure in the functional verification of a DUT is also provided. The circuit-level design and experimental results of an integrated prototype in standard CMOS 0.5 m technology are presented to demonstrate the feasibility of the proposed BIT technique.Marcia G. Mendez-Rivera was born in Irapuato, Mexico in 1972. She received the Communications and Electronics Engineering Degree from the Universidad de Guanajuato, Guanajuato, Mexico. in 1996, the M.Sc. degree from the Instituto Nacional de Astrofisica, Optica y Electronica (INAOE), Puebla, Mexico in 1998 and the M.Sc. from Texas A&M University, College Station in 2002. Her research interest is in the design and fabrication of analog and mixed-signal circuits.Alberto Valdes-Garcia born in 1978, grew up in San Mateo Atenco, Mexico. He received the B.S. in Electronic Systems Engineering degree from the Monterrey Institute of Technology (ITESM), Campus Toluca, Mexico in 1999 (with honors as the best score from all majors). Since the fall of 2000 he has been working towards the Ph.D. degree at Analog and Mixed-Signal Center (AMSC), Texas A&M University. During the spring and summer of 2000 he was a Design Engineer with Motorola Broadband Communications Sector. In the summer of 2002 he was with the Read Channel Design Group at Agere Systems where he investigated wide tuning range GHz LC VCOs for mass storage applications. During the summer of 2004 he was with the Mixed-Signal Communications IC Design Group at the IBM T. J. Watson Research Center, where worked on design and analysis of SiGe power amplifiers for millimeter wave radios. Since the fall of 2001 he has been a Semiconductor Research Corporation (SRC) research assistant at the AMSC working on the development of analog built-in testing techniques. Since the fall of 2000, Alberto has been the recipient of a scholarship from the Mexican National Council for Science and Technology (CONACYT). He represented Mexico in the 1994 Odyssey of the Mind World Creativity Contest and in the 1997 International Exposition for Young Scientists. His present research interests include built-in testing implementations for analog and RF circuits, system level design for wireless receivers and RF circuit design for UltraWideBand (UWB) communications.Jose Silva-Martinez was born in Tecamachalco, Puebla, México. He received the B.S. degree in electronics from the Universidad Autónoma de Puebla, México, in 1979, the M.Sc. degree from the Instituto Nacional de Astrofísica Optica y Electrónica (INAOE), Puebla, México, in 1981, and the Ph.D. degree from the Katholieke Univesiteit Leuven, Leuven Belgium in 1992. From 1981 to 1983, he was with the Electrical Engineering Department, INAOE, where he was involved with switched-capacitor circuit design. In 1983, he joined the Department of Electrical Engineering, Universidad Autonoma de Puebla, where he remained until 1993; He was a co-founder of the graduate program on Opto-Electronics in 1992. From 1985 to 1986, he was a Visiting Scholar in the Electrical Engineering Department, Texas A&M University. In 1993, he re-joined the Electronics Department, INAOE, and from May 1995 to December 1998, was the Head of the Electronics Department; He was a co-founder of the Ph.D. program on Electronics in 1993. He is currently with the Department of Electrical Engineering (Analog and Mixed Signal Center) Texas A&M University, at College Station, where He holds the position of Associate Professor. His current field of research is in the design and fabrication of integrated circuits for communication and biomedical application. Dr. Silva-Martinez has served as IEEE CASS Vice President Region-9 (1997–1998), and as Associate Editor for IEEE Transactions on Circuits and Systems part-II from 1997–1998 and May 2002–December 2003. Since January 2004 is serving as Associate Editor of IEEE TCAS Part-I. He was the main organizer of the 1998 and 1999 International IEEE-CAS Tour in region 9, and Chairman of the International Workshop on Mixed-Mode IC Design and Applications (1997–1999). He is the inaugural holder of the TI Professorship-I in Analog Engineering, Texas A&M University. He was a co-recipient of the 1990 European Solid-State Circuits Conference Best Paper Award.Edgar Sánchez-Sinencio was born in Mexico City, Mexico. He received the degree in communications and electronic engineering (Professional degree) from the National Polytechnic Institute of Mexico, Mexico City, the M.S.E.E. degree from Stanford University, CA, and the Ph.D. degree from the University of Illinois at Urbana-Champaign, in 1966, 1970, and 1973, respectively. In 1974 he held an industrial Post-Doctoral position with the Central Research Laboratories, Nippon Electric Company, Ltd., Kawasaki, Japan. From 1976 to 1983 he was the Head of the Department of Electronics at the Instituto Nacional de Astrofísica, Optica y Electrónica (INAOE), Puebla, Mexico. He was a Visiting Professor in the Department of Electrical Engineering at Texas A&M University, College Station, during the academic years of 1979–1980 and 1983-1984. He is currently the TI J Kilby Chair Professor and Director of the Analog and Mixed-Signal Center at Texas A&M University. He was the General Chairman of the 1983 26th Midwest Symposium on Circuits and Systems. He was an Associate Editor for IEEE Trans. on Circuits and Systems, (1985–1987), and an Associate Editor for the IEEE Trans. on Neural Networks. He is the former Editor-in-Chief of the Transactions on Circuits and Systems II. He is co-author of the book Switched Capacitor Circuits (Van Nostrand-Reinhold 1984), and co-editor of the book Low Voltage/Low-Power Integrated Circuits and Systems (IEEE Press 1999). In November 1995 he was awarded an Honoris Causa Doctorate by the National Institute for Astrophysics, Optics and Electronics, Mexico. The first honorary degree awarded for Microelectronic Circuit Design contributions. He is co-recipient of the 1995 Guillemin-Cauer for his work on Cellular Networks. He is a former IEEE CAS Vice President-Publications. He was also the co-recipient of the 1997 Darlington Award for his work on high-frequency filters He received the Circuits and Systems Society Golden Jubilee Medal in 1999. He was the IEEE Circuits and Systems Society, Representative to the Solid-State Circuits Society (2000–2002). He is presently a member of the IEEE Solid-State Circuits Fellow Award Committee. His present interests are in the area of RF-Communication circuits and analog and mixed-mode circuit design. He is an IEEE Fellow Member since 1992.     

New 1.5-V CMOS second generation current conveyor based on wide range transconductor

This paper presents a novel CMOS low-voltage and low-power positive second-generation current conveyor (CCII+). The proposed CCII+ uses two n-channel differential pairs instead of the complementary differential pairs; i.e. (n-channel and p-channel), to realize the input stage. This solution allows almost a rail-to-rail input and output operation; also it reduces the number of current mirrors needed in the input stage. The CCII+ is operating at supply voltages of ±0.75 V with a total standby current of 133 μA. The application of the proposed CCII+ to realize a MOS-C second order maximally flat low-pass filter is given. PSpice simulation results for the proposed CCII+ and its application are given. Ahmed H. Madian was born in Jeddah, Saudi Arabia in 1975. He received the B.Sc. degree with honors, and the M.Sc. degree in electronics and communications from Cairo University, Cairo, Egypt, in 1997, and 2001 respectively. He is currently a Research Assistant in the Electronics Engineering Department, Micro-Electronics Design Center, Egyptian Atomic Energy Authority, Cairo, Egypt. His research interests are in circuit theory; low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed/digital applications on filed programmable gate arrays. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the BSc degree with honors in 1994, the MSc degree in 1996, and the PhD degree in 1999, all from the Electronics and Communications Department, Cairo University, Egypt. He is currently an Associate Professor at the Electrical Engineering Department, Fayoum University, Egypt. He is currently also a visiting Associate Professor at the Electrical and Electronics Engineering Department, German University in Cairo, Egypt. In 2005, He was decorated with the Science Prize in Advanced Engineering Technology from the Academy of Scientific Research and technology. His research and teaching interests are in circuit theory, fully-integrated analog filters, high-frequency transconductance amplifiers, low-voltage analog CMOS circuit design, current-mode analog signal processing, and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964,the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997-September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985-1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987-1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo.He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In November 2005, Dr Soliman gave a lecture at Nanyang Technological University, Singapore.Dr Soliman was also invited to visit Taiwan and gave lectures at Chung Yuan Christian University and at National Central University of Taiwan. In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a Member of the Editorial Board of the IEE Proceedings Circuits, Devices and Systems. Dr Soliman is a Member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Dr Soliman served as Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters) from December 2001 to December 2003 and is Associate Editor of the Journal of Circuits, Systems and Signal Processing from January 2004-Now.     

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

The Data-Intensive Architecture (DIVA) system employs Processing-In-Memory (PIM) chips as smart-memory coprocessors. This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia applications and pointer-based and sparse-matrix computations. The DIVA project has built a prototype development system using PIM chips in place of standard DRAMs to demonstrate these concepts. We have recently ported several demonstration kernels to this platform and have exhibited a speedup of 35X on a matrix transpose operation.This paper focuses on the 32-bit scalar and 256-bit WideWord integer processing components of the first DIVA prototype PIM chip, which was fabricated in TSMC 0.18 m technology. In conjunction with other publications, this paper demonstrates that impressive gains can be achieved with very little smart logic added to memory devices. A second PIM prototype that includes WideWord floating-point capability is scheduled to tape out in August 2003.Jeffrey Draper is a Research Assistant Professor in the Department of Electrical Engineering at the University of Southern California. He holds this appointment in conjunction with a Project Leader position at the Information Sciences Institute of the University of Southern California. Dr. Drapers research group has participated in many DARPA-sponsored large-scale VLSI development efforts. He is a member of the IEEE Computer Society and has conducted research in the areas of processing-in-memory architectures, thermal management, VLSI, interconnection networks, and modeling/performance evaluation. Dr. Draper received a BSEE from Texas A&M University and an MS and PhD from the University of Texas at Austin.J. Tim Barrett is a Senior Electrical Engineer at the Information Sciences Institute of the University of Southern California. Mr. Barrett has managed, designed and implemented the hardware, low-level software and integration of many computer systems. Applications of these systems include scalable supercomputers at USC Information Sciences Institute, the long distance telephone switch at AT&T Bell Labs, building energy management at Barber-Colman Company, and laser entertainment performance instruments at Aura Technologies and Laser Images Inc. He is a member of IEEE Solid State Circuits Society and received his MSCS from the University of Illinois Chicago and BSEE from the University of Iowa.Jeff Sondeen is a Research Associate at the Information Sciences Institute of the University of Southern California, where he supports and maintains CAD technology files, libraries, and tools for implementing VLSI designs. Previously he has worked at Silicon Compilers and Hewlett-Packard in CAD tool and test chip development. He received an MSEE from the University of Michigan.Sumit Mediratta is currently pursuing a PhD in Electrical Engineering at the University of Southern California. He received a Bachelor of Engineering degree in Electronics and Telecommunication from the Shri Govind Ram Sekseria Institute of Technology and Science, India. His research interests include interconnection networks, VLSI, processing-in-memory architectures, high-speed data communication and synchronization techniques and network interfaces for high-performance architectures.Chang Woo Kang received a BS in electrical engineering from Chung-ang University, Seoul, South Korea, in 1997 and an MS in electrical engineering from the University of Southern California, Los Angeles, in 1999. He is currently pursuing a PhD in electrical engineering at the University of Southern California. His research includes VLSI system design and algorithms for low-power logic synthesis and physical design.Ihn Kim is a PhD student in the Department of Electrical Engineering at the University of Southern California. He is also a Staff Engineer at QLogic. His research interests include user-level network interface, network processor architectures, and modeling/performance evaluation of system area networks. He is a member of the IEEE Computer Society. He received an MS at KAIST (Korea Advanced Institute of Science and Technology).Gokhan Daglikoca is an Application Engineer at Cadence Design Systems, Inc, where he specializes in High-Performance ASIC and Microprocessor Design Methodologies. He is a member of IEEE. Gokhan Daglikoca received a BS from Istanbul Technical University and an MS from the University of Southern California.     

Clock Feedthrough in CMOS Analog Transmission Gate Switches

An analysis of clock feedthrough in CMOS analog transmission gate (TG) switches is presented in this paper. The mechanism for clock feedthrough and a related model of a transmission gate switch are established in the current-voltage domain. A region map is developed for the TG switch during the period when both devices are turned off. The region map is further divided into zones. From these region and zone maps, the sign and relative magnitude of the clock feedthrough noise can be efficiently estimated for different signal levels. Placing the input voltage near half of the power supply voltage is a useful technique for minimizing clock feedthrough noise. A model of clock feedthrough noise as compared with SPICE simulations exhibits less than 3% error. This research was supported in part by the Semiconductor Research Corporation under Contract No. 99-TJ-687, the DARPA/ITO under AFRL Contract F29601-00-K-0182, grants from the New York State Office of Science, Technology & Academic Research to the Center for Advanced Technology—Electronic Imaging Systems and to the Microelectronics Design Center, and by grants from Xerox Corporation, IBM Corporation, Intel Corporation, Lucent Technologies Corporation, and Eastman Kodak Company. Weize Xu received the B.S. degree from Nanjing University of Posts and Telecommunications, China in 1982, and the M.S. degrees from the University of Rhode Island in 1993, both in electrical engineering. Since 1997, he has been a senor research engineer and analog IC design specialist at Eastman Kodak Company. His research interests include high speed analog IC designs, pipelined A/D converter, low power switched capacitor circuit analysis and design, CMOS image sensor design, and analysis of noise in mixed signal ICs. He currently is a Ph.D candidate at the University of Rochester. Eby G. Friedman (S'78-M'79-SM'90-F'00) received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering. From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog IC's. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, the Director of the High Performance VLSI/IC Design and Analysis Laboratory, and the Director of the Center for Electronic Imaging Systems. He also enjoyed a sabbatical at the Technion—Israel Institute of Technology during the 2000/2001 academic year. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors and low power wireless communications. He is the author of more than 250 papers and book chapters, several patents, and the author or editor of seven books in the fields of high speed and low power CMOS design techniques, high speed interconnect, and the theory and application of synchronous clock distribution networks. Dr. Friedman is the Regional Editor of the Journal of Circuits, Systems, and Computers, a Member of the editorial boards of the Proceedings of the IEEE, Analog Integrated Circuits and Signal Processing microelectronics Journal, and Journal of VLSI Signal Processing, a Member of the Circuits and Systems (CAS) Society Board of Governors, and a Member of the technical program committee of a number of conferences. He previously was the past Editor-in-Chief of the IEEE Transactions on VLSI Systems, a Member of the editorial board of the IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Chair of the IEEE Transactions on VLSI Systems steering committee, CAS liaison to the Solid-State Circuits Society, Chair of the VLSI Systems and Applications CAS Technical Committee, Chair of the Electron Devices Chapter of the IEEE Rochester Section, Program or Technical chair of several IEEE conferences, Guest Editor of several special issues in a variety of journals, and a recipient of the Howard Hughes Masters and Doctoral Fellowships, an IBM University Research Award, an Outstanding IEEE Chapter Chairman Award, and a University of Rochester College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow.     

Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI

This paper presents a detailed scaling analysis of the power supply distribution network voltage drop in DSM technologies. The effects of chip temperature, electromigration and interconnect technology scaling (including resistivity increase of Cu interconnects due to electron surface scattering and finite barrier thickness) are taken into consideration during this analysis. It is shown that the voltage drop effect in the power/ground (P/G) distribution network increases rapidly with technology scaling, and that using well-known countermeasures such as wire-sizing and/or decoupling capacitor insertion which are typically used in the present design methodologies may be insufficient to limit the voltage fluctuations over the power grid for future technologies. It is also shown that such voltage drops on power supply lines of switching devices in a clock distribution network can introduce significant amount of skew which in turn degrades the signal integrity.This work was done when the author was with the Dept. of EESystems, University of Southern California.Amir H. Ajami received his B.S. degree in electrical engineering from the University of Tehran, Tehran, Iran in 1993. He received his M.S. and Ph.D. degrees in electrical engineering from the University of Southern California, Los Angeles, CA, in 1999 and 2002, respectively.He is currently a member of consulting staff in research and development division at MagmaDesign Automation, Inc., Santa Clara, CA. He has previously held positions at Cadence Design Systems, Inc., andMagma Design Automations, Inc., in 1999 and 2000, respectively. His research interests are in the area of technology scaling issues in high-performance VLSI designs with emphasis on full-chip thermal analysis, thermalaware timing and power optimization methodologies, and signal integrity. He has coauthored several papers on the modeling and analysis of the effects of substrate thermal gradients on performance degradation and development of thermal-aware physical-synthesis optimization algorithms.Dr. Ajami is a member of Association of Computing Machinery (ACM) and IEEE. HE serves on the technical program committee of the 2005 IEEE International Symposium on Quality Electronics Design.Kaustav Banerjee received the Ph.D. degree in electrical engineering and computer sciences from the University of California at Berkeley in 1999. He was with Stanford University, Stanford, CA, from 1999 to 2002 as a Research Associate at the Center for Integrated Systems. In July 2002, he joined the faculty of the Electrical and Computer Engineering Department at the University of California, Santa Barbara, as an Assistant Professor. From February 2002 to August 2002 he was a Visiting Professor at the Circuit Research Labs of Intel in Hillsboro, Oregon. In the past, he has also held summer/visiting positions at Texas Instruments Inc., Dallas, Texas, Fujitsu Labs and the Swiss Federal Institute of Technology (EPFL). His present research interests focus on a wide variety of nanometer scale issues in high-performance VLSI and mixed-signal designs, as well as on circuits and systems issues in emerging nanoelectronics. He is also interested in some exploratory interconnect and circuit architectures including 3-D ICs. At UCSB, Dr. Banerjee mentors several doctoral and masters students. He also co-advises graduate students at Stanford University, University of Illinois at Urbana-Champaign and EPFL-Switzerland. He has co-directed two doctoral dissertations at Stanford University and the University of Southern California. Dr. Banerjee served as Technical Program Chair of the 2002 IEEE International Symposium on Quality Electronic Design (ISQED 02), and is the General Chair of ISQED 05. He also serves or has served on the technical program committees of the IEEE International Electron Devices Meeting, the IEEE International Reliability Physics Symposium, the EOS/ESD Symposium and the ACM International Symposium on Physical Design. His research has been chronicled in over 100 journals and refereed international conference papers and a book chapter. He has also co-edited a book titled Emerging Nanoelectronics: Life with and after CMOS by Kluwer in 2004. Dr. Banerjee has been recognized through the ACM SIGDA Outstanding New Faculty Award (2004) as well as a Best Paper Award at the Design Automation Conference (2001). He is listed in Whos Who in America and Whos Who in Science and Engineering.Massoud Pedram received a B.S. degree in Electrical Engineering from the California Institute of Technology in 1986 and M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley in 1989 and 1991, respectively. He then joined the department of Electrical Engineering, Systems at the University of Southern California where he is currently a professor. Dr. Pedram has served on the technical program committee of a number of conferences, including the Design automation Conference (DAC), Design and Test in Europe Conference (DATE), Asia-Pacific Design automation Conference (ASP-DAC), and International Conference on Computer Aided Design (ICCAD). He served as the Technical Co-chair and General Co-chair of the International Symposium on Low Power Electronics and Design (SLPED) in 1996 and 1997, respectively. He was the Technical Program Chair and the General Chair of the 2002 and 2003 International Symposium on Physical Design. Dr. Pedram has published four books, 60 journal papers, and more than 150 conference papers. His research has received a number of awards including two ICCD Best Paper Awards, a Distinguished Citation from ICCAD, a DAC Best Paper Award, and an IEEE Transactions on VLSI Systems Best Paper Award. He is a recipient of the NSFs Young Investigator Award (1994) and the Presidential Faculty Fellows Award (a.k.a. PECASE Award) (1996).Dr. Pedram is a Fellow of the IEEE, a member of the Board of Governors for the IEEE Circuits and systems Society, an associate editor of the IEEE Transactions on Computer Aided Design, the IEEE Transactions on Circuits and Systems, and the IEEE Circuits and Systems Society Distinguished Lecturer Program Chair. He is also an Advisory Board Member of the ACM Interest Group on Design Automation, and an associate editor of the ACM Transactions on Design Automation of Electronic Systems. His current work focuses on developing computer aided design methodologies and techniques for low power design, synthesis, and physical design. For more information, please go to URL address: .     

Reducing Encoder Bit-Rate Variation in MPEG Video

A shortcoming of current video transmission using the MPEG standard is that its encoder produces a variable bit rate (VBR). Due to this, the encoder output has to be buffered and released over the network at a constant rate. This buffering of the encoder output introduces an additional delay between the encoding and decoding phases of the video transmission. To remedy this problem, we present a strategy to distribute the load produced by the encoder as evenly as possible, i.e., try to have a constant bit rate (CBR). This is done by treating the slices in each frame separately while compressing them and then mixing the different kinds of slices that are sent over the network. The resulting load variation is much more uniform, reducing the buffering delay and making future bandwidth requirement estimates more accurate.This material is based upon work supported in part by the National Science Foundation under Award No. IRI-9526004, by the Texas Advanced Research Program under Grant No. 3652270, and by a grant from the University of Houston Institute of Space Systems Operations. Rajat Agarwal is now with Lucent Technologies. This paper is an extended version of a shorter paper presented at IEEE ICMCS 1999.Albert Mo Kim Cheng received the B.A. with Highest Honors in Computer Science at age 19, graduating Phi Beta Kappa, the M.S. in Computer Science with a minor in Electrical Engineering at age 21, and the Ph.D. in Computer Science at age 25, all from The University of Texas at Austin, where he held a GTE Foundation Doctoral Fellowship. Dr. Cheng is currently a tenured Associate Professor in the Department of Computer Science at the University of Houston, where he is the founding Director of the Real-Time Systems Laboratory. He has served as a technical consultant for several organizations, including IBM, and was also a visiting faculty in the Departments of Computer Science at Rice University (2000) and at the City University of Hong Kong (1995).He is the author/co-author of over seventy refereed publications in IEEE Transactions on Software Engineering, IEEE Transactions on Knowledge and Data Engineering, Real-Time Systems Symposium, Real-Time and Embedded Technology and Applications Symposium, and other leading conferences. One of his recent work presents a timing analysis of the NASA X-38 Space Station Crew Return Vehicle Avionics, which contains a fault-tolerant distributed system.Dr. Cheng has received numerous awards, including the National Science Foundation Research Initiation Award (now known as the NSF CAREER award). He has been invited to present seminars and tutorials at over 30 conferences, and has given invited seminars/keynotes at over 20 universities and organizations, most recently at ICEIS, Ecole Superieure de l Ouest (ESEO), Angers, France, April 2003. His next invited keynote speech will be at the 1st Intl. Conf. on Informatics in Control, Automation and Robotics (ICINCO), Setubal, Portugal, August 2004.He is an Associate Editor of the IEEE Transactions on Software Engineering (1998-2003), a Guest Co-Editor of two IEEE TSE Special Issues on Software and Performance (Nov. and Dec. 2000), an Associate Editor of the International Journal of Computer and Information Science, the work-in-progress program chair of the 2001 IEEE-CS Real-Time Technology and Applications Symposium, the work-in-progress session chair of the 2003 IEEE-CS Real-Time Systems Symposium, and the invited special panel chair for the software engineering for multimedia session at the 1999 IEEE-CS International Conference on Multimedia Computing Systems (ICMCS). Currently, he is a member of the program committees of RTSS, RTAS, ICEIS, ICECCS, RTAS, LCN, COMPSAC, ICCCN, AIA, DBA, PDCN, SE, and ICINCO. Dr. Cheng is an Honorary Member of the Institute for Systems and Technologies of Information, Control and Communication (INSTICC). He is a Senior Member of the IEEE.Dr. Cheng is the author of several book chapters on E-commerce/Enterprise Information Systems, and an article entitled Embedded OS, in the upcoming Encyclopedia of Computer Science and Engineering (John Wiley & Sons). He is the author of the new senior/graduate-level textbook entitled Real-Time Systems: Scheduling, Analysis, and Verification (John Wiley & Sons). cheng@cs.uh.eduRajat Agarwal received the M.S. in Computer Science from the University of Houston. He is currently a Member of the Technical Staff at Lucent Technologies. His research interest is in real-time multimedia systems.     

A High Dynamic Range Programmable CMOS Front-End Filter with a Tuning Range from 1850 to 2400 MHz

This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, –25 dBm in-band 1-dB input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply.Kâre T. Christensen received the M.Sc. and Ph.D. degrees in electrical engineering from the Technical University of Denmark in 1997 and 2002, respectively.In 1995-96 he was a visiting scholar working on switched current memory cells at the Spanish National Microelectronics Centre in Seville. In 1997 he worked on an asynchronous embedded MIPS16/MIPS32 microprocessor core for LSI Logic. In 1999-2000 he was a visiting researcher at Stanford University. During his stay he worked on fully integrated RF front-end filters in CMOS.From 1998 to 2002 he worked for Nokia Mobile Phones conducting research in the design of RF ICs for multi-band GSM terminals. He currently works for the Danish hearing aid manufacturer Oticon A/S designing micro-power RF circuits and systems in CMOS.He has lectured on several occasions at the Technical University of Denmark and other universities. He has authored or co-authored nine papers and holds three U.S. patents.Thomas H. Lee received the S.B., S.M. and Sc.D. degrees in electrical engineering, all from the Massachusetts Institute of Technology in 1983, 1985, and 1990, respectively.He joined Analog Devices in 1990 where he was primarily engaged in the design of high-speed clock recovery devices. In 1992, he joined Rambus Inc. in Mountain View, CA where he developed high-speed analog circuitry for 500 megabyte/s CMOS DRAMs.He has also contributed to the development of PLLs in the StrongARM, Alpha and AMD K6/K7/K8 microprocessors. Since 1994, he has been a Professor of Electrical Engineering at Stanford University where his research focus has been on gigahertz-speed wireline and wireless integrated circuits built in conventional silicon technologies, particularly CMOS.He has twice received the Best Paper award at the International Solid-State Circuits Conference, co-authored a Best Student Paper at ISSCC, was awarded the Best Paper prize at CICC, and is a Packard Foundation Fellowship recipient.He is an IEEE Distinguished Lecturer of both the Solid-State Circuits and Microwave Societies. He holds 35 U.S. patents and authored The Design of CMOS Radio-Frequency Integrated Circuits (now in its second edition), and Planar Microwave Engineering, both with Cambridge University Press. He is a co-author of four additional books on RF circuit design, and also cofounded Matrix Semiconductor.Erik Bruun received the M.Sc. and Ph.D. degrees in electrical engineering in 1974 and 1980, respectively, from the Technical University of Denmark. In 1980 he received the B.Com. degree from the Copenhagen Business School. In 2000 he also received the dr. techn. degree from the Technical University of Denmark.From January 1974 to September 1974 he was with Christian Rovsing A/S, working on the development of space electronics and test equipment for space electronics. From 1974 to 1980 he was with the Laboratory for Semiconductor Technology at the Technical University of Denmark, working in the fields of MNOS memory devices, IL devices, bipolar analog circuits, and custom integrated circuits. From 1980 to 1984 he was with Christian Rovsing A/S. From 1984 to 1989 he was the managing director of Danmos Microsystems ApS. Since 1989 he has been a Professor of analog electronics at the Technical University of Denmark where he has served as head of the Sector of Information Technology, Electronics, and Mathematics from 1995 to 2001. Since 2001 he has been head of ÿrstedïDTU.His current research interests are in the areas of RF integrated circuit design and integrated circuits for mobile phones.     

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.Chao-Tsung Huang was born in Kaohsiung, Taiwan, R.O.C., in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 2001. He currently is working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for signal processing systems.Po-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems.Liang-Gee Chen received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications, During 2001-2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

A time-to-first spike CMOS image sensor with coarse temporal sampling

Conventional voltage-based CMOS image sensors inherently have a dynamic range of about 60 dB. To extend the dynamic range, a two-degree of freedom time-based CMOS image sensor is proposed. Instead of reading analog voltages off chip, a time representation is used to record when the photodetector voltage passes a timing-varying threshold. The time measurements are combined with the reference voltage waveform to reconstruct the image. Experimental results on a prototype 32 × 32 pixel array CMOS image sensor verify that the two-degree of freedom sampling technique is feasible for ultra-wide dynamic range imaging. A measured 115 dB dynamic range at 30 fps is obtained. Qiang Luo received the B.S. (with honor) and M.S. degrees in electrical engineering from Fudan University, Shanghai, China, in 1995 and 1998, respectively, and the Ph.D. degree in electrical engineering from University of Florida, Gainesville, FL, in 2002. In 2001, he was with Texas Instruments Inc., Dallas, TX, where he was an intern engineer working on ultra-wide dynamic range CMOS image sensors. From 2002 to 2004, he was with National Semiconductor Corporation, Santa Clara, CA, where he was a staff circuit design engineer and worked on the design of high performance CMOS image sensors. He is currently with the Marvell Semiconductor Inc, Sunnyvale, CA, where he is working on the development of advanced DVD servo IC. His research interests include high-speed mixed-signal IC design, CMOS image sensors, DVD servo IC and device physics. Dr. John G. Harris received his BS and MS degrees in Electrical Engineering from MIT in 1983 and 1986. He earned his PhD from Caltech in the interdisciplinary Computation and Neural Systems program in 1991. After a two-year postdoc at the MIT AI lab, Dr Harris joined the Electrical and Computer Engineering Department at the University of Florida (UF). He is currently an associate professor and leads the Hybrid Signal Processing Group in researching biologically-inspired circuits, architectures and algorithms for signal processing. Dr. Harris has published over 100 research papers and patents in this area. He co-directs the Computational NeuroEngineering Lab and has a joint appointment in the Biomedical Engineering Department at UF. Zhiliang J. Chen received Ph.D. degree in electrical engineering from University of Florida in 1994. From 1994 to 2004, he was with Texas Instruments where he worked as Senior Member of Technical Staff and Design Branch Manager. In 2002 he was expatriated to COMMIT, a Texas Instruments JV company in China, as director of RF & Analog Base Band department. In 2004, he left Texas Instrument and found On-Bright (Shanghai) Corporation where he serves as president of the company. Dr. Chen currently held 22 US patents and has published morn than 10 journal papers. He was a recipient of the Best Paper Award from the 1997 ESD/EOS symposium.     

Reciprocal and Reciprocal Square Root Units with Operand Modification and Multiplication

Reciprocals and reciprocal square roots are used in several digital signal processing, multimedia, and scientific computing applications. This paper presents high-speed methods for computing reciprocals and reciprocal square roots. These methods use a table lookup, operand modification, and multiplication to obtain an initial approximation. This is followed by a modified Newton-Raphson iteration, which improves the accuracy of the initial approximation. The initial approximation and Newton-Raphson iteration employ specialized hardware to reduce the delay, area, and power dissipation. The application of these methods is illustrated through the design of reciprocal and reciprocal square root units for operands in the IEEE single precision format. These designs are pipelined to produce a new result every clock cycle. Kent Wires received a B.S. degree in Electrical Engineering from Cornell University, Ithaca, NY in 1996, and M.S. and Ph.D. degrees in Electrical Engineering from Lehigh University, Bethlehem, PA, in 1997 and 2001, respectively. From 1998 to 2001, he was a Member of Technical Staff at Lucent Technologies, Allentown, PA, where he was a member of the Advanced DSP Architectures and Compilers Group. He is currently a Senior Member of Technical Staff at Agere Systems, Allentown, PA, where he is a systems architect focusing on media streaming and network protocol techniques. His current research interests include computer arithmetic, media streaming techniques, efficient processor modeling techniques, and network processor architectures and protocols. Michael Schulte received a B.S. degree in Electrical Engineering fromthe University of Wisconsin-Madison in 1991, and M.S. and Ph.D. degrees in Electrical Engineering from the University of Texas at Austin in 1992 and 1996, respectively. From 1996 to 2002, he was an assistant and associate professor at Lehigh University, where he directed the Computer Architecture and Arithmetic Research Laboratory. In 1997, he received a NSF CAREER Award to research hardware support for accurate and reliable numerical computations. Prof. Schulte has consulted for or had joint research projects with Sandbridge Technologies, IBM, Sun Microsystems, ARM, Lucent Technologies, Agere Systems, MIPS Technologies, and Sandia National Laboratories. He is currently an assistant professor at the University of Wisconsin-Madison, where he leads the Madison Embedded Systems and Architectures Group. His research interests include high-performance embedded processors, computer architecture, domain-specific systems, computer arithmetic, and wireless security. He is a senior member of the IEEE and the IEEE Computer Society, and an associate editor for the IEEE Transactions on Computers and the Journal of VLSI Signal Processing.     

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension. The latter consists of two multiplexers and can solve the shape-adaptive boundary extension locally without any additional register. Two case studies are presented, including the JPEG 2000 default (9, 7) filter and MPEG-4 default (9, 3) filter. According to comparison results with previous architectures, the efficiency of the proposed architectures is proven.Chao-Tsung Huang was born in Kaohsiung, Taiwan in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2001. He is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D Discrete Wavelet Transform. cthuang@video.ee.ntu.edu.twPo-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems. pctseng@video.ee.ntu.edu.twLiang-Gee Chen (S84–M86–SM94–F01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. lgchen@video.ee.ntu.edu.tw     

Interactive Content-aware Video Streaming System with Fine Granularity Scalability

Video streaming with varying transmission bandwidth is becoming increasingly important. In this paper, an interactive video streaming system is proposed. Fine Granularity Scalability (FGS) is applied to be the streaming video format. The computational complexity of FGS coding is analyzed to explore an efficient FGS implementation. A new transmission model is proposed for the realization of a content-aware video streaming. At encoder side, the current MPEG-4 FGS coding flow is reordered such that the picture-level maximum can be acquired in advance and bit-plane data can be dynamically adapted. With these proposed hardware-oriented optimization approaches, a hardwired FGS block-level processing core is proposed to achieve a cost-effective solution to FGS implementation. The streaming server can adaptively decide quality-enhanced region by selective enhancement according to both object information from encoding side and user-defined region from receiver side. From the simulation results, it’s demonstrated that the proposed approach can provide better quality in users’ interest regions with no bit-rate or complexity overhead. Yung-Chi Chang was born in Kaohsiung, Taiwan, R.O.C., in 1975. He received the B.S., M.S., and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C., in 1998, 2000, and 2005, respectively. He serves as senior engineer in SoC Solutions Dept., Vivotek Inc. now. His research interests include video coding algorithms and VLSI architectures for image/video processing. Chih-Wei Hsu was born in Taipei, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia coding standard and digital consumer devices. His research interests include video coding, video processing and VLSI design. Wei-Min Chao was born in Taoyuan, Taiwan, R.O.C., in 1977. He received the B.S. and M.S. degrees from the Department of Electronics Engineering, National Taiwan University in 2000 and 2002 separately. His research interests include video coding algorithms and VLSI architecture for image and video processing. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 to 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. In 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was a Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. In 1997, he was a visiting scholar of the Department of Electrical Engineering, University of Washington, Seattle. During 2001 to 2004, he was the first director of the Graduate Institute of Electronics Engineering (GIEE) in National Taiwan University (NTU). Currently, he is a Professor of the Department of Electrical Engineering and GIEE in NTU, Taipei, Taiwan. He is also the director of the Electronics and Optoelectronics Research Laboratories in Industrial Technology Research Institute, Hsinchu, Taiwan. His current research interests are DSP architecture design, video processor design, and video coding systems. Dr. Chen has served as an Associate Editor of IEEE Transactions on Circuits and Systems for Video Technology since 1996, as Associate Editor of IEEE Transactions on VLSI Systems since 1999, and as Associate Editor of IEEE Transactions on Circuits and Systems II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the Proceedings of the IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi.     

Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing

The concept of model-based test was developed in order to reduce the production test effort for data converters (Cherubal and Chatterjee (IEEE Trans Circuits Syst part I 50(3):317–327, 2003); Stenbakken and Souders (1985) Modelling and test point selection for data converter testing. In: ITC, Int Test Conf, pp 813–817; Wegener and Kennedy (IEEE Trans Circuits Syst I 51(1):213–217, 2004); Wrixon and Kennedy (IEEE Trans Instrum Meas IM-48(5):978–985, 1999)). In applying this concept, a vector of model parameters is determined for each device under test (DUT). Typically, this model parameter vector is merely used to calculate the DUT performance characteristic which is then subject to specification-oriented testing. However, each element of the model parameter vector represents an independent error source which contributes to performance degradations; thus, the model parameter vector can be viewed as a signature of the error sources. In this work, analyzing the error source signature is used to devise a model-based methodology for hard-fault detection and diagnosis. We investigate conditions under which hard-faults are detectable/diagnosable in spite of masking effects due to manufacturing process variations. In particular, we show that taking the model parameter vector as the fault signature is optimal as it minimizes the masking effects and thus maximizes detectability/diagnosibility.

A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications

A methodological framework for performance estimation of multimedia signal processing applications on different implementation platforms is presented. The methodology derives a complexity profile which is characteristic for an application, but completely platform-independent. By correlating the complexity profile with platform-specific data, performance estimation results for different platforms are obtained. The methodology is based on a reference software implementation of the targeted application, but is, in constrast to instruction-level profiling-based approaches, fully independent of its optimization degree. The proposed methodology is demonstrated by example of an MPEG-4 Advanced Simple Profile (ASP) video decoder. Performance estimation results are presented for two different platforms, a specialized VLIW media processor and an embedded general-purpose RISC processor, showing a high accuracy of he methodology. The approach can be employed to assist in design decisions in the specification phase of new architectures, in the selection process of a suitable target platform for a multimedia application, or in the optimization stage of a software implementation on a specific platform.Hans-Joachim Stolberg received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.From 1995 to 1996, he worked at the NEC Information Technology Research Laboratories, Kawasaki, Japan, on efficient implementation of video compression algorithms. Since 1996, he has been with the Institute of Microelectronic Systems at the University of Hannover as a Research Assistant. During summer 2001, he was a Monbukagakusho Research Fellow at the Tokyo Institute of Technology, Japan. His current research interests include VLSI architectures for video signal processing, performance estimation of multimedia schemes, and profile-guided memory organization approaches for signal processing and multimedia applications.Mladen Bereković received the Dipl.-Ing. degree in electrical engineering from the University of Hannover, Germany, in 1995.Since then he has been a Research Assistant with the Institute of Microelectronic Systems of the University of Hannover. His current research interests include VLSI architectures for video signal processing, MPEG-4, System-on-Chip (SOC) designs, and simultaneously multi-threaded (SMT) processor architectures.Peter Pirsch received the Ing. grad. degree from the engineering college in Hannover, Germany, in 1966, and the Dipl.-Ing. and Dr.-Ing. degrees from the University of Hannover, in 1973 and 1979, respectively, all in electrical engineering.From 1966 to 1973 he was employed by Telefunken, Hannover, working in the Television Department. He became a Research Assistant at the Department of Electrical Engineering, University of Hannover, in 1973, a Senior Engineer in 1978. During 1979 to 1981 he was on leave, working in the Visual Communications Research Department, Bell Laboratories, Holmdel, NJ. During 1983 to 1986 he was Department Head for Digital Signal Processing at the SEL Research Center, Stuttgart, Germany. Since 1987 he is Professor in the Department of Electrical and Computer Engineering at the University of Hannover. He served as Vice President Research of the University of Hannover from 1998 to 2002.His present research includes architectures and VLSI implementations for image processing applications, rapid prototyping and design automation for DSP applications. He is the author or coauthor of more than 200 technical papers. He has edited a book on VLSI Implementations for Image Communications (Elsevier 1993) and is author of the book Architectures for Digital Signal Processing (John Wiley 1998).Dr. Pirsch is a member of the IEEE, the German Institute of Information Technology Engineers (ITG) and the German Association of Engineers (VDI). He was recipient of several awards: the NTG paper price award (1982), IEEE Fellow (1997), IEEE Circuits and Systems Golden Jubilee Medal (1999). He was member or chair of several technical program committees of international conferences and organizer of special sessions and preconference courses. He has held several administrative and technical positions with the IEEE Circuits and Systems Society and other professional organizations. Dr. Pirsch currently serves as Vice President Publications of the IEEE Circuits and Systems Society. Since 2000 he is chairman of the Accreditation Commission for Engineering and Informatics of the Accreditation Agency for Study Programs in Engineering, Informatics, Natural Science and Mathematics (ASIIN). Dr. Pirsch is chair of the VDI committee on Engineering Education.     

A low-cost programmable clock generator for switched-capacitor circuit applications

This paper presents two improved circuit techniques that allow the design of a low-cost programmable clock generator using a ring oscillator for low-frequency switched-capacitor applications. The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller current-starved inverter ring oscillator. For identical values of integrated components in implementation, the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional current-starved inverter ring oscillator. This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixed-signal circuits. The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit. The experimental results have verified that the programming range of 56 kHz to 1.042 MHz is achieved using discrete-step tuning on small capacitor values from 0.375 pF to 5.625 pF together with frequency division by four divider stages, whilst the jitter is less than 300 ps at ±10% variation in a 5 V supply in the entire tuning range. Wing Foon Lee was born in Singapore. He had worked as an application engineer for more than two years. He received his B.Eng., M.Eng. and Ph.D. degrees in Electrical & Electronic Engineering from Nanyang Technological University, Singapore in 1996, 1999 and 2005 respectively. His research interest is on low power analog circuit design, high precision readout circuits and signal-conditioning circuits for sensor applications. P. K. Chan was born in Hong Kong. He received the B.Sc. (Hons) degree from the University of Essex, Colchester, U.K., in 1987, the M.Sc. degree from the University of Manchester, Institute of Science and Technology (U.M.I.S.T.), Manchester, U.K., in 1988, and the PhD degree from the University of Plymouth, U.K. in 1992. From 1989 to 1992, he was a Research Assistant with the University of Plymouth, working in the area of MOS continuous-time filters. In 1993, he joined the Institute of Microelectronics (IME) as a Member Technical Staff, where he designed CMOS sensor interfaces for industrial applications. In 1996, He was a Staff Engineer with Motorola, Singapore where he developed the magnetic write channel for Motorola 1st generation hard-disk preamplifier. He joined Nanyang Technological University (NTU), Singapore in 1997, where he is currently an Associate Professor in the School of Electrical and Electronic Engineering and Program Director [analog/mixed-signal IC and applications] for the Center for Integrated Circuits and Systems (CICS). He holds four patents and is an IC Design Consultant to local and multi-national companies in Singapore. He has also conducted numerous IC design short courses to the industrial companies and design centers. His research interests include circuit theory, amplifier frequency compensation techniques, sensing interfaces for integrated sensors, biomedical circuits and systems, integrated filters and data converters.     

Overcoming Test Setup Limitations by Applying Model-Based Testing to High-Precision ADCs

Test setup limitations, such as noise and parasitics, increasingly impede repeatable and accurate linearity measurements in high-volume production testing of high-precision data converters. Model-based testing has been shown to reduce the adverse effects of noise [14].In this work, we present two enhancements of the linear model-based approach: one is a change of the modeling strategy in order to account for measurement errors induced, for example, by parasitics associated with the device contactor, and another is a Design-for-Test feature that significantly improves the models ability to reduce the effect of measurement noise on the accuracy of the test outcome.The authors acknowledge the support by Analog Devices B.V., Limerick, Ireland and Enterprise Ireland under the Strategic Research Grant ST/00/26.Carsten Wegener has been awarded the academic degree of a Diplom-Ingenieur in Electronic Circuits and Systems by the Technical University of Dresden, Germany, in 1997. During a period of two years, 1996 through 1998, he attended the lecture series for the Vordiplom in Mathematics at Humboldt-University at Berlin, Germany.In Spring 1998, he moved permanently to Ireland, where he started to work with the Test Department of Analog Devices B.V. in Limerick. In Autumn of the same year he took up his PhD-studies with Dr M.P. Kennedy in the area of model-based testing of mixed-signal integrated circuits. He has been awarded the PhD degree by the National University of Ireland in December 2003.He has contributed to numerous conferences, publishing works in areas of nonlinear oscillator dynamics and mixed-signal testing. In Ireland, he has taught MATLAB courses to design and test engineers at Analog Devices B.V., and graduate courses on Digital Design-for-Test and Mixed-signal Test and Testability at the Department of Microelectronic Engineering, University College Cork.Michael Peter Kennedy received the B.E. degree in electronics from the National University of Ireland in 1984, and the M.S. and Ph.D. degrees from the University of California at Berkeley (UC Berkeley) in 1987 and 1991, respectively, for his contributions to the study of neural networks and nonlinear dynamics.He worked as a Design Engineer with Philips Electronics, a Postdoctoral Research Engineer with the Electronics Research Laboratory, UC Berkeley, and as a Professeur Invité with the EPFL, Switzerland. He returned to University College Dublin in 1992 as a College Lecturer in the Department of Electronic and Electrical Engineering. He was appointed Professor of Microelectronic Engineering at University College Cork in 2000.He has published 200 articles in the area of nonlinear circuits and systems and has taught courses on nonlinear dynamics and chaos. His research interests are nonlinear circuits and systems for applications in communications and signal processing. Since 1995 he has been active in research into algorithms for mixed-signal testing. Since 1994, he has led international basic and applied research projects on chaotic communications valued at over USD 2M.Dr. Kennedy was elected a Fellow of the IEEE in 1998. He received the Third Millenium Medal from the IEEE in 2000, the IEEE Circuits and Systems Society Golden Jubilee Medal, and the inaugural Parsons Award for excellence in Engineering Sciences from the Royal Irish Academy in 2001.