高可靠、高效率的白光LED高压驱动芯片

根据白光LED(Light Emitting Diode)的特性及其对驱动电路的要求,提出了一种高可靠、高效率的LED高压驱动芯片,具有线性调光和数字调光两种调光功能。芯片采用简化的脉冲宽度调制(PWM,Pulse Width Modulation)峰值电流控制模式控制通过LED的电流,系统稳定性好,抗干扰能力强。振荡器中新型抖频电路模块的加入,提高了系统的电磁干扰(EMI,Electro Magnetic Interference)性能,使系统可靠性进一步增强。驱动芯片的输入电压范围为8.5 V~40V,输出的驱动电压达7.5V,可有效降低NMOS功率开关管的导通损耗。电路设计采用低静态电流、低反馈电压等低功耗设计技术,提高了系统的电能转换效率。芯片采用CSMC公司1μm 40V高压CMOS工艺模型设计,并完成流片。测试结果验证了抖频电路的作用,系统的最高转换效率达到了95.3%。     

整合型功率光敏可控硅

V03526是一款可输出1A电流来驱动电阻及电感负载的整合功率光敏可控硅,它采用16引脚DIP封装,包含GaAs红外LED,该LED可光耦合到单片光敏非过零TRIAC检测器芯片上,从而可启动整合功率TRIAC。由于消除了对外部功率TRIAC的需求,该器件可降低设计成本并节省板面空间。该功率光敏可控硅器件额定阻断电压为600V,在120V及240V的交流线路上可实现直流与交流电压的隔离,从而可提供两倍或更高的安全系数。     

中小屏幕TFT-LCD驱动芯片的输出缓冲电路

在分析中小屏幕TFT-LCD驱动芯片的负荷特性的基础上,提出了一种新型的驱动电压输出缓冲电路结构.通过负反馈动态控制输出级的工作状态,具有交替提供拉电流和灌电流的驱动能力,可有效抑制输出电压的波动.与传统的两级运算放大器电路相比,该电路结构简单,稳定性能好,降低了静态功耗并节省了芯片面积.采用0.25μm CMOS工艺设计并实现了两种不同输出电压的缓冲电路.HSPICE仿真结果表明,输出电压缓冲电路的静态电流为3μA,Offset电压小于±2mV.同时,当TFT-LCD的驱动电压在-8～ 16V之间切换时,输出电压的波动范围小于±0.4V,输出电压的恢复时间小于7μs.经对工程样片的测试知,其性能完全满足中小屏幕TFT-LCD驱动控制芯片的要求.     

一种提高硅基OLED微显示器对比度的像素电路

提出了一种应用于硅基有机发光二极管(Organic light emitting diode,OLED)微显示驱动芯片的新型像素单元电路,具有三个MOSFET和一个存储电容。相比传统的电压驱动像素单元电路,增加的一个MOSFET,可以根据输入数据的变化,自动调节其等效电阻,降低像素单元的最小输出电流。本像素电路能够在较宽的OLED公共阴极电压范围内维持很大的电流比率。该电路采用SMIC 0.35μm 2P4M混合信号工艺进行设计,目前已成功应用于一款分辨率为800×600,像素节距为15μm×15μm的硅基OLED驱动芯片,经测试验证,输出电流范围为280pA~65nA,可以同时满足OLED阵列高亮度和高对比度的要求。     

Intersil整合功率驱动芯片和MOSFET器件

Intersil公司最近将一种功率驱动芯片与两款MOSFET结合到同一封装设计 ,命名为 EnduraISL6571 Synchro FET,采用 QFN封装方式。该产品显著减少了面板空间 ,简化其设计结构 ,也降低了制造成本。该器件结合了补偿式 MOSFET驱动器、同步半桥转换器和肖特基二极管 ,采用小型热效能封装。其设计可将 DC/DC转换器的工作频率提升至 1 MHz/phase,从整体上减少印刷电路板的空间。ISL6571 CR采用 QFN封装 ,在 4,999～ 9,999数量范围的定购单价为 2美元。相关设计、评估板和电路设计也可提供。Intersil整合功率驱动芯片和MOSFET器件…     

一款集成驱动放大器的低变频损耗混频器设计

采用0.5μm GaAs工艺设计并制造了一款单片集成驱动放大器的低变频损耗混频器.电路主要包括混频部分、巴伦和驱动放大器3个模块.混频器的射频(RF)、本振(LO)频率为4～7 GHz,中频(IF)带宽为DC～2.5 GHz,芯片变频损耗小于7 dB,本振到射频隔离度大于35 dB,本振到中频隔离度大于27 dB.1 dB压缩点输入功率大于11 dBm,输入三阶交调点大于20 dBm.该混频器单片集成一款驱动放大器,解决了无源混频器要求大本振功率的问题,变频功能由串联二极管环实现,巴伦采用螺旋式结构,在实现超低变频损耗和良好隔离度的同时,保持了较小的芯片面积.整体芯片面积为1.1 mm×1.2 mm.     

中小屏幕TFT-LCD驱动芯片的输出缓冲电路

在分析中小屏幕TFT-LCD驱动芯片的负荷特性的基础上,提出了一种新型的驱动电压输出缓冲电路结构.通过负反馈动态控制输出级的工作状态,具有交替提供拉电流和灌电流的驱动能力,可有效抑制输出电压的波动.与传统的两级运算放大器电路相比,该电路结构简单,稳定性能好,降低了静态功耗并节省了芯片面积.采用0.25μm CMOS工艺设计并实现了两种不同输出电压的缓冲电路.HSPICE仿真结果表明,输出电压缓冲电路的静态电流为3μA,Offset电压小于±2mV.同时,当TFT-LCD的驱动电压在-8～+16V之间切换时,输出电压的波动范围小于±0.4V,输出电压的恢复时间小于7μs.经对工程样片的测试知,其性能完全满足中小屏幕TFT-LCD驱动控制芯片的要求.     

一种基于升压DC-DC变换器的白光LED驱动芯片

设计了一种升压型恒流LED驱动芯片,驱动电流可由外接电阻从15～300 mA任意调整,输入电压为2.8～5.5 V,输出电压最高可达38 V.设计固定开关频率为1 MHz,应用时只需很小的外接电感即可.相对于其他驱动器电路,该驱动器增加了过压保护电路,无需外接稳压二极管,降低了应用成本.采用上华0.5μm BCD工艺完成芯片的设计,传输效率高达94％.     

实现64级灰度显示的无源OLED驱动芯片的设计

设计出了一种实现64级灰度显示的单片混合信号驱动芯片,它采用脉冲宽度调制方法和两级电压预充方式,适用于驱动132×64像素的无源OLED显示屏.芯片内部主要包括数字控制器,显示数据存取器,DC-DC电压转换器,参考电流产生器,电压预充电路产生器,64个行驱动电路和132个列驱动电路.它已经用Chartered0.35μm 18V高压CMOS工艺制作完成,芯片面积约为10mm×2mm.测试结果表明芯片性能良好,在电源低压为3V,高压为12V,显示电流为100mA并处于最高级灰度显示的条件下,芯片与面板的总功耗为294mW.     

实现64级灰度显示的无源OLED驱动芯片的设计

设计出了一种实现64级灰度显示的单片混合信号驱动芯片,它采用脉冲宽度调制方法和两级电压预充方式,适用于驱动132×64像素的无源OLED显示屏.芯片内部主要包括数字控制器,显示数据存取器,DC-DC电压转换器,参考电流产生器,电压预充电路产生器,64个行驱动电路和132个列驱动电路.它已经用Chartered0.35μm 18V高压CMOS工艺制作完成,芯片面积约为10mm×2mm.测试结果表明芯片性能良好,在电源低压为3V,高压为12V,显示电流为100mA并处于最高级灰度显示的条件下,芯片与面板的总功耗为294mW.     

一种用于TFT-LCD液晶显示的片内门宽调制控制器的设计

为了防止在液晶显示面板上发生闪烁和减小栅驱动器的馈通现象,设计了一种基于升压型DC-DC和电荷泵的用于TFT-LCD液品显示的片内门宽调制控制器.该控制器能减小液品显示功耗,减少栅走线和液晶面板之间的耦合效应,其输出延时可调并输入到栅驱动器中,从而避免液晶显示设备错误的显示.采用该门宽调制器的基于电流模PWM升压型DC-DC和电荷泵的芯片已在UMC 0.6μm BCD工艺线投片,DC-DC的效率高达93%,可调电荷泵输出电压为10～30V,测试结果证明该门宽调制控制器电路工作良好,其面积为0.3mm2,静态电流小于1μA.     

基于可调电荷泵的双模式高压开关控制器

为了防止在液晶显示面板上发生闪烁和减小栅驱动器的馈通现象,设计了一种基于可调电荷泵的用于TFT-LCD液晶显示的片内双模式高压开关控制器,该控制器能减小液晶显示功耗,减少栅走线和液晶面板之间的耦合效应,其输出延时和下降斜率可调并输入到栅驱动器中,从而避免液晶显示设备错误的显示。该基于可调电荷泵的高压开关控制器的芯片已在UMC0.6μm-BCD工艺线投片,电荷泵输出可调电压范围为10～30V,测试结果证明,高压开关控制器电路工作良好,其面积为0.32mm2,静态电流小于3μA。     

有源矩阵有机电致发光像素电路的研究进展

有源驱动方式的有机发光二极管（AMOLED）较之无源驱动方式易于实现高亮度和高分辨率、功耗更小,更适合大屏幕显示。但传统的两管驱动电路会出现驱动管阈值电压在整个屏幕上分布不均匀,或长时间加偏压后驱动管的阂值电压发生漂移。本文在两管驱动电路的基础上介绍了几种最近提出的补偿电路并描述了它们的改善效果及各自存在的问题。     

High-Voltage Analog System for a Mobile NAND Flash

High-voltage analog circuits, including a novel high-voltage regulation scheme, are presented with emphasis on low supply voltage, low power consumption, low area overhead, and low noise, which are key design metrics for implementing NAND Flash memory in a mobile handset. Regulated high voltage generation at low supply voltage is achieved with optimized oscillator, high-voltage charge pump, and voltage regulator circuits. We developed a design methodology for a high-voltage charge pump to minimize silicon area, noise, and power consumption of the circuit without degrading the high-voltage output drive capability. Novel circuit techniques are proposed for low supply voltage operation. Both the oscillator and the regulator circuits achieve 1.5 V operation, while the regulator includes a ripple suppression circuit that is simple and robust. Through the paper, theoretical analysis of the proposed circuits is provided along with Spice simulations. A mobile NAND Flash device is realized with an advanced 63 nm technology to verify the operation of the proposed circuits. Extensive measurements show agreement with the results predicted by both analysis and simulation.     

Design of a 16 gray scales 320×240 pixels OLED-on-silicon driving circuit

A 320×240 pixel organic-light-emitting-diode-on-silicon (OLEDoS) driving circuit is implemented using the standard 0.5 μm CMOS process of CSMC. It gives 16 gray scales with integrated 4 bit D/A converters. A three-transistor voltage-programmed OLED pixel driver is proposed, which can realize the very small current driving required for the OLEDoS microdisplay. Both the D/A converter and the pixel driver are implemented with pMOS devices. The pass-transistor and capacitance in the OLED pixel driver can be used to sample the output of the D/A converter. An additional pMOS is added to OLED pixel driver, which is used to control the D/A converter operating only when one row is on. This can reduce the circuit's power consumption. This driving circuit can work properly in a frame frequency of 50 Hz, and the final layout of this circuit is given. The pixel area is 28.4×28.4 μm2 and the display area is 10.7×8.0 mm2 (the diagonal is about 13 mm). The measured pixel gray scale voltage shows that the function of the driver circuit is correct, and the power consumption of the chip is about 350 mW.     

Method of dissipating heat generated in high-voltage CMOS driver IC

A method of dissipating the heat generated in a high-voltage CMOS driver IC, which is designed for use with a flat panel display, is proposed. It utilises a charge pump circuit to reduce the voltage across the driver IC when its output stages change their status. It can reduce the power consumption and relieve the thermal problems of driver ICs.     

A novel CMOS charge-pump circuit with current mode control 110 mA at 2.7 V for telecommunication systems

This paper presents a novel organization of switch capacitor charge pump circuits based on voltage doubler structures. Each voltage doubler takes a DC input and outputs a doubled DC voltage. By cascading voltage doublers the output voltage increases up to 2 times. A two-phase voltage doubler and a multiphase voltage doubler structures are discussed and design considerations are presented. A simulator working in the Q-V realm was used for simplified circuit level simulation. In order to evaluate the power delivered by a charge pump, a resistive load is attached to the output of the charge pump and an equivalent capacitance is evaluated. To avoid the short circuit during switching, a clock pair generator is used to achieve multi-phase non-overlapping clock pairs. This paper also identifies optimum loading conditions for different configurations of the charge pumps. The proposed charge-pump circuit is designed and simulated by SPICE with TSMC 0.35-μm CMOS technology and operates with a 2.7 to 3.6 V supply voltage. It has an area of 0.4 mm2; it was designed with a frequency regulation of 1 MHz and internal current mode to reduce power consumption.     

A high efficiency all-PMOS charge pump for 3D NAND flash memory

For 3D vertical NAND flash memory, the charge pump output load is much larger than that of the planar NAND, resulting in the performance degradation of the conventional Dickson charge pump. Therefore, a novel all PMOS charge pump with high voltage boosting efficiency, large driving capability and high power efficiency for 3D V-NAND has been proposed. In this circuit, the Pelliconi structure is used to enhance the driving capability, two auxiliary substrate bias PMOS transistors are added to mitigate the body effect, and the degradation of the output voltage and boost efficiency caused by the threshold voltage drop is eliminated by dynamic gate control structure. Simulated results show that the proposed charge pump circuit can achieve the maximum boost efficiency of 86% and power efficiency of 50%. The output voltage of the proposed 9 stages charge pump can exceed 2 V under 2 MHz clock frequency in 2X nm 3D V-NAND technology. Our results provide guidance for the peripheral circuit design of high density 3D V-NAND integration.     

Device and circuit level optimization for high performance a-Si:H TFT-based AMOLED displays

Active matrix organic light-emitting diode (AMOLED) displays with amorphous hydrogenated silicon (a-Si:H) thin-film transistor (TFT) backplanes are becoming the state of art in display technology. Though a-Si:H TFTs suffer from an intrinsic device instability, which inturn leads to an instability in pixel brightness, there have been many pixel driving methods that have been introduced to counter this. However, there are issues with these circuits which limit their applicability in terms of speed and resolution. This paper highlights these issues and provides detailed design considerations for the choice of pixel driver circuits in general. In particular, we discuss the circuit and device level optimization of the pixel driver circuit in a-Si:H TFT AMOLED, displays for high gray scale accuracy, subject to constraints of power consumption, and temporal and spatial resolution.     

电荷泵高端浮动自举式H桥功率驱动电路

提出了一种可以实现极低频甚至是０Ｈｚ下的高压Ｈ桥驱动电路的电荷泵高端浮动自举电路。通过理论分析、仿真和实验。主宰了在保证驱动器的开关速度不变的情况下,该电路能提供稳定物高端浮动电源。同时,对Ｈ桥功率驱动电路中高端浮动自举电路的设计方法也进行了探讨。