基于TMS320DM642的视频解码系统优化

介绍了TMS320DM642数字媒体处理器,并结合该芯片的结构特点,设计实现了MPEG-4视频多路实时解码器。论述了基于DM642媒体处理器的MPEG-4视频多路实时解码器软件系统级优化策略和代码级优化关键技术。测试结果表明,本文提出的优化策略和技术使解码系统在DM642媒体处理器上实现了高质量的多路实时应用。     

媒体处理器协同仿真平台中集成USB接口的研究

分析了USB接口总线和媒体处理器的紧密联系，根据USB接口的规范协议，设计了集成于媒体处理器的USBLLIP核，开发了驱动程序。并在媒体处理器软硬件协同仿真验证平台上验证了USB核和驱动程序的正确性和稳定性。     

一种支持SIMD指令的流水化可拆分乘加器结构

乘加器是媒体数字信号处理器的关键运算部件。该文结合32位数字信号处理器芯片MD32开发（“863”计划）实践，提出了一种流水化可拆分的乘加器硬件实现结构，通过对乘法操作的流水处理实现了200MHz工作频率下的单周期吞吐量指标，通过构造可拆分的数据通道实现了对SIMD乘法指令的支持，支持4个通道16位媒体数据的并行乘法，大大提升了处理器的媒体处理性能。文中对所提出的乘加器体系结构，给出了理论依据和实验结果，通过MD32的流片实现得到了物理验证。     

德州仪器推出实时高清视频转码解决方案

近日．为了使消费者在各种视频终端产品间实现无缝内容传输，德州仪器（TI）推出了一款能够在多种应用间进行视频转码的新型达芬奇技术数字媒体处理器，这些应用包括媒体网关、多点控制设备、数字媒体适配器、视频安全监控DVR．以及IP机顶盒等。新型TMS320DM6467达芬奇处理器是一种基于DSP的片上系统（SoC），特别适合实时多格式高清（HD）视频转码，并配套提供完整的开发工具与数字媒体软件。     

网络处理器简介及其微引擎设计

网络规模的膨胀型增长、用户对宽带需求的急速增加、各种新业务的层出不穷和智能化管理、应用可升级的技术需求催生了网络处理器，形成了以网络处理器为核心的新一代网络设备体系结构。该文简要介绍了网络处理器的定义、结构及其特点，分析了网络处理器设计与通用处理器的主要不同点，着重阐述了网络处理器的核心部分——微引擎的结构和设计重点。     

蓝光品质掌上显 ZiiLABSZMS-08干细胞处理器

11月9日，ZiiLABS发布第三代富媒体应用处理器ZMS-08。ZMS—08将ZiiLABS干细胞计算阵列灵活的多格式媒体处理能力与1GHz的ARMCortex处理器结合在一起，使其性能达到了上一代器件的4倍以上。     

一种基于SIMD结构的可重组乘累加器设计

超高速乘法器是高性能通用微处理器和媒体处理器的重要部件。本文提出一种基于SIMD(Single Lnstrnction multiple Data)高性能并行处理器体系结构的可重组乘累加器及其修正算法，用于音频、视频和网络通信等多媒体数据处理，克服了传统的定长数据处理在多媒体应用方面所固有的局限性，满足了下一代高性能计算的要求。     

异步处理器设计中的关键技术研究

异步处理器解决了传统的同步处理器时钟偏移的问题,具有低功耗和高并行性等优点。本文着重分析了设计异步处理器的关键技术及实现方法,分析比较了当前异步处理器的实现方式,指出了异步处理器的研究方向和重点。并展望了异步处理器技术在媒体处理领域中的应用。异步处理器虽然还没有得到实际的广泛应用,但具有很高的研究价值。     

高清H.264变换编码的流式实现

H.264作为新一代视频编码标准,具有很好的性能,但计算复杂度比较高。Storm处理器是一款面向媒体应用和信号处理的高效能流处理器,在媒体处理方面具有很好的应用前景。针对H.264对计算性能的要求,本文给出了高清H.264(1080P)变换编码在Storm-SP16 G160流处理器上的流式实现。本文根据不同算法的数据流特征,结合具体的流化过程详细介绍了并行粒度选择以及数据流组织、规范化处理等流化技术。实验结果表明:编码的流式实现具有很好的性能,按照此编码效率加速整个程序可满足实时要求。提供了一种不同于硬件加速的程序加速方法,对其他媒体应用在流处理器上的映射具有很大的借鉴意义。     

冠AMD欲与Intel决战消费电子

世界第二大芯片制造商AMD的首席技术官Fred Weber近日向媒体透露，他们将借低能耗、低成本的处理器系列Geode来进一步扩大其x86处理器产量。未来几年里，AMD计划推出一系列为个人媒体播放器，机顶盒等设计的新处理器。而Intel和威盛同样也有类似扩充x86处理器应用范围的计划。AMD首先推出的会是一些功耗较低的新一代全功能Geode芯片，     

Hardware-software interactions on Mpact

Media processors, a new class of processor architectures that combine hardware and software to accelerate multimedia functions concurrently, owe their existence to several computational needs and enabling technologies. In this article, the author discusses the reasons for media processors existence, the implementation of the Mpact media processor, and some examples of the relationship between hardware and software on the Mpact chip     

Challenges to combining general-purpose and multimedia processors

Multimedia processor media extensions to general purpose processors present new challenges to the compiler writer, language designer, and microarchitect. Multimedia workloads have always held an important role in embedded applications, such as video cards or set top boxes, but these workloads are becoming increasingly common in general purpose computing as well. Over the past three years the major vendors of general purpose processors (GPPs) have announced extensions to their instruction set architectures that supposedly enhance the performance of multimedia workloads. These include North Carolina MAX 2 extensions to Hewlett-Packard PA-RISC, MMX for Intel's x86, UltraSparc's VIS, and MDMX extensions to MIPS V. Merging these new multimedia instructions with existing GPPs poses several challenges. Also, some doubt remains as to whether multimedia extensions are a real development or just a competition induced fad in the GPP industry. If it is indeed a development, how must current processor microarchitectures change in reaction? And if they change, can GPPs and MMPs apply application specific integrated circuit (ASIC) solutions to the same problems?     

How multimedia workloads will change processor design

Workloads drive architecture design and will change in the next two decades. For high-performance, general-purpose processors, there is a consensus that multimedia will continue to grow in importance. The authors predict these processors will incorporate more media processing capabilities, eventually bringing about the demise of specialized media processors, except perhaps, in embedded applications. These enhanced general-purpose processor capabilities will arise from multimedia applications that require real-time response, continuous-media data types and significant fine-grained data parallelism     

A holistic approach for tightly coupled reconfigurable parallel processors

New standards in signal, multimedia, and network processing for embedded electronics are characterized by computationally intensive algorithms, high flexibility due to the swift change in specifications. In order to meet demanding challenges of increasing computational requirements and stringent constraints on area and power consumption in fields of embedded engineering, there is a gradual trend towards coarse-grained parallel embedded processors. Furthermore, such processors are enabled with dynamic reconfiguration features for supporting time- and space-multiplexed execution of the algorithms. However, the formidable problem in efficient mapping of applications (mostly loop algorithms) onto such architectures has been a hindrance in their mass acceptance. In this paper we present (a) a highly parameterizable, tightly coupled, and reconfigurable parallel processor architecture together with the corresponding power breakdown and reconfiguration time analysis of a case study application, (b) a retargetable methodology for mapping of loop algorithms, (c) a co-design framework for modeling, simulation, and programming of such architectures, and (d) loosely coupled communication with host processor.     

Evaluation of data-parallel H.264 decoding approaches for strongly resource-restricted architectures

Decoding of an H.264 video stream is a computationally demanding multimedia application which poses serious challenges on current processor architectures. For processors with strongly limited computational resources, a natural way to tackle this problem is the use of multi-core systems. The contribution of this paper lies in a systematic overview and performance evaluation of parallel video decoding approaches. We focus on decoder splittings for strongly resource-restricted environments inherent to mobile devices. For the evaluation, we introduce a high-level methodology which can estimate the runtime behaviour of multi-core decoding architectures. We use this methodology to investigate six methods for accomplishing data-parallel splitting of an H.264 decoder. These methods are compared against each other in terms of runtime complexity, core usage, inter-communication and bus transfers. We present benchmark results using different numbers of processor cores. Our results shall aid in finding the splitting strategy that is best-suited for the targeted hardware-architecture.     

Reconfigurable media processing

Multimedia processing is becoming increasingly important with wide variety of applications ranging from multimedia cell phones to high definition interactive television. Media processing techniques typically involve the capture, storage, manipulation and transmission of multimedia objects such as text, handwritten data, audio objects, still images, 2D/3D graphics, animation and full-motion video. A number of implementation strategies have been proposed for processing multimedia data. These approaches can be broadly classified into two major categories, namely (i) general purpose processors with programmable media processing capabilities, and (ii) dedicated implementations (ASICs). We have performed a detailed complexity analysis of the recent multimedia standard (MPEG-4) which has shown the potential for reconfigurable computing, that adapts the underlying hardware dynamically in response to changes in the input data or processing environment. We therefore propose a methodology for designing a reconfigurable media processor. This involves hardware–software co-design implemented in the form of a parser, profiler, recurring pattern analyzer, spatial and temporal partitioner. The proposed methodology enables efficient partitioning of resources for complex and time critical multimedia applications.     

OMAP平台下H.264的DSP优化

随着嵌入式多核处理器的广泛使用,结合DSP芯片对于数据处理的优势,多媒体应用得到了极大的推广。本文基于OMAP3730芯片的DSP内核,选用开源的X.264编码工程,在移植成功的基础上尝试进行全方位的优化,为后续的应用开发打好基础。     

并行系统的通讯效率问题

巨量并行处理（ＭＰＰ）强调并行系统结构和并行算法的可扩放性。在一个可扩放的并行系统结构上，可扩放的并行算法应该能够有效地利用不断增加的处理机，算法的有效性通常以算法运行时的处理机效率来衡量。一个被普遍忽视的因素是通讯效率，这是一个具有一般性的问题。本文给出了通讯效率的定义，研究了它与处理机效率的关系，并通过对一个典型算法的运行情况分析，研究了几个常见的并行系统结构的通讯效率。本文的结果表明：处理机效率和通讯效率的综合才能全面地评价算法的可扩放性并指导并行系统结构的设计。     

Programmable stream processors

The demand for flexibility in media processing motivates the use of programmable processors. Stream processing bridges the gap between inflexible special-purpose solutions and current programmable architectures that cannot meet the computational demands of media-processing applications. The central idea behind stream processing is to organize an application into streams and kernels to expose the inherent locality and concurrency in media-processing applications. The performance of the Imagine stream processor on these media application is given.     

流处理器技术研究与发展

高性能计算技术在过去十年中不断向前发展,但片外存储、通信延迟等问题一直得不到本质改善,线延迟和功耗问题也越来越突出。高性能计算领域正在寻求能够解决这一问题的新型处理器体系结构。流处理器是在众多新兴的处理器体系结构中发展非常迅速、被学界和业界广泛关注的一种新型处理器,它在数字处理、多媒体以及图像等领域已取取得很好的效果。本文分析了当前流行的几种流处理器,指出了流体系结构在科学计算领域的应用前景和所面临的挑战。