Design of Weaver topology

A novel design based on Weaver topology is proposed. Studies showed that the image-rejection ratio (IRR) performance of the design is insensitive to the phase errors of the LO₁ and the IRR against gain mismatch is inherently about 6 dB superior to the conventional Weaver topology. The design greatly increases the practicality of the Weaver receiver     

Analysis of the behaviours of phase and amplitude mismatch compensators to achieve 82.5 dB image rejection ratio

This article presents an experiment to analyse the behaviour of phase and amplitude mismatch compensators in quadrature receivers. The experiment shows that the input signal level and convergence time affect image rejection ratio (IRR) and signal to noise and distortion ration (SNDR). Based on the findings, design guidelines are suggested and an exceptionally high 82.5 dB IRR is demonstrated in a digital low intermediate frequency (low-IF) Weaver receiver constructed using off-the-shelf components, whereas existing mismatch compensation techniques can only achieve 50 to 65 dB IRR.     

A Discrete-Time Digital-IF Interference-Robust Ultrawideband Pulse Radio Transceiver Architecture

This paper discusses the challenges in ultrawideband pulse radio transceiver design and proposes an architecture operating between 3.1 and 10.6 GHz to address them. The 7.5-GHz band is subdivided into multiple channels of 500 MHz each to relax the requirements for pulse generation, transceiver synchronization, and group-delay flatness. The pulse bases for these channels are stored in digital memories and are used for pulse generation on the transmit side and correlation on the receive side. The transceiver can operate in combination with a fast interferer detector that quickly sweeps through the channels to determine which channels are occupied by large interferers and are thus unsuitable for communication. The all-digital pulse bases allow the transceiver to quickly switch between different channels to avoid interferers without needing multiple or, alternatively, broadband fast-settling phase-locked loops. The frequency plan allows the most critical 802.11 interferers to be pushed to higher frequencies during the first block downconversion where they are attenuated by the low-pass filters of the receiver. The wideband intermediate-frequency correlation architecture significantly relaxes the speed requirement of the digital circuit and the local memories. Several signal-processing techniques to eliminate sampling images in the transmitter as well as spurious image responses in the receiver are also presented. The proposed architecture is digitally intensive and, hence, can take advantage of technology scaling.      

基于RFID的读卡器射频前端硬件设计与实现

首先说明射频识别(RFID)系统结构和关键技术,然后针对无源被动标签的通信原理,给出了915 MHz特高频(UHF)RFID读卡器射频前端的硬件设计方法,包括发送模块、接收模块及锁相环的设计,最后列出射频前端硬件系统的测试方法.结果表明,该设计满足915 MHz频段的读卡器功能需求,且具有性能稳定,效果良好和配置维护灵活的特点.     

Effect of Phase Mismatch on Image Rejection in Weaver Architecture

In a radio frequency receiver, image signals degrade the sensitivity of the receiver for receiving desired signals. This letter analyzes the effect of phase mismatch on image rejection in the Weaver architecture, which has been proposed to reject image signals. Weaver architecture requires the phase difference between the I signal and Q signal of the first and second local oscillators (LOs) to be 90deg. However, the realization of accurate 90deg phase shifters is very difficult. It is found here that an accurate 90deg phase shifter is not essential in Weaver architecture. Instead, by making the phase mismatch between the I and Q signals of the first LO be equal to that of the second LO, image rejection can be performed, being insensitive to the phase mismatch. The reason for this is mathematically analyzed and simulation results are presented     

A low-power all-digital FSK receiver for space applications

A frequency-shift keying (FSK) receiver has been designed for deep space applications which exhibits potential for ultra low power performance. The receiver is based on a novel, almost all-digital architecture. It supports a wide range of data rates and is very robust against large and fast frequency offsets due to Doppler. The architecture utilizes subsampling and 1-bit data processing together with a discrete Fourier transform-based detection scheme to enable power consumption dramatically lower than implementations reported in the literature. Novel and power-efficient algorithms are derived for frequency and timing tracking. Most of the power saving techniques are applicable to a variety of applications, but some are achieved by taking advantage of the asymmetric power constraints for the receiver and the transmitter as well as the absence of adjacent channel interferers. The worst-case bit-error rate (BER) performance of the receiver is just 2.5 dB below that of the optimal uncoded noncoherent FSK receiver at a BER of 10^-6 and better for lower BERs     

GSM transceiver front-end circuits in 0.25-μm CMOS

So far, CMOS has been shown to be capable of operating at radio-frequency (RF) frequencies, although the inadequacies of the device-level performance often have to be circumvented by innovations at the architectural level that tend to shift the burden to the circuit building blocks at lower frequencies, The RF front-end circuits presented in this paper show that excellent RF performance is feasible with 0.25-μm CMOS, even in terms of the requirements of the tried-and-true superheterodyne architecture. Design for low-noise and low-current consumption targeted for GSM handsets has been given particular attention in this paper. Low-noise amplifiers with sub-2-dB noise figures (NFs) and a double balanced mixer with 12.6 dB single-sideband NF, as well as sub-25-mA current consumption for the RF front end (complete receiver), are among the main achievements     

5.2/5.7-GHz 48-dB Image Rejection GaInP/GaAs HBT Weaver Down-Converter Using LO Frequency Quadrupler

A GaInP/GaAs heterojunction bipolar transistor (HBT) down-converter using the Weaver architecture is demonstrated in this paper. The Weaver system is a double-conversion image rejection heterodyne system which requires no bandpass filters in the signal path and no quadrature networks. The Weaver down-converter has the image rejection ratios of 48 dB and 44 dB when the RF frequency is 5.2 GHz and 5.7 GHz, respectively. A new frequency quadrupler is employed in the down-converter to generate the local oscillator (LO) signals. The frequency quadrupler is designed to minimize the phase error when generating LO signals and thus the image rejection performance is improved. A diagrammatic explanation using the complex mixing technique to analyze the image rejection mechanism of the Weaver architecture is developed in this paper. From our analysis, the image rejection can be further improved by making the LO₁ and LO₂ signals coherent     

双波段软件无线电接收机射频前端设计与仿真

射频前端是无线电接收机的重要组成部分,目前常用的超外差结构射频前端虽然性能良好,但结构复杂、不易集成、便携性不高。因此文中从结构出发,采用直接变频的零中频结构设计了一种可以兼容接收短波、超短波射频信号,同时也能达到一般超外差接收机的性能指标的射频前端。并通过multisim软件仿真验证,该设计具备跨波段、高灵敏度、大动态范围等性能特点。     

一种X波段船舶导航雷达射频接收机设计

根据一种X波段船舶导航雷达的总体技术指标,研制了一款与之配套的低噪声镜像抑制射频前端接收机。整个接收机由限幅、低噪声放大、镜像抑制混频三个主要功能模块构成。在研制过程中采取由独立到集成的研制思路,在每个独立模块的性能经测试符合技术指标的基础上再进行整个接收机的集成设计及实验测试,给出了接收机的噪声及链路增益测试曲线。测试结果表明：该射频接收机在9.36 GHz~9.46 GHz频率范围内具有3.6 dB的噪声系数及2.5 dB的链路增益,镜像抑制度达到30 dB,各项性能指标均满足船舶导航雷达使用要求。整个前端模块体积小、成本低,适合民用领域的规模化生产。     

Multiple tone interferers in an FH-MFSK spread spectrum communication system

An analysis of the effect of multiple tone interferers on the bit error rate (BER) in a frequency-hopped multiple frequency shift keying (FH-MFSK) spread spectrum communication is given. A constant insertion rate detection strategy has been considered and a matched tuned filtering used in the receiver. We have obtained results in the 20 MHz (one-way) bandwidth with a data rate of 32 kbit/s and a Rayleigh fading channel. The results show that adequate performance can be achieved even when 40 tone interferers are present with a signal to interference ratio of -10 dB and a signal-to-noise ratio of 25 dB.     

A high IIP2 downconversion mixer using dynamic matching

This paper presents an RF downconversion mixer with improved rejection to second-order intermodulation for RF application within a direct-conversion receiver requiring high input blocking performance. The mixer, implemented in a 2.7-V 0.35-μm BiCMOS process, achieves a second-order input intercept point of at least +72 dBm for a BiCMOS design and at least +66 dBm for an all-CMOS design. The design utilizes dynamic matching to enhance the balance of a fully differential mixer through mitigation of both component and device mismatches. In addition, dynamic matching is shown to improve the mixer's 1/f noise performance. For an all-CMOS mixer design, a 30-dB improvement in the mixer's noise floor at 1 kHz has been observed compared to conventional fully differential CMOS Gilbert-cell mixer. Additionally, background is given on second-order intermodulation and on system IIP2 requirements for a direct-conversion receiver     

Symbol/bit-error rate of LMMSE receiver for M-ary QAM in multipath faded CDMA channels

This letter investigates the performance analysis of a linear minimum mean square error receiver for M-ary quadratic-amplitude modulation in multipath fading channels. Both channel gain variances and instantaneous channel gains of the interferers are considered for receiver implementation. Approximate expressions for symbol and bit error rates are derived only when the receiver knows the channel gain variances of the interferers. In deriving the analytical expressions, we exploit large system analysis and results in single-user multipath combining. The receiver performance and the accuracy of the theoretical results are examined via simulations.     

A Digital Receiver Architecture for Bluetooth in 0.25- μm CMOS Technology and Beyond

A digital receiver architecture for short-range communications systems like Bluetooth is presented. The architecture is tailored to a highly integrated Bluetooth single-chip integrated circuit (IC) and can easily be adapted to other communications systems using a Gaussian frequency-shift keying (GFSK ) modulation scheme. The single-chip IC integrates the complete digital baseband and radio frequency (RF) functionality on a single die and is realized in a 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology targeted for cost efficiency. The superior performance of this digital receiver architecture compared to the state-of-the-art short-range communications receivers is shown. Simulation and measurement results are presented showing a receiver sensitivity of 87 dBm and excellent co-channel and adjacent channel interference performance.     

Calibration of phase and gain mismatches in Weaver image-reject receiver

A modified image-reject Weaver architecture is presented. The design automatically calibrates for phase and gain mismatches that limit the performance of image-reject receivers. On-line or off-line calibrations are possible without using any calibrating tone. An experimental CMOS prototype RF front-end operating at 1.8 GHz achieves an image rejection ratio of 59 dB using on-line calibration. The design was fabricated in a 0.35-/spl mu/m CMOS process and dissipates 160 mW from a 3-V supply during on-line calibration, and 95 mW during normal receiving. The die area is 4 mm/sup 2/.     

先进米波雷达DBF 模拟接收机设计

现代雷达系统对接收机提出了更高的要求,数字化接收机能满足这些要求并已经成为现代雷达、通信等接收系统的一种主流实现方式。文中研究了数字接收机,重点讨论了模拟接收机与数字模块的匹配、增益的计算和分配。根据设计要求,给出了一种模拟接收机详细设计方案,进行了各部分分析计算和详细设计,按照设计方案进行了工程样机研制,调试完成后给出了测试结果。测试结果表明:模拟接收机指标完全满足设计要求,并应用到了样机系统中,且工作稳定可靠。     

雷达接收机的电磁兼容性分析

对于目前广泛使用的超外差式雷达接收机而言,其受到了来自寄生频率的严重干扰,为提高雷达接收机的整机性能,对其进行了电磁兼容性分析。主要针对影响最为严重的镜像干扰进行分析,使用了ADS软件建立了接收机的行为级模型,并分析了镜像干扰下的S参数和频谱。根据仿真结果,使用了合适的EMC整改措施。同时对改善后的接收机在相同条件下进行了仿真和分析,其镜像抑制比有明显提高,整机性能也得到了较大改善,为高性能的接收机设计提供了一种有效的EMC预评估方法。     

Challenges in portable RF transceiver design

As wireless products such as cellular phones become an everyday part of people's lives, the need for higher performance at lower costs becomes even more important. Overcoming the challenges involved in the design of radio-frequency (RF) transceivers can help meet this need. This article provides an overview of RF electronics in portable transceivers and describes design issues as well as current work toward achieving both high performance and low cost. To understand the implications in the design of RF integrated circuits (ICs) we look at the properties of the mobile communications environment. We then study receiver and transmitter architectures and their viability in present IC technologies. An example of an RF transceiver is given and the design of transceiver building blocks is discussed. We conclude by looking at future directions in RF design     

Adaptive Blocker Rejection Continuous-Time $Sigma Delta $ ADC for Mobile WiMAX Applications

An adaptive blocker-rejection wideband continuous-time (CT) sigma-delta (SigmaDelta) analog-to-digital converter (ADC) is presented. An integrated blocker detector reconfigures the ADC loop architecture to avoid overloading in the presence of strong interferers, improving receiver channel selectivity and sensitivity without increasing its dynamic range (DR) requirements. The adaptive operation relaxes receiver baseband channel filtering requirements for a worldwide inter-operability for microwave access (WiMAX, IEEE 802.16e) receiver. The ADC achieves 71 dB of dynamic range (DR), 65 dB of peak SNDR and 68 dB of peak SNR over a 10 MHz signal bandwidth, consuming 18 mW from a 1.2 V supply. The ADC system reconfigures the loop filter topology within 51 mus, improving receiver selectivity without any transient impact on BER. In the blocker suppression mode, the ADC can withstand 30 dBc blocker at the adjacent channel, achieving - 22 dB error vector magnitude (EVM) with a 24 Mb/s 16-QAM signal. The IC is fabricated on a 130 nm 8-level metal, metal-insulator-metal (MIM) capacitor, CMOS technology, occupying 1.5 times 0.9 mm² silicon area.     

Optical heterodyne image-rejection receiver for high-densityoptical frequency division multiplexing system

An optical heterodyne image-rejection receiver (IRR) for high-density optical frequency division multiplexing (OFDM) systems is described. The IRR was realized using balanced receivers, which showed more than 18-dB suppression over the 1.5-3.0-GHz IF region. Measured crosstalk penalties in a two-channel 560 Mb/s differential phase-shift keyed (DPSK) heterodyne optical communication system were realized for the first time. The crosstalk penalties in an OFDM system are estimated theoretically with and without the IRR. The required channel spacing and number of channels that can be accommodated in the 10-nm tuning range of the local laser are presented. A particular configuration of the IRR, its operation, and its performance limitations are discussed. The experimental results for image-rejection reception in a two-channel 560-Mb/s DPSK system are also given. Crosstalk penalties are estimated experimentally and compared to the theoretical calculation. Since the conventional configurations of the IRR are very sensitive to the polarization fluctuation of the transmitted signals, polarization-insensitive IRRs are proposed and their features are considered