Electrical instability in short channel organic thin-film transistors induced by lucky-polaron mechanism

In this work we study the electrical stability under both gate bias stress and gate and drain bias stress of short channel (L = 5 μm) bottom contact/top gate OTFTs made on flexible substrate with solution-processed organic semiconductor and fluoropolymer gate dielectric. These devices show high field-effect mobility (μ_FE> 1 cm²V⁻¹s⁻¹) and excellent stability under gate bias stress (bias stress V_ds = 0V). However, after prolonged bias stress performed at high drain voltage, V_ds, the transfer characteristics show a decreased threshold voltage, degradation of the subthreshold slope and an apparent increase in the field effect mobility. Furthermore, the output characteristics show an asymmetry when measured in forward and reverse mode. These experimental results can be explained considering that the bias stress induces the damage of a small part of the device channel, localized close to the source contact. The analysis of the experimental data through 2D numerical simulations supports this explanation showing that the electrical characteristics after bias stress at high V_ds can be reproduced considering the creation of donor-like interface states and trapping of positive charge into the gate dielectric at the source end of the device channel. In order to explain this degradation mechanism, we suggest a new physical model that, assuming holes injection from the source contact into the channel in bounded polarons, envisages the defect creation at the interface near the source end of the channel induced by injection of holes that gained energy from both the high longitudinal electric fields and the polaron dissolution.     

The electron irradiation effects on silicon gate dioxide used for power MOS devices

The work provides experimental results of high energy electron irradiation effects on silicon dioxide used for power MOS devices. A systematic increase of the threshold voltage has been observed in irradiated IGBT and VDMOS devices processed on Si1 0 0 and Si1 1 1, respectively. The threshold voltage shift has been interpreted as a result of the accumulated charge in the gate oxide. Single event gate rupture has been observed and attributed to the recoil ion interaction with the gate SiO₂. The result has been corroborated by reliability stress tests. After electron irradiation, an increase in breakdown voltage appeared on all devices which was attributed to a change in the surface impact ionisation coefficient. The change is most notable in devices processed on Si substrate with 1 1 1 orientation.     

Effects of high electric field and elevated-temperature bias stressing on radiation response in power VDMOSFETs

The effects of pre-irradiation high electric field and elevated-temperature bias stressing on radiation response of power VDMOSFETs have been investigated. Compared to unstressed devices, larger irradiation induced threshold voltage shift and mobility reduction in high electric field stressed devices have been observed, clearly demonstrating inapplicability of electrical stressing for radiation hardening of power MOSFETs. On the other hand, larger irradiation induced threshold voltage shift in elevated-temperature bias stressed, and more considerable mobility reduction in unstressed devices have been observed, confirming the necessity of performing the radiation qualification testing after the reliability screening of these devices. The underlying changes of gate oxide-trapped charge and interface trap densities have been calculated and analysed in terms of the mechanisms responsible for pre-irradiation stress effects.     

Investigation of the effect of temperature during off-state degradation of AlGaN/GaN High Electron Mobility Transistors

AlGaN/GaN High Electron Mobility Transistors were found to exhibit a negative temperature dependence of the critical voltage (V_CRI) for irreversible device degradation to occur during bias-stressing. At elevated temperatures, devices exhibited similar gate leakage currents before and after biasing to V_CRI, independent of both stress temperature and critical voltage. Though no crack formation was observed after stress, cross-sectional TEM indicates a breakdown in the oxide interfacial layer due to high reverse gate bias.     

Improvement in gate breakdown voltage for SOS devices

It was attempted to improve low gate breakdown voltage for an air-isolated SOS devices, employing ion-beam etching technology for silicon-island formation. Gate breakdown origin was clarified with SEM observation. As a result, it has been found that 1) low gate breakdown voltage for air-isolated SOS devices is caused by thinner gate oxide at the bottom of a steep silicon-island edge, and 2) ion-beam etching with the ion-beam incident angle over 40° allows the silicon island to have a sidewall angle under 35°, thus resulting in uniform gate oxide thickness. Consequently, the gate breakdown voltage for the air-isolated SOS devices can be improved to as high as that for dielectric isolated SOS devices.     

Physical analysis of hard and soft breakdown failures in ultrathin gate oxides

The physical analysis of the ultrathin gate oxides (33 and 25 Å) after the electrical stressing, under constant voltage stress, reveals that the damage is not only limited to the oxide layer, but also to the entire gate structure. The hard breakdown failure makes catastrophic damage to the structure, whereas the analysis of soft breakdown failure reveals many of the hidden damages in the device structure. In Ti-silicided structures, the predominant failure mechanism is Ti migration to form a leakage path, as well as localized re-crystallisation of poly-Si or Si substrate near to the gate oxide. Co migration is so far not seen in Co-silicided devices. However, even for the very low current compliance levels and devices which do not show any electrical degradation after the SBD stress, localized epitaxy formation in the gate or Si substrate is observed, which could be a reliability concern.     

Junction leakage current degradation under high temperature reverse-bias stress induced by band-defect-band tunnelling in power VDMOS

A deep analysis of the intrinsic junction and surface currents in power vertically diffused MOS devices with sub-micrometer channel length and thin gate oxide has been carried on after a typical reliability high temperature reverse bias (HTRB) stress. A reference set of gated diodes has also been examined in order to better understand the onset and evolution of post-stress leakage degradation. A comparison among complete MOSs, single body diodes and enriched diodes allows to highlight the role played by the point defectivity both at gate interface and in the bulk silicon close to the junction surface. We found that the typical interface defects involved in the leakage degradation are shallow traps and can be de-populated simply by a thermally activated mechanism. More specifically, the main degradation mechanism relies to band-defect-band tunneling localized at the surface drain/body junction where an intrinsic n-i-p region evolves due to a bird’s beak lateral profile of the body diffusion. We have demonstrated that the most important contribution to the activation of the precursor defect sites is given by the transverse electrical field that develops just below the SiO₂/Si interface within the n-i-p region during the stress.     

Impact of gate placement on RF power degradation in GaN high electron mobility transistors

We have investigated the RF power degradation of GaN high electron mobility transistors (HEMTs) with different gate placement in the source–drain gap. We found that devices with a centered gate show different degradation behavior from those with the gate placed closer to the source. In particular, centered gate devices degraded through a mechanism that has a similar signature as that responsible for high-voltage DC degradation in the OFF state and is likely driven by electric field. In contrast, offset gate devices under RF power stress showed a large increase in source resistance, which is not regularly observed in DC stress experiments. High-power pulsed stress tests suggest that the combination of high voltage and high current stress maybe the cause of RF power degradation in these offset-gate devices.     

High temperature electro-optical degradation of InGaN/GaN HBLEDs

This paper presents a study of the high temperature degradation of high brightness light emitting diodes (HBLEDs) on gallium nitride. Two different families of devices, from two leading manufacturers, have been submitted to thermal stress: during treatment, the optical and electrical characteristics of the devices have been analyzed. Degradation modes detected after stress have been (i) operating voltage increase, (ii) output power decrease, (iii) modifications of the spectral properties. The degradation of the electrical and optical characteristics of the devices were found to have different kinetics: this fact indicates that optical power (OP) loss is not strongly related to the degradation of the electrical parameters of the LEDs. On the other hand, spectral analysis indicated that OP loss is strongly related to the decrease of the phosphors-related yellow emission band. Microscopic analysis showed that this effect can be ascribed to the carbonization of the package and phosphorous material. A degradation of the transparency of the top-side ohmic contact has been also detected after stress: these mechanisms are thought to be responsible for the detected OP decrease. OP decay process has been found to be thermally activated, with activation energy equal to 1.5 eV.     

Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs)

Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied in this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO₂-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

Electrical degradation and recovery of dielectrics in n-poly-Si/SiOx/SiO2/p-sub structures designed for application in low-voltage non-volatile memories

In this paper we study the degradation and recovery of dielectrics in n⁺⁺-poly-Si/SiO_x/SiO₂/p-sub capacitors designed for application in low-voltage flash EEPROM memories. Constant current stress experiment have been performed and the gate voltage in the Fowler–Nordheim (FN) regime and the flat-band voltage monitored. Experiment demonstrated that SiO_x has a greater tendency to trap electrons than pure SiO₂ and exhibits a larger voltage shift in the FN regime after electrical stress. On the other hand, permanent recovery of the leakage current can be obtained by injection of current at very low flux. This effect has been tentatively explained with the annealing of native metastable defects occurring in concurrence with the stress induced creation of new traps.     

Gate protection of MIS devices

Gate shorts caused by electrical breakdown of the gate dielectric are a major yield and reliability problem for MOS transistors and integrated circuits. Diodes or diffused resistors with breakdown voltages of about 40 V can be used to protect the gate from high voltage transients or static discharges. This paper provides a uniform approach to gate protection. It is shown theoretically that in order to obtain effective gate protection: the protecting device should have a low dynamic resistance in breakdown; the breakdown voltage of the protecting device should be above, but close to, the maximum gate operating voltage; and protection by a diffused resistor in series with the gate is much more effective than by a diode in parallel with the gate. It is shown experimentally that, compared to the widely used fieldplate-induced breakdown, breakdown due to reach-through to a highly doped substrate provides: a dynamic resistance that is almost two orders of magnitude lower; reasonable control of the breakdown voltage; much better protection against simulated static discharges. Since under pilot line conditions no adverse effects on performance or yield have been observed, reach-through breakdown devices seem to improve gate protection decisively without any coincident disadvantages.     

热载流子应力下p-MOSFETs在低栅电压范围的统一退化模型

研究了低栅电压范围的热载流子统一退化模型.发现对于厚氧化层的p-MOSFETs主要退化机制随应力电压变化而变化,随着栅电压降低,退化机制由氧化层俘获向界面态产生转变,而薄氧化层没有这种情况,始终是界面态产生;此外退化因子与应力电压成线性关系.最后得出了不同厚度的p-MOSFETs的统一退化模型,对于厚氧化层,退化由电子流量和栅电流的乘积决定,对于薄氧化层,退化由电子流量决定.     

Surface‐Modified High‐k Oxide Gate Dielectrics for Low‐Voltage High‐Performance Pentacene Thin‐Film Transistors

In this study, pentacene thin‐film transistors (TFTs) operating at low voltages with high mobilities and low leakage currents are successfully fabricated by the surface modification of the CeO₂–SiO₂ gate dielectrics. The surface of the gate dielectric plays a crucial role in determining the performance and electrical reliability of the pentacene TFTs. Nearly hysteresis‐free transistors are obtained by passivating the devices with appropriate polymeric dielectrics. After coating with poly(4‐vinylphenol) (PVP), the reduced roughness of the surface induces the formation of uniform and large pentacene grains; moreover, –OH groups on CeO₂–SiO₂ are terminated by C₆H₅, resulting in the formation of a more hydrophobic surface. Enhanced pentacene quality and reduced hysteresis is observed in current–voltage (I–V) measurements of the PVP‐coated pentacene TFTs. Since grain boundaries and –OH groups are believed to act as electron traps, an OH‐free and smooth gate dielectric leads to a low trap density at the interface between the pentacene and the gate dielectric. The realization of electrically stable devices that can be operated at low voltages makes the OTFTs excellent candidates for future flexible displays and electronics applications.     

An advanced MOS-IC process technology using local oxidation ot oxygen-doped polysilicon films

An O-POS (oxygen-doped polysilicon) film, deposited directly on silicon, is oxidized locally to create an active gate area. The electrical properties for the active gate area are the same as conventional p- and n-channel MOS devices, but the field area has an extremely high threshold voltage for both p- and n-type silicon substrates. The electrical properties in metal/oxidized O-POS/silicon and metal/oxide/O-POS/silicon structures have been investigated while varying the O-POS film thickness, oxygen concentration, local oxidation time, and silicon substrate resistivity. According to these basic studies, it is proposed that the high density of trapping centers existing in O-POS film is responsible for the high field threshold voltage. A applications of this process technology, a silicon-gate CMOS integrated circuit, and a high voltage n-channel MOS device are discussed.     

Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study

The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO₂ based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated.     

Impact of ESD protection device trigger transient on the reliability of ultra-thin gate oxide

Common ESD protection devices have a snapback characteristic similar to a silicon-control rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. In this work, it is demonstrated that the defect generation mechanism in oxide during electrical stress remains unchanged in the sub-nanosecond stress regime. As a result, the voltage transient can create far more defects in the gate oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.     

Effect of fluorinated silicate glass passivation layer on electrical characteristics and dielectric reliabilities for the HfO2/SiON gate stacked nMOSFET

The superior characteristics of the fluorinated hafnium oxide/oxynitride (HfO₂/SiON) gate dielectric are investigated comprehensively. Fluorine is incorporated into the gate dielectric through fluorinated silicate glass (FSG) passivation layer to form fluorinated HfO₂/SiON dielectric. Fluorine incorporation has been proven to eliminate both bulk and interface trap densities due to Hf-F and Si-F bonds formation, which can strongly reduce trap generation as well as trap-assisted tunneling during subsequently constant voltage stress, and results in improved electrical characteristics and dielectric reliabilities. The results clearly indicate that the fluorinated HfO₂/SiON gate dielectric using FSG passivation layer becomes a feasible technology for future ultrathin gate dielectrics applications.     

Realization of electrically stable organic field-effect transistors using simple polymer blended dielectrics

Organic field-effect transistors (OFETs) were fabricated using polymer blended gate dielectrics in an effort to enhance the electrical stability against a gate bias stress. A poly(melamine-co-formaldehyde) acrylated (PMFA) gate dielectric layer with great insulating properties was blended with polypentafluorostyrene (PFS), a type of hydrophobic fluorinated polymer. Although the overall electrical performance dropped slightly due to the rough and hydrophobic surfaces of the blend films, at the blend ratio (10%), the OFET’s threshold voltage shift under a sustained gate bias stress applied over 3 h decreased remarkably compared with an OFET based on a PMFA dielectric alone. This behavior was attributed to the presence of the hydrophobic and electrically stable PFS polymer, which provided a low interfacial trap density between the gate dielectric and the semiconductor. A stretched exponential function model suggested that the energetic barrier to create trap states was high, and the distribution of energetic barrier heights was narrow in devices prepared with PFS.