CMOS low-voltage operational amplifiers with constant-gm rail-to-rail input stage

Two 3.3-V operational amplifiers with constant-g _m rail-to-rail input stage and rail-to-rail output stage are presented. The constant transconductance (g _m ) ensures a constant unity-gain frequency within the whole commonmode input range. Two new methods to control theg _m are introduced. Both operational amplifiers use the same rail-to-rail output stage. The operational amplifiers have been integrated in a CMOS semicustom process with transistor lengths of 10µm. The common-mode input voltage swing extends beyond the positive supply rail by 400 mV and beyond the negative supply rail by 200 mV. The output voltage is able to reach within 130 mV of the supply rails. The output current of the operational amplifiers is 2 mA and the voltage gain is 85 dB. The unity-gain frquency is 165 kHz, which is mainly limited by the relatively long transistor lengths of 10µm. In another process with channel lengths of 2µm, simulation results showed that a unity-gain frequency of 4 MHz can easily be obtained.     

一种恒跨导轨对轨CMOS运算放大器的设计

设计了一种新颖的恒跨导轨对轨CMOS运算放大器结构。输入级采用轨对轨的结构,在输入级采用4个虚拟差分对管来对输入差分对的电流进行限制,使运放的输入级跨导在工作范围内保持恒定。输出级采用前馈式AB类输出结构,以使输出达到全摆幅。仿真结果显示,在5 V电源电压和带有10 pF电容与10 kΩ电阻并联的负载下,该运放在共模输入范围内实现了恒跨导,在整个共模输入范围内跨导变化率仅为3%,输出摆幅也达到了轨对轨全摆幅,运放的开环增益为108.5 dB,增益带宽积为26.7 MHz,相位裕度为76.3°。     

基于最小电流选择的运算放大器设计

设计了一种工作电压为3V恒跨导满幅CMOS运算放大器,针对轨对轨输入级中存在的跨导不恒定和简单AB类输出级性能偏差这2个问题,提出了利用最小电流选择电路来稳定输入级的总跨导;浮动电流源控制的无截止前馈AB类输出级实现了运放的满幅输出,同时减小了交越失真。该电路通过HSpice进行仿真验证,在0～3V输入共模范围内,输入级跨导的变化小于3.3%,开环增益为93dB,单位增益带宽为8MHz,相位裕量为66°。     

An Adaptive Biased Single-Stage CMOS Operational Amplifier with a Novel Rail-to-Rail Constant-<Emphasis Type="Italic">g</Emphasis><Subscript><Emphasis Type="Italic">m</Emphasis></Subscript> Input Stage

Using rail-to-rail (R-R) swing analog circuits has become almost mandatory in the design of low supply voltage circuits. In this paper, a new architecture for constant-g_m rail-to-rail input stages is presented. The design features a less than 5% deviation in g_m over the entire range of the input common-mode voltage. Furthermore, a new structure for folded cascode amplifier based on the use of a floating current source is presented. By employing these techniques, a low-power operational amplifier (op-amp) with 100 MHz unity-gain bandwidth, 106 dB gain, 60^∘ phase margin, 2.65 V swing, and 6.4 nV/✓Hz input-referred noise with rail-to-rail input common-mode range is realized in a 0.8 μ m CMOS technology. This amplifier dissipates 10 mW from a 3 V power supply.     

1-V Rail-to-Rail CMOS OpAmp With Improved Bulk-Driven Input Stage

This paper introduces a CMOS operational amplifier with rail-to-rail input and output voltage ranges, suitable for operation in extremely low-voltage environments. The approach is based on a bulk-driven input stage with extended input common-mode voltage range, in which the effective input transconductance is enhanced by means of a partial positive feedback loop. As a result, a gain and gain-bandwidth product performance similar to that of an amplifier using a gate-driven approach is obtained. Output rail-to-rail operation is achieved by means of a push-pull stage, which is biased in class-AB by using a static feedback loop, thus avoiding frequency limitations inherent in dynamic-feedback tuning schemes. The proposed two-stage operational amplifier was designed to operate with a 1-V supply, and a test chip prototype was fabricated in 0.35-mum standard CMOS technology. The experimental performance features an open-loop DC gain higher than 76 dB and a closed-loop unity-gain bandwidth above 8 MHz when a 1-MOmegapar17-pF load is connected to the amplifier output     

1-V operational amplifier with rail-to-rail input and output ranges

A bipolar operational amplifier (OA) with rail-to-rail input and output ranges which can operate at supply voltages down to 1 V is presented. At this supply voltage, the input offset voltage is typically 1.0 mV in an input common-mode voltage range that extends beyond both supply rails for about 300 mV, with a common-mode rejection ratio (CMRR) between 38 and 100 dB, depending on conditions. The output voltage can reach both supply rails within 100 mV, the output current is limited to ±10 mA, the voltage gain is 100 dB, and the bandwidth is 450 kHz. The die is 2.5×5.5 mm². Qualities such as offset, input-bias current, and CMRR are improved when the supply voltage is increased and the dynamic level shift is autonomically turned off. The OA has been protected against unintentional reversal of the output signal when the inputs are substantially overdriven. The output stage of the circuit consists of two full complementary composite transistors, whose HF characteristics have been improved by internal Miller compensation and linearization of the transconductance     

Input/Output Rail-to-Rail CMOS Operational Amplifier with Shaped Common-Mode Response

This paper presents an input/output rail-to-rail class-AB CMOS operational amplifier with reduced variations in unity-gain frequency over the entire voltage range. The rail-to-rail amplifier input stage is based on two parallel-connected complementary differential pairs. Variations in the small-signal response are kept to a minimum by realizing an adequate shaping of the CM response of the input stage, while still reducing deviations in the total limiting current of the two input pairs with respect to traditional solutions. This is achieved independently of the g _m -I _D characteristic of the amplifier input devices and of any strict matching condition between the complementary input pairs. Experimental results from a 3-V 0.8-m CMOS test-chip are given.     

Rail-to-rail BiCMOS operational amplifier using input signal adapters with floating outputs

An operational amplifier with rail-to-rail input and output voltage range in 0.6 μm BiCMOS technology is presented. Two simple input signal adapters with floating outputs serving as pre-stages are introduced. They are followed by a differential amplifier. The adapters translate the input signals into a floating level within the operating region of the differential amplifier, enabling rail-to-rail operation. An inverter-based simple rail-to-rail class AB output stage has been used. With a single supply of 1.5 V, the proposed rail-to-rail operational amplifier achieves 72 dB DC open-loop gain, 2.54 MHz unity-gain frequency, 62° phase margin, 2.5 V/μs slew rate, and 147 μW power consumption.     

Class AB CMOS amplifiers with high efficiency

A new class AB CMOS operational-amplifier principle is presented. A transconductance amplifier based on this principle exhibits small-signal characteristics comparable to those of a conventional OTA. It has, however, a superior current efficiency and its settling time is not slew-rate limited. The new class AB principle can also be used in an output stage with a well-defined quiescent current, a rail-to-rail output swing, and a good driving capability. A two-stage amplifier with both the input and output stages based on the new principle has been realized. It features a rail-to-rail input and output common-mode range, a gain-bandwidth of 370-kHz, a settling time of less than 5 μs independent of the applied step, and a power consumption of 247 μW. It drives a resistive load of 3 kΩ in parallel with a capacitive load of 400 pF when operated on a 2.5-V/-2.5-V power supply     

Low-voltage micropower super class AB CMOS OTA

Novel class AB OTA topologies result from the combined use of local common-mode feedback and class AB input stages. They can operate at low supply voltage and feature very low static power consumption, bandwidth enhancement, and very high slew rate. Measurement results of a 0.5 /spl mu/m CMOS prototype show slew rate and unity-gain bandwidth enhancement factors of 180 and 4.5, respectively, compared to a conventional one-stage OTA.     

0．6VCMOS轨至轨运算放大器

为适应低压低功耗设计的应用,设计了一种超低电源电压的轨至轨CMOS运算放大器。采用N沟道差分对和共模电平偏移的P沟道差分对来实现轨至轨信号输入．。当输入信号的共模电平处于中间时,P沟道差分对的输入共模电平会由共模电平偏移电路降低,以使得P沟道差分对工作。采用对称运算放大器结构,并结合电平偏移电路来构成互补输入差分对。采用0．13μm的CMOS工艺制程,在0．6V电源电压下,HSpice模拟结果表明,带10pF电容负载时,运算放大器能实现轨至轨输入,其性能为：功耗390μw,直流增益60dB,单位增益带宽22MHz,相位裕度80°。     

Constant-g/sub m/ constant-slew-rate high-bandwidth low-voltage rail-to-rail CMOS input stage for VLSI cell libraries

This paper introduces a general-purpose low-voltage rail-to-rail input stage suitable for analog and mixed-signal applications. The proposed circuit provides, simultaneously, constant small-signal and large-signal behaviors over the entire input common-mode voltage range, while imposing no appreciable constraint for high-frequency operation. In addition, the accuracy of the circuit does not rely on any strict matching of the devices, unlike most of the traditional approaches based on complementary input pairs, which need to compensate for the difference in mobility between electrons and holes with the transistor aspect ratios. Also, the technique is compatible with deep submicrometer CMOS devices, where the familiar voltage-to-current square law in saturation is not completely satisfied. Based on the proposed input stage, a transconductor with rail-to-rail input common-mode range and an input/output rail-to-rail operational amplifier were developed. Both cells were designed to operate with a 3-V single supply and fabricated in standard 0.8-/spl mu/m CMOS technology. Experimental results are provided.     

Compact CMOS constant-gm rail-to-rail input stage with gm-control by an electronic zener diode

A family of compact CMOS rail-to-rail input stages with constant-g _m is presented. To attain a constant-g_m over the whole common-mode input range, an electronic zener diode is inserted between the tails of the complementary input pairs. This zener keeps the sum of the gate-source voltages of the input pairs, and therefore the g _m of the rail-to-rail input stage, constant. Two possible implementations of the zener have been realized and inserted in a rail-to-rail input stage. These input stages are implemented in two two-stage compact amplifiers. Both amplifiers have been realized in a 1 μm BiCMOS process. They have a unity-gain frequency of 2-MHz, for a capacitive load of 20 pF     

A family of high-swing CMOS operational amplifiers

A family of high-swing CMOS operational amplifiers has been developed to maximize the available dynamic range with low supply voltages. Complementary differential pairs are used to achieve an almost rail-to-rail input common-mode voltage range. High linearity is obtained by summing currents so that the small-signal differential-mode voltage gain is constant over the entire input common-mode range. With a 5.0-V power supply, the total harmonic distortion is typically only 1% in a unity-gain configuration with a 4.5-V_p-p signal. The measured DC offset voltages versus input common-mode range track between the conventional and high-swing versions. These measurements suggest that the commonly feared crossover distortion may not be a problem when the current summation high-swing topology is used. The measured step response characteristics were excellent and exhibited no signs of phase mismatch crossover distortion for high-frequency signals     

Some Design Aspects of a Two-Stage Rail-to-Rail CMOS Op Amp

A two-stage low-voltage CMOS op amp with rail-to-rail input and output voltage ranges is presented. The circuit uses complementary differential input pairs to achieve the rail-to-rail common-mode input voltage range. The differential pairs operate in strong inversion, and the constant transconductance is obtained by keeping the sum of the square roots of the tail currents constant. Such an input stage has an offset voltage which depends on the common input voltage level, resulting in a poor common-mode rejection ratio. Therefore, special attention has been given to the reduction of the op amp's systematic offset voltage. Gain-boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain, but also to provide a significant reduction of the systematic offset voltage.     

A rail-to-rail CMOS op amp

A CMOS op amp (operational amplifier) is reported which has a rail-to-rail voltage range at its input as well as its output. An area-efficient output stage has been used. While the entire op amp occupies only 600 mil², when used as a unity-gain buffer and with ±5-V supplies, the op amp can drive a 9-V_pp/1-kHz sine wave across a 300-Ω load with -64 dB of harmonic distortion     

The design of fully differential CMOS operational amplifiers without extra common-mode feedback circuits

A new fully differential CMOS operational amplifier (op amp) without extra common-mode feedback (CMFB) circuit is proposed and analyzed. In this op amp, simple inversely connected current-mirror pairs are used as active loads. From the theoretical analysis, it is shown that the common-mode signal can be efficiently suppressed by the reduced effective common-mode resistance of the active load. The proposed op amp with 2 pF capacitance loadings has an open-loop unity-gain bandwidth of 63 MHz, a phase margin 47°, and a dc gain of 67 dB in 3.5µm p-well CMOS technology. The common-mode gain at a single output node can be as low as —38 dB without extra CMFB circuit. Experimental results have successfully confirmed the capability of the efficient common-mode rejection.This work was supported by the United Microelectronics Corporation (UMC), Republic of China, under Grant C80054.     

Constant-Gm rail-to-rail common-mode rangeinput stage with minimum CMRR degradation

The inherent drawbacks associated with CMOS amplifiers with rail-to-rail input common-mode range (CMR) are addressed. It is shown how they impact on the amplifier and limit its performance. An input stage, suitable to be incorporated in the design of any amplifier topology with extended input range, is introduced. By controlling the bias current level as a function of the input common-mode voltage, the input stage provides simultaneously an almost constant total transconductance and over 18 dB of common-mode rejection ratio (CMRR) improvement in comparison to the classical approach with just 5 V of total supply voltage. Experimental results obtained from the evaluation of a prototype chip fabricated in a standard CMOS p-well process with 2-μm feature size are given     

一种恒跨导CMOS运算放大器的设计

设计了一种宽带轨对轨运算放大器,此运算放大器在3.3 V单电源下供电,采用电流镜和尾电流开关控制来实现输入级总跨导的恒定。为了能够处理宽的电平范围和得到足够的放大倍数,采用用折叠式共源共栅结构作为前级放大。输出级采用AB类控制的轨对轨输出。频率补偿采用了级联密勒补偿的方法。基于TSMC 2.5μm CMOS工艺,电路采用HSpice仿真,该运放可达到轨对轨的输入/输出电压范围。     

Current mode instrumentation amplifier with rail-to-rail input and output

This paper presents the results from an investigation on the implementation of Current Mode Instrumentation Amplifiers (CMIAs) with rail-to-rail operational amplifiers (op amp) with a gm control circuit. The objective of employing rail-to-rail op amps in the implementation of a CMIA is the improvement of the common-mode operation range. The enhancement of the input common mode range (ICMR) is obtained using op amps with a rail-to-rail input stage followed by a cascode-based output stage. A prototype of the CMIA was implemented in standard 0.6 μm XFAB CMOS technology. Test results showed that the CMIA common mode range was extended but with moderated CMRR. To minimize this issue the amplifier was re-designed and sent to fabrication. Simulations with the components variations included were performed and showed the enhancement of the CMRR can be expected.